Embedded and Cyber-physical Systems Group

Scheduling Approaches for

Accelerating Real-Time Tasks
in Software Hardware Co-
Design Paradigm
Prof. Amlan Chakrabarti
IEEE Computer Society, Distinguished Speaker
University of Calcutta, India
Email: [email protected]

Connect 2023
Organised By: IEEE Bangalore Section
 Introduction
• Embedded systems are computing systems with tightly coupled hardware and
software integration.
• Designed to perform dedicated function
• Real-time embedded systems are defined as those systems in which the
correctness of the system depends not only on the logical result of computation,
but also on the time at which the results are produced.
Example:
Airbag sensory system in Automobiles
RTS RTEMB EMB “--- this thing will probably have to work
only once in 10 years, but it better work
then, otherwise you might die.”
 FPGA Basics
• The term FPGA stands for Field Programmable
Gate Array and, it is a one type of
semiconductor logic chip which can be
programmed (fully and partially) to become
almost any kind of system or digital circuit
• The general FPGA architecture consists of three
types of modules
• Configurable logic blocks (CLB)
• Switch Matrix/ Interconnection Wires
• I/O blocks or Pads
• The ability to configure the FPGA’s CLBs into
hundreds or thousands of identical processing
blocks has applications in image processing,
artificial intelligence (AI), data center hardware
accelerators

Image Source: National Instruments

 Target Platforms
 Reconfigurable systems combine the
benefits of flexibility of general purpose
processors along with the performance
GPP
efficiency of a dedicated hardware
 Reconfigurable systems are increasingly

?
Flexibility

being employed in a large class of

Reconfigurable today’s real-time embedded systems
Platforms  Example: Avionic systems, Automotive
applications, object tracking etc. (Gracia
et al. , 2011)
ASIC

Performance
 FPGA SoCs as Hardware Task Processing Engines

Intel’s latest FPGA family, Agilex. Source: Intel

Xilinx’s Versal family. Source: Xilinx

(a) Standard FPGA based Cloud Environment (b) FPGA in Cloud

Real-Time Tasks
 Real Time Tasks
• In a Real-Time System the correctness of the system behavior depends not only on the logical results of the
computations, but also on the physical instant at which these results are produced

Healthcare Autonomous Vehicles Surveillance

Military Application Augmented Reality

Process Automation
 Challenges in RT Scheduling in FPGAs
• The periodic real time scheduling algorithms can’t directly be employed for reconfigurable systems due to its
architectural constraints

• All timing constraints should be met while taking care of the reconfiguration overheads and also allowing
efficient resource utilization

Slotted 1D Flexible 1D

Slotted 2D Flexible 2D
Scheduling Periodic Hard Real-Time
Task Sets on Fully and Partially
Reconfigurable Platforms
 Assumptions
 Processing elements Identity: The reconfigurable platform is assumed to be equipartitioned into
m homogeneous tiles

 Task Independence: Tasks are independent and hard real time

 Task Unity: Tasks run on one tile at a time

 Overhead: Context switch overhead (Full and partial reconfiguration overhead)

Deadline Partition Approach

Levin et al. (2011) proposed DP-Fair optimal scheduling algorithm for general purpose
processors. Each task should be executed proportional to its weight upto the deadline boundaries.
10
 DPSPR Working Principle
• DPSPR (Deadline Partitioning Scheduler for Partially Reconfigurable
Systems)
• Context switching not a global event
• Localized to individual partitions
• Partial reconfiguration overhead is low than full reconfiguration over
head
• Tasks are allocated in any order starting from 1st tile
• Such that sum of task shares along with the reconfiguration over head is
less than tslr
 Example:
• Consider same task set as that of DPSFR
• shr1= shr2= shr3= shr6=24, shr4= 49, shr5=48 and sum_shr=193, tprg=1ms
•
 Performance Evaluation
• The performance of DPSFR and DPSPR evaluated using simulation based experiments
• Task weight and periods have been taken from normal distribution
• The principal performance metric used TRR=µ/N ×100
• Total number of task rejected per total number of task arrived

DPSFR

DPSFR: TRR Vs WL
DPSFR can achieve fair resource utilization up to 80% with TRR less than 10% and DPSPR can utilize resource
up-to 90% with 1%TRR [Published in IEEE ESL, Vol 7, Page: 23-26]
Co-scheduling Persistent Periodic and
Dynamic Aperiodic
Real-Time Tasks on Reconfigurable
Platforms
 Introduction
• Scheduling for a set of safety critical persistent periodic tasks along with
less critical dynamic aperiodic tasks
• Guarantee the execution of all critical periodic tasks and execute arbitrarily
arriving aperiodic tasks utilizing residual system capacity
• Follows Offline Online approach.
• Offline- generate periodic schedule and maintain free resource.
• Online- Utilize that resource to schedule aperiodic tasks.
• DPCS-FR (Deadline Partitioning Combined Scheduler for Fully
Reconfigurable Systems)
• DPCS-PR (Deadline Partitioning Combined Scheduler for Partially
Reconfigurable Systems)
Data Structure for DPCS-FR Offline
• The information stored corresponding to
the rth node Stsr of the circular linked
list is as follows:
• 1. Time-slice length: tslr
• 2. Each node schir in SCH contain the
following information:
• Number of frames per tile: Cir
• Frame size: Gir
• # of free frames: FFir
• #frames needed for each task
Tj P: PRFi,jr
• Link to next node SLir 
• 3. Start time of the time-slice: t r
CLLS • 4. Pointer to next node: Linkr
 Example:
• Considering a run-time partially reconfigurable scenario, let us again take the same 4-tile
platform. The hypothetical FPGA under consideration has a full reconfiguration overhead
of tfrg = 6 ms and partial reconfiguration overhead tprg = 2 ms (6/4 ~ 2 ms).
• The shares to be executed within this time slice is shr 1= shr3= shr5= 8 and shr2= shr4= 12 and
sum_shr= 96
• Ta1 arrives at 60, with ea1=13, da1=83 and Ta2 arrives at 67 with ea2=12, da2=81.

Slack in ts2
After allocation of aperiodic task
 Experimental Results (Contd..)

DPCS-FR is able to limit task rejection rates below 15% while

simultaneously providing system utilizations as high as 60% on
fully reconfigurable systems. On partially reconfigurable
systems, DPCS-PR performs even better achieving system
utilizations up to 90% with task rejection rates below 13%.

This work published as: Sangeet Saha et al. “Co-scheduling Persistent

Periodic and Dynamic Aperiodic Real-Time Tasks on Recongurable
Platforms", IEEE Transactions on Multi-Scale Computing Systems (TMSCS),
April, 2017, doi:10.1109/TMSCS.2017.2691701 PU=40%, daavg = 0.5 × HP
Spatio-Temporal Scheduling of Preemptive
Real-Time Tasks on Partially
Reconfigurable Systems
 How this work differs??

• The floor of the FPGA is statically partitioned into M equi-sized Partially

Reconfigurable Regions (PRRs) V1, V2,..., VM
• Each such PRR is capable of concurrently hosting multiple tasks of any
arbitrary size and allows an individual task to be placed anywhere within the
PRR, in compliance with the flexible 2D area model
• Using this model, we have proposed a hybrid offline-online periodic real-
time scheduling and placement methodology named SPORTS (Semi-
Partition Oriented Reconfigurable-sysTems Scheduler and placer)
System Model & Scheduling Scenario

 All task reconfigurations within a PRR are

restricted to always occur at the same time
Each of the M PRRs may be reconfigured
as a unit autonomously and independent of
other PRRs in the system
Task execution within a PRR proceeds
frame by frame with PRR-wide partial
reconfigurations (having overhead tpr) at
frame boundaries
 Results

SPORTS Vs Existing Works

TRR vs Utilization
 U = 80%, while SPORTS only rejects 8% tasks on average, EDF-NF [Guan et al 10] rejects 35% tasks and EDF-FkF
rejects 50% tasks
 For a given maximum number of allowed clusters (say, K = 3), higher skewness among tasks cause a larger number of
task rejections primarily due to higher internal fragmentation within the rectangular region into which a task is placed
Results
• It can be observed that in general runtime
overheads monotonically increase as the number
of tasks become higher with higher values of U
• Runtime overhead also increases with increase
of K and σsz
• SPORTS is able to limit task rejection rates
below 9% even under workloads as high as 90%

Sangeet Saha, Arnab Sarkar, Amlan Chakrabarti. “Spatio-

Temporal Scheduling of Preemptive Real-Time Tasks on
Partially Reconfigurable Systems", in ACM Transactions on
Design Automation of Electronic Systems (TODAES), 22(4):
71:1-71:26 (2017).
 Scheduling and Placement of
Dependent Hardware Tasks on
Partially Reconfigurable Systems
 Introduction
• In certain applications, computational activities cannot be executed in arbitrary order but
have to respect some precedence relations defined at the design stage
• Such precedence relations are usually described through a directed acyclic graph DAG,
where tasks are represented by nodes and each task has a distinct execution time
• Precedence relations are represented by the edges among nodes i.e output of a given
node becomes the input of a node

DAG
 Challenges
• Tasks must be managed efficiently in time and space to exploit the advantages
offered by the FPGA
• To achieve the objective the scheduler must be able to handle all the following
requests:
 what task to load at what time (temporal reconfiguration) ?
where to place the task (spatial reconfiguration) ?
 when to start the execution of a task according with its precedence constraints
(temporal scheduling) ?
 ILP based Formulation
• Objectives: Minimize the Total Schedule Length
• Constraints:
Each task has an unique loading time through ICAP Port
Each task has an unique start time after loading in FPGAs
All tasks have to be loaded before it can start its execution
All loaded tasks (executing or non-executing) consumed an area in the floor of the FPGA
 Task dependency constraints must be satisfied
 The ICAP port can load at most one task at any given time

• We have formulated the ILP version of the problem and solved it. As per the
outcome of the ILP solution obtained in offline, our task graphs will be scheduled
on that way in online
 Scheduling and Placement of
Dependent Hardware Tasks on
Partially Reconfigurable Systems

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 Tasks with Multiple Versions

• Hardware task could have multiple

hardware variants (variation in
throughput) based upon its spatial
requirements
• Tasks with more resources execute faster

• We have to chose the correct version of

the task

• Area Vs Execution time trade-off!!!

Example: ASAP Schedule

30
Example: ALAP Schedule

31
Application Use Cases
Energy-aware application management strategy for FPGA-based IoT-
Cloud environments

• Publications:
• Atanu Majumder, Sangeet Saha, Amlan
Chakrabarti, Klaus D. McDonald-Maier: Energy-
Aware Real-Time Tasks Processing for FPGA-
Based Heterogeneous Cloud. IEEE Trans.
Sustain. Comput. 7(2): 414-426 (2022).

• Atanu Majumder, Sangeet Saha, Amlan

Chakrabarti: EAAM: Energy-aware application
management strategy for FPGA-based IoT-
Cloud environments. J. Supercomput. 76(12)

33
High Speed Fault tolerant System Design
for High Energy Physics Applications
• Publications:
• S Mandal, J Saini, WM Zabołotny, S Sau, A
Chakrabarti, S Chattopadhyay: An FPGA-Based
High-Speed Error Resilient Data Aggregation and
Control for High Energy Physics Experiment.
IEEE Transactions on Nuclear Science 64 (3),
933-944(2017).

• S Mandal, S Sarkar, WM Ming, A Chattopadhyay,

A Chakrabarti: Criticality aware soft error
mitigation in the configuration memory of SRAM
based FPGA. 32nd International Conference on
VLSI Design and 2019 18th International
Conference on Embedded Systems (VLSID),2019

34
Energy Efficient Scheduling of Real-Time Tasks in Heterogeneous
Multi-core Systems and Cloud

• Publications:
• Kalyan Baital and Amlan Chakrabarti, “Dynamic Scheduling of Tasks for Multi-core
Real Time Systems based on Optimum Energy and Throughput”, IET Computers &
Digital Techniques, Vol.13, No.2, pp.93-100, 2019.

• Kalyan Baital and Amlan Chakrabarti, "Dynamic Scheduling of Real-Time Tasks in

Heterogeneous Multicore Systems", IEEE Emb Sys Letters, Vol. 11 (1) pp. 29-32,
2019.

• Kalyan Baital and Amlan Chakrabarti, "An Efficient Dynamic Scheduling of Tasks for
Multi-core Real Time Systems", Advances in Computing Applications, Springer,pp.
31 - 47, 2016.

• Kalyan Baital, Amlan Chakrabarti, B. Chatterjee, S. Holst and X. Wen, “Power and
Energy Safe Real-Time Multi-core Task Scheduling”, in Proc. 35th Intl Conf on VLSI
Design and 21st Intl Conf on Emb. Sys. (VLSID), Bangalore, India, 2022, pp. 16-21.
Error Resilient SRAM-Based
Reconfigurable Computing Platform
• Publications:
• Swagata Mandal; Amlan Chakrabarti; Srinivasu
Bodapati: Clustered Error Resilient SRAM-Based
Reconfigurable Computing Platform. IEEE trans.
on aerospace and electronic system, 57(3): 1768 –
1779(2021).
• S Mandal, R Paul, S Sau, A Chakrabarti, S
Chattopadhyay: A novel method for soft error
mitigation in FPGA using modified matrix code.
IEEE Embedded Systems Letters 8 (4), 65-
68(2016)
• S Mandal, R Paul, S Sau, A Chakrabarti, S
Chattopadhyay: Efficient dynamic priority based
soft error mitigation techniques for configuration
memory of FPGA hardware. Microprocessors and
Microsystems 51, 313-330(2017).
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 Detection of unknown cipher using fault
injection techniques

Publication:
Arijit Tewary, Swagata Mandal, Amlan Chakrabarti, Debasri Saha, and Avishek Adhikari: Differential Fault Analysis of Trivium Using
Artificial Neural Network on SoC Platform, 5 th International symposium on Devices, Circuit and systems , 2022. 37
Self-aware Embedded Hardware Design using FPGAs for mitigating threats like Hardware Trojans,
Side-Channel, Fake IPs
Main Focus: Development of Self Aware Hardware Agents for Runtime Security
Key Contributions: Publications:
• Development of Security Algorithms based on the security activities exhibited by different species of nature • Krishnendu Guha, Atanu Majumder, Debasri Saha, Amlan Chakrabarti      :
Criticality based reliability against hardware Trojan attacks for processing of
• Development of Self Aware Agents (SAAs) that works based on the Observe-Decide-Act (ODA) paradigm tasks on reconfigurable hardware. Microprocess. Microsystems 71 (2019)      
that: • Krishnendu Guha      , Debasri Saha, Amlan Chakrabarti      :
Stigmergy-Based Security for SoC Operations From Runtime Performance
• Bypasses Confidentiality Attacks in SoC platforms Degradation of SoC Components. ACM Trans. Embed. Comput. Syst. 18(2)
• Counteracts Integrity Attacks for in SoC platforms : 14:1-14:26 (2019)
• Krishnendu Guha      , Debasri Saha, Amlan Chakrabarti      :
• Mitigates Availability Attacks in SoC platforms
Real-Time SoC Security against Passive Threats Using Crypsis Behavior of
• Authenticates reconfigurable intellectual properties in remote FPGA platforms Geckos. ACM J. Emerg. Technol. Comput. Syst. 13(3): 41:1-41:26 (2017)
• Krishnendu Guha, Debasri Saha, Amlan Chakrabarti      :
Zero Knowledge Authentication for Reuse of IPs in Reconfigurable
Platforms. TENCON 2019: 2040-2045
• Krishnendu Guha      , Atanu Majumder, Debasri Saha, Amlan Chakrabarti
     :
Reliability Driven Mixed Critical Tasks Processing on FPGAs Against
Hardware Trojan Attacks. DSD 2018: 537-544
• Krishnendu Guha      , Debasri Saha      , Amlan Chakrabarti      :
SARP: Self Aware Runtime Protection Against Integrity Attacks of Hardware
Trojans. VDAT 2018: 198-209
• Krishnendu Guha      , Sangeet Saha, Amlan Chakrabarti      :
SHIRT (Self Healing Intelligent Real Time) Scheduling for Secure
Embedded Task Processing. VLSID 2018: 463-464
• Krishnendu Guha      , Debasri Saha, Amlan Chakrabarti      :
Self Aware SoC Security to Counteract Delay Inducing Hardware Trojans at
Runtime. VLSID 2017: 417-422
• Krishnendu Guha      , Debasri Saha, Amlan Chakrabarti      :
RTNA: Securing SOC architectures from confidentiality attacks at runtime
using ART1 neural networks. VDAT 2015: 1-6    
• Krishnendu Guha      , Romio Rosan Sahani, Moumita Chakraborty, Amlan
Chakrabarti      , Debasri Saha:
Analysis of Secret Key Revealing Trojan Using Path Delay Analysis for Some
Cryptocores. FICTA (2) 2014: 13-20
Self-Aware Strategies for FPGAs on Cloud
Key Focus: Develop Security based Scheduling Approaches via Self Aware Runtime Agents
Publications:
Key Contributions • Krishnendu Guha, Atanu Majumder, Debasri Saha, 
• Analyse threats to real time tasks for FPGA based Cloud Platforms Amlan Chakrabarti:
Dynamic power-aware scheduling of real-time tasks for
• Develop criticality based reliability security based scheduling at runtime FPGA-based cyber physical systems against power
draining hardware trojan attacks. J. Supercomput. 76(11)
: 8972-9009 (2020)
• Krishnendu Guha, Amlan Chakrabarti:
Criticality based Reliability from Rowhammer Attacks in
Multi-User-Multi-FPGA Platform. VLSID 2022: 234-239
• Krishnendu Guha, Amlan Chakrabarti, Krishna Paul, 
Biswadeep Chatterjee:
Criticality based Reduction of Security Costs in a FPGA
based Cloud Computing Farm. VLSID 2021: 264-269
• Krishnendu Guha, Debasri Saha, Amlan Chakrabarti:
Blockchain Technology Enabled Pay Per Use Licensing
Approach for Hardware IPs. DATE 2020: 1618-1621
• Krishnendu Guha, Atanu Majumder, Debasri Saha, 
Amlan Chakrabarti:
Ensuring Green Computing in Reconfigurable Hardware
based Cloud Platforms from Hardware Trojan Attacks. 
TENCON 2020: 1380-1385
• Krishnendu Guha, Debasri Saha, Amlan Chakrabarti:
A Multi-Agent Co-operative Model to Facilitate
Criticality based Reliability for Mixed Critical Task
Execution on FPGA based Cloud Environment. 
VLSID 2020: 143-148
New Domains
Test-Aware Scheduling of Real-Time Tasks in Multi-core Systems

• The objective is to improve the overall reliability of multi-core

embedded real-time systems by enabling a health aware task
scheduling where each core of the system is tested with a
confidence level of 99%.
• We propose a way to optimally schedule the periodic tests to
maximize the overall reliability of the system, preserving
important and independent qualities of service (QoS)
parameters of task scheduling.
• We have developed our own simulator for estimating the
effectiveness of the proposed model in the light of all the QoS
parameters.

• Communicated:
• K. Baital, B. Chatterjee, A. Chakrabarti, S. Holst and X. Wen,
“QoS Peserving Test-Aware Scheduling of Real-Time Tasks in
Multicore Systems”.
 Embedded and Cyber-physical Systems Group

Reconfigurable Computing for Edge

• We are using reconfigurable edge devices in different domain like biomedical, agriculture etc.

Architecture of Multi-Sensor Fusion used in agriculture Heartbeat classification using two-stage RF classifier
42
 Embedded and Cyber-physical Systems Group

Open RISC based Embedded Applications

• We are working on open RISC based SoC design for various applications like computer vision, image
processing.
• We are working on development of custom instruction set using RISCV based instruction to enhance the
acceleration of deep learning network on reconfigurable platform,

Basic workflow for AI based Accelerator on

AI accelerator centric System on Chip RISCV based SoC 43
 Embedded and Cyber-physical Systems Group

Key Areas of Research

• Enabling FPGA as the Driver for Real-Time Tasks (Supported By TCS)
• Developing a scheduling platform based on Offline and Online Strategies and harnessing the Power of FPGAs through full and partial reconfiguration
• Energy Aware FPGA Processing for Cloud Platforms
• Custom FPGA hardware Design for Mission Critical Tasks (Supported by DAE & DST)
• Error Control and Fault Tolerance
• Hardware Cryptography
• Hardware Software Co-design for Real-Time Signal Processing (Speech, Audio and Video)
• Self-Aware Strategies for Threat Mitigation in Critical Applications (DST & Intel india)
• Self-aware Embedded Hardware Design using FPGAs for mitigating threats like Hardware Trojans, Side-Channel, Fake IPs
• Self-Aware Strategies for FPGAs on Cloud
• Fault aware & Secured Task Processing (Supported DAE & DRDO)
• How to Combat Fault Injections?
• Design of Efficient Error Detection & Correction Strategies
• Multicore Embedded Systems
• Scheduling for Heterogeneous Tasks
• Low Energy and Test Aware Approaches Architecture and Scheduling
• New Domains
• Reconfugurable Computing for Edge
• Open RISC based Embedded Applications
 Group Members:
Graduated Students

Dr. Sangeet Saha, Dr Swagata Mandal,

Dr. Suman Sau, Dr. Rourab Paul, Dr. Kalyan Baital,
Asst. Prof. Univ. of Essex, UK Asst. Prof. Jalpaiguri Govt.
Asst. Prof. Siksha Anusandhan Asst. Prof. Siksha Anusandhan Scientist D, NIELIT,, Kolkata
University University Engineering College

Collaborators:

Dr. Krishnendu Guha Prof. Juergen Becker Dr. Arnab Sarkar, Assoc. Prof. Mr. Biswadeep Chatterjee Prof. Xiaoqing Wen
Asst. Prof. Univ. of Cork, Ireland Head of the Institute ITIV, KIT, IIT Kharagpur Associate V.P. HCLTech KyuTech.,Japan
Germany
08/17/2023 46