William Stallings

Computer Organization
and Architecture
8th Edition

Chapter 3
Top Level View of Computer
Function and Interconnection
Program Concept
• Hardwired systems are inflexible
• General purpose hardware can do
different tasks, given correct control
signals
• Instead of re-wiring, supply a new set of
control signals
Program Concept
• Hardwired systems are inflexible
What is a program?
• A sequence of steps
• For each step, an arithmetic or logical
operation is done
• For each operation, a different set of
control signals is needed
Basic Programme Code
Function of Control Unit
• For each operation a unique code is
provided
—e.g. ADD, MOVE
• A hardware segment accepts the code and
issues the control signals

• We have a computer!
Components
• The Control Unit and the Arithmetic and
Logic Unit constitute the Central
Processing Unit
• Data and instructions need to get into the
system and results out
—Input/output
• Temporary storage of code and results is
needed
—Main memory
Computer Components:
Top Level View
Instruction Cycle
• Two steps:
—Fetch
—Execute
Fetch Cycle
• Program Counter (PC) holds address of
next instruction to fetch
• Processor fetches instruction from
memory location pointed to by PC
• Increment PC
—Unless told otherwise
• Instruction loaded into Instruction
Register (IR)
• Processor interprets instruction and
performs required actions
Execute Cycle
• Processor-memory
—data transfer between CPU and main memory
• Processor I/O
—Data transfer between CPU and I/O module
• Data processing
—Some arithmetic or logical operation on data
• Control
—Alteration of sequence of operations
—e.g. jump
• Combination of above
Hypothetical Machine
Example of Program Execution
Instruction Cycle State Diagram
Interrupts
• Mechanism by which other modules (e.g.
I/O) may interrupt normal sequence of
processing
• Program
—e.g. overflow, division by zero
• Timer
—Generated by internal processor timer
—Used in pre-emptive multi-tasking
• I/O
—from I/O controller
• Hardware failure
—e.g. memory parity error
Program Flow Control
Interrupt Cycle
• Added to instruction cycle
• Processor checks for interrupt
—Indicated by an interrupt signal
• If no interrupt, fetch next instruction
• If interrupt pending:
—Suspend execution of current program
—Save context
—Set PC to start address of interrupt handler
routine
—Process interrupt
—Restore context and continue interrupted
program
Transfer of Control via Interrupts
Instruction Cycle with Interrupts
Program Flow Control
Program Timing
Short I/O Wait
Program Flow Control
Program Timing
Long I/O Wait
Instruction Cycle (with Interrupts) -
State Diagram
Multiple Interrupts
• Disable interrupts
—Processor will ignore further interrupts whilst
processing one interrupt
—Interrupts remain pending and are checked
after first interrupt has been processed
—Interrupts handled in sequence as they occur
• Define priorities
—Low priority interrupts can be interrupted by
higher priority interrupts
—When higher priority interrupt has been
processed, processor returns to previous
interrupt
Multiple Interrupts - Sequential
Multiple Interrupts – Nested
Time Sequence of Multiple Interrupts

(Interrupt
service
routine)
Connecting
• All the units must be connected
• Different type of connection for different
type of unit
—Memory
—Input/Output
—CPU
PCI Express bus card slots (from top to bottom: x4, x16, x1 and
x16), compared to a traditional 32-bit PCI bus card slot
(bottom). (PCI = Peripheral Component Interconnect)
Computer Modules
Memory Connection
• Receives and sends data
• Receives addresses (of locations)
• Receives control signals
—Read
—Write
—Timing
Computer Modules
Input/Output Connection(1)
• Similar to memory from computer’s
viewpoint
• Output
—Receive data from computer
—Send data to peripheral
• Input
—Receive data from peripheral
—Send data to computer
Input/Output Connection(2)
• Receive control signals from computer
• Send control signals to peripherals
—e.g. spin disk
• Receive addresses from computer
—e.g. port number to identify peripheral
• Send interrupt signals (control)
Computer Modules
CPU Connection
• Reads instruction and data
• Writes out data (after processing)
• Sends control signals to other units
• Receives (& acts on) interrupts
Buses
• There are a number of possible
interconnection systems
• Single and multiple BUS structures are
most common
• e.g. Control/Address/Data bus (PC)
• e.g. Unibus (DEC-PDP)
What is a Bus?
• A communication pathway connecting two
or more devices
• Usually broadcast
• Often grouped
—A number of channels in one bus
—e.g. 32 bit data bus is 32 separate single bit
channels
• Power lines may not be shown
Bus Interconnection Scheme
Data Bus
• Carries data
—Remember that there is no difference between
“data” and “instruction” at this level
• Width is a key determinant of
performance
—8, 16, 32, 64 bit
Address bus
• Identify the source or destination of data
• e.g. CPU needs to read an instruction
(data) from a given location in memory
• Bus width determines maximum memory
capacity of system
—e.g. 8080 has 16 bit address bus giving 64k
address space

—2 16
= 2 10 X 2 6
= 2 6 X 2 10
= 64 k
Control Bus
• Control and timing information
—Memory read/write signal
—Interrupt request
—Clock signals
Bus Interconnection Scheme
Big and Yellow?
• What do buses look like?
—Parallel lines on circuit boards
—Ribbon cables
—Strip connectors on mother boards
– e.g. PCI
—Sets of wires
Bus
Physical Realization of Bus Architecture
Single Bus Problems
• Lots of devices on one bus leads to:
—Propagation delays
– Long data paths mean that co-ordination of bus use
can adversely affect performance
– If aggregate data transfer approaches bus capacity
• Most systems use multiple buses to
overcome these problems
Traditional (ISA – Industry Standard Architecture )
(with cache)
High Performance Bus
Bus Types
• Dedicated
—Separate data & address lines
• Multiplexed
—Shared lines
—Address valid or data valid control line
—Advantage - fewer lines
—Disadvantages
– More complex control
– Ultimate performance
Bus Arbitration
• More than one module controlling the bus
• e.g. CPU and DMA controller
• Only one module may control bus at one
time
• Arbitration may be centralised or
distributed
Centralised or Distributed Arbitration
• Centralised
—Single hardware device controlling bus access
– Bus Controller
– Arbiter
—May be part of CPU or separate
• Distributed
—Each module may claim the bus
—Control logic on all modules
Timing
• Co-ordination of events on bus
• Synchronous
—Events determined by clock signals
—Control Bus includes clock line
—A single 1-0 is a bus cycle
—All devices can read clock line
—Usually sync on leading edge
—Usually a single cycle for an event
Synchronous Timing Diagram
Asynchronous Timing – Read Diagram
Asynchronous Timing – Write Diagram
Point-to-Point Interconnect

At higher and higher data

Principal reason for change
rates it becomes
was the electrical
increasingly difficult to
constraints encountered
perform the
with increasing the
synchronization and
frequency of wide
arbitration functions in a
synchronous buses
timely fashion

A conventional shared bus

on the same chip magnified
Has lower latency, higher
the difficulties of increasing
data rate, and better
bus data rate and reducing
scalability
bus latency to keep up with
the processors
+Quick Path Interconnect
QPI
 Introduced in 2008
 Multiple direct connections

 Direct pairwise connections to other components

eliminating the need for arbitration found in shared
transmission systems
 Layered protocol architecture

 These processor level interconnects use a layered

protocol architecture rather than the simple use of
control signals found in shared bus arrangements
 Packetized data transfer

 Data are sent as a sequence of packets each of

which includes control headers and error control
codes
 Multicore
Configuration
Using
QPI

QPI - quick path

interconnect
PCI – peripheral
component interconnect
 QPI Layers

Flit – flow control unit (flow control digit)

Phit – physical unit of information transfer
Physical Interface of the Intel QPI
Interconnect
QPI Multilane Distribution
+
QPI Link Layer
• Flow control function
• Performs two key — Needed to ensure that a
sending QPI entity does
functions: flow control not overwhelm a receiving
and error control QPI entity by sending data
faster than the receiver
— Operate on the can process the data and
level of the flit clear buffers for more
incoming data
(flow control unit)
— Each flit consists of
a 72-bit message
• Error control function
payload and an 8-
bit error control — Detects and recovers
code called a cyclic from bit errors, and so
redundancy check isolates higher layers
(CRC) from experiencing bit
errors
 QPI Routing and Protocol Layers
Routing Layer Protocol Layer

• Used to determine the • Packet is defined as the

course that a packet unit of transfer
will traverse across the • One key function
available system performed at this level is a
interconnects cache coherency protocol
• Defined by firmware which deals with making
sure that main memory
and describe the
values held in multiple
possible paths that a caches are consistent
packet can follow • A typical data packet
payload is a block of data
being sent to or from a
cache
PCI Bus
• Peripheral Component Interconnection
• Intel released to public domain
• 32 or 64 bit
• 50 lines
PCI Expresss Configuration
PCIe Protocol Layers
PCIe Protocol layers

• Physical: Actual wires carrying the signals, and

circuitry and logic to support the transmission and
receipt of the 1s and 0s.
• • Data link: Responsible for reliable transmission
and flow control. Data packets Data Link Layer
Packets (DLLPs).
• • Transaction: Generates and consumes data packets
for load/store data transfer mechanisms, manages the
flow control of packets between the two components
on a link. Data packets are called Transaction Layer
Packets (TLPs).
PCIe Multilane Distribution

round robin
 The Transaction Layer supports four
+ address spaces:

• Memory • I/O
— The memory space includes — This address space is used
system main memory and for legacy Peripheral
PCIe I/O devices Component Interconnect
— Certain ranges of memory (PCI) devices, with reserved
addresses map into I/O address ranges used to
devices address legacy I/O devices

• Configuration • Message
— This address space — This address space is
enables the TL to for control signals
read/write configuration related to interrupts,
registers associated error handling, and
with I/O devices power management
 PCIe
Protocol
Data
Unit
Format
TLP Memory Request Format
 Summary
• Computer —Point-to-point
components interconnect
— QPI physical layer
• Computer function
— QPI link layer
— Instruction fetch and
— QPI routing layer
execute
— QPI protocol layer
— Interrupts
— I/O function —PCI express
• Interconnection — PCI physical and
structures logical architecture
— PCIe physical layer
• Bus interconnection
— PCIe transaction layer
— Bus structure
— PCIe data link layer
— Multiple bus hierarchies
— Elements of bus design