Very-large-scale integration (VLSI)

Process of combining thousands of transistors into a single chip.

(started in the 1970s)

• In 1965, Gordon Moore, an industry pioneer, predicted that

the number of transistors on a chip doubles every 18 to 24
months. He also predicted that semiconductor technology
will double its effectiveness every 18 months and many other
factors grow exponentially.
• Jack St. Clair Kilby was an American electrical engineer who took
part (along with Robert Noyce) in the realization of the
first integrated circuit while working at Texas Instruments (TI) in
1958.
• He was awarded the Nobel Prize in Physics on December 10, 2000.
The first IC
 The first planar IC

• In 1960, Noyce invented the planar integrated

circuit.
• The industry preferred Fairchild's invention over
Texas Instruments' because the transistors in planar
ICs were interconnected by a thin film deposit,
whereas Texas Instruments' invention required fine
wires to connect the individual circuits.
 The first MOSFET
• The first MOSFET was invented by Mohamed Atalla and 
Dawon Kahng at Bell Labs in 1959, and demonstrated in
early 1960.

• MOS devices were later commercialized by Fairchild in 1964,

with p-channel devices for logic and switching applications.

• During the early 1970s, MOS integrated circuit technology

enabled the very large-scale integration (VLSI) of more than
10,000 transistors on a single chip
 Transistors’ Logic gates’
Name Year
number number

small-scale
1964 1 to 10 1 to 12
integration (SSI)
medium-scale
1968 10 to 500 13 to 99
integration (MSI)
large-scale
1971 500 to 20,000 100 to 9,999
integration (LSI)
very large scale 20,000 to 10,000 to
1980
integration (VLSI) 1,000,000 99,999
Ultra large scale 1,000,000 and 100,000 and
1984
integration (ULSI) more more
 Technology nodes

The technology node (also process node, process technology or simply node)

refers to a specific semiconductor manufacturing process and its design rules.
Fabrication
 Fabrication process sequence
1.Silicon manufacture
2.Wafer processing
3.Lithography
4.Oxide growth and removal
5.Diffusion and ion implantation
6.Annealing
7.Silicon deposition
8.Metallization
9.Testing
10.Assembly and packaging
 1.Silicon manufacture

• Crystal Growth : Czochralski Method

Seed

Single Crystal Silicon

Quartz Crucible

Water Cooled Chamber

Heat Shield

Carbon Heater

Graphite Crucible

Crucible Support

Spill Tray

Electrode
 Polysilicon Ingot

RF Coil
• An alternative process is the float
zone process which can be used for
refining or single crystal growth.
Single Crystal Si

• After crystal pulling, the

boule is shaped and cut into
wafers which are then
polished on one side.

(See animations of crystal polishing etc. at

http://www.memc.com/co-as-process-animation.asp)
13
 2. Wafer Preparation

Level 1 Contamination Reduction: Clean Factories

• Air quality is measured by the

“class” of the facility.
Level 2 Contamination Reduction: Wafer Cleaning

• RCA clean is “standard process”

used to remove organics, heavy
metals and alkali ions.

• Ultrasonic agitation is used to

dislodge particles.
Level 3 Contamination Reduction: Gettering
 3.Lithography

Historical Development and Basic Concepts • Patterning process consists

of mask design, mask
fabrication and wafer
Electron Light printing.
Gun Source
Condenser
Lens
Focus Mask • It is convenient to divide the
Deflection wafer printing process into three
Reduction
Lens parts A: Light source, B. Wafer
Mask Wafer
exposure system, C. Resist.
CAD System
• Layout
• Simulation
• Design Rule Checking
Mask Making Wafer Exposure • Aerial image is the pattern of
optical radiation striking the top
of the resist.

• Latent image is the 3D replica

produced by chemical processes
in the resist.
 Wafer Exposure Systems
1:1 Exposure Systems Usually 4X or 5X
Reduction

Light
Source

Optical • Three types of

System
exposure systems
have been used.
Mask Gap
Photoresist
Si Wafer

Contact Printing Proximity Printing Projection Printing

• Contact printing is capable of high resolution but has unacceptable defect

densities.
• Proximity printing cannot easily print features below a few µm (except for
x-ray systems).
• Projection printing provides high resolution and low defect densities and
dominates today.
• Typical projection systems use reduction optics (2X - 5X), step and repeat or step
and scan mechanical systems, print ≈ 50 wafers/hour and cost $10 - 25M.
 Photoresists

• Positive Photoresist
• Negative Photoresist
Thermal Oxidation
 Properties of SiO2
Thermal SiO2 is amorphous. SiO2
Weight Density = 2.20 gm/cm3
Molecular Density = 2.3E22 molecules/cm3

Crystalline SiO2 [Quartz] = 2.65 gm/cm3 <Si>

(1) Excellent Electrical Insulator

Resistivity > 1E20 ohm-cm Energy Gap ~ 9 eV

(2) High Breakdown Electric Field

> 10MV/cm

(3) Stable and Reproducible Si/SiO2 Interface

 Properties of SiO2 (cont’d)
(4) Conformal oxide growth on exposed Si surface SiO2

Thermal
Oxidation

Si Si

(5) SiO2 is a good diffusion mask for common dopants

Dsio2  Dsi e.g. B, P, As, Sb.
*exceptions are Ga
(a p-type dopant) and some
SiO2 metals, e.g. Cu, Au

Si
Thermal Oxidation of Silicon
Dry Oxidation

Si  O2  S i O2

Wet Oxidation

S i  2 H 2O  S i O2  2 H 2

Growth Occurs 54% above and

46% below original surface as
silicon is consumed
 Thermal Oxidation Equipment

Horizontal Furnace

Vertical Furnace
 Kinetics of SiO2 growth

Oxidant Flow
(O2 or H2O)

Gas Diffusion Gas Flow

Stagnant Layer
Solid-state SiO2
Diffusion

SiO2 Si-Substrate
Formation
Silicon consumption during oxidation
Si SiO2 2.17 mm
1mm
Si

1mm Si oxidized 2.17 mm SiO2

N ox molecular density of SiO2

X si  X ox  atomic density of Si
N si

2.3  10 22 molecules / cm 3
 X ox  22 3
 0.46 X ox
5  10 atoms / cm
The Deal-Grove
stagnant
Model of Oxidation
CG layer
Cs SiO2 Si

Note
Cs  C o Co
Ci

X0x
F1 F2 F3

gas diffusion reaction

transport flux flux
flux through SiO2 at interface
 F: oxygen flux – the number of oxygen molecules that crosses a plane of a
certain area in a certain time
The Deal-Grove Model of Oxidation (cont’d)
CG
stagnant
layer
Cs SiO2 Si

Note
Note
CCs CCo Co
s o
Ci

X0x

F1 F2 F3

F1  hG  CG  CS 
Mass transfer coefficient [cm/sec].
C
F2   D “Fick’s Law of Solid-state Diffusion”
x
 C  Ci 
 D   o 
 X ox 
Diffusivity [cm2/sec]
F3  k s  Ci
Oxidation reaction rate constant

EE143 - Ali Javey

 Diffusivity: the diffusion coefficient
 E 
D  DO exp  A 
 kT 

E A  activation energy
k = Boltzmann' s constant = 1.38 x10 -23 J/K
T = absolute temperatu re

EE143 - Ali Javey

The Deal-Grove Model of Oxidation (cont’d)
CG
stagnant
layer
Cs SiO2 Si

Note
Note
CCs CCo Co
s o
Ci

X0x

F1 F2 F3

• CS and Co are related by Henry’s Law

• CG is a controlled process variable (proportional to the input

oxidant gas pressure)
Only Co and Ci are the 2 unknown variables
which can be solved from the steady-state condition:
F1 = F2 =F3 ( 2 equations)

EE143 - Ali Javey

The Deal-Grove Model of Oxidation (cont’d)
CG
stagnant
layer
Cs SiO2 Si

Note
Note
CCs CCo Co
s o
Ci

X0x

F1 F2 F3

Co  H  Ps Henry’s Law

Henry’s partial pressure of oxidant

constant at surface [in gaseous form].
 H  kT  C s  from ideal gas law PV= NkT

C
Co
s 
HkT
EE143 - Ali Javey
Solution: Oxide Thickness Regimes
   
A  t   
X ox   1  2   1
2 A  
  4B  

(Case 1) Large t [ large Xox ]

X ox  Bt
(Case 2) Small t [ Small Xox ]
B
X ox  t
A

EE143 - Ali Javey

Thermal Oxidation Example
Graphical Solution

(b) The total oxide thickness at the end

of the oxidation would be 0.5 mm
which would require 1.5 hr to grow
if there was no oxide on the surface
to begin with. However, the wafer
“thinks” it has already been in the
furnace 0.4 hr. Thus the additional
time needed to grow the 0.3 mm
oxide is 1.5-0.4 = 1.1 hr.

EE143 - Ali Javey

Thermal Oxidation Example
Mathematical Solution

(a) From Table 3.1,

2
2   1.23  m B   2.00  m
B = 7.72 x10 exp   3.71x10 6 exp  X i  25nm
 kT  hr A  kT  hr
m 2 B m
For T = 1373 K, B = 0.0236 and  0.169
hr A hr


0.025m 
2

0.025m
 0.174 hr
m 2
 m
0.0236 0.169
hr hr

t=
0.2 m 
2

0.2 m
 0.174hr  2.70 hr
m 2 0.169 m
0.0236
hr hr

EE143 - Ali Javey

Thermal Oxidation Example
Mathematical Solution

(b) From Table 3.1,

2
  0.78  m
2 B 7   2.05  m
B = 3.86 x10 exp   9. 70 x10 exp   Xi  0
 kT  hr A  kT  hr
m 2 B m
For T = 1273 K, B = 0.314 and  0.742
hr A hr


0.2 m 
2

0.2m
 0.398 hr
m 2
m
0.314 0.742
hr hr

t=
0.5m 2 
0.5m
 0.398hr  1.07 hr
m 2 m
0.314 0.742
hr hr

EE143 - Ali Javey

 Local Oxidation of Silicon (LOCOS)
Standard process suffers for Fully recessed process attempts
significant bird’s beak to minimize bird’s beak

EE143 - Ali Javey

LOCOS process steps: 
I. Preparation of silicon substrate 
II. CVD deposition of SiO2, pad/buffer oxide 
III. CVD deposition of Si3N4, nitride mask 
IV. Etching of nitride layer and silicon oxide
layer 
V. Thermal growth of silicon oxide 
VI. Further growth of thermal silicon oxide 
VII. Removal of nitride mask LOCOS process
materials: 
1) Si, silicon substrate 
2) SiO2, pad/buffer oxide, chemical vapor
deposition silicon oxide 
3) Si3N4, nitride mask 
4) SiO2, isolation oxide, thermal oxide
 4.Oxide growth and removal

• SiO2 and the Si/SiO2 interface are the principal reasons for silicon’s dominance
in the IC industry.

SiO2:
• Easily selectively etched using lithography.
• Masks most common impurities
(B, P, As, Sb).
• Excellent insulator
• High breakdown field
• Excellent junction passivation.
• Stable bulk electrical properties.
• Stable and reproducible interface with Si.
 Conceptual Silicon Oxidation System

Quartz
Tube
Wafers

Quartz Carrier

Resistance Heating

O2 H2
 SiO2 Growth Kinetics Models
Deal Grove Model
0.01 - 1 µm ­500 µm
xO

CG • The basic model for oxidation

was developed in 1965 by Deal
CS
and Grove.
CO
Si  O2  SiO2
CI
C I Si  2H 2 O  SiO2  2H 2
Gas Oxide Silicon

F1 F2 F3

F1  hG C G  C S 

N C  C I 
F2  D  D O 
x  x O 

F3  k SC I




 x 2O  x 2i x O  x i
 t
B B/ A
2DC *
whereB  (parabolic rate constant)
N1
B  C* C *k S
and   (linear rate constant)
A  1 1  N1
N 1   
 k S h 

(100) can also be written with oxide thickness as a function of time.


A  t 
x O   1  2  1
2  A / 4B 

where x 2i  Ax i

B


