LHO 12 Interfacing

1
 A simple bus
• Wires:
– Uni-directional or bi-directional
– One line may represent multiple wires
• Bus Processor
rd'/wr
Memory
enable
– Set of wires with a single function addr[0-11]
• Address bus, data bus data[0-7]

– Or, entire collection of wires

bus
• Address, data and control bus structure

• Associated protocol: rules for

communication

2
 Timing Diagrams
• Most common method for describing a rd'/wr
communication protocol enable
• Time proceeds to the right on x-axis
addr
• Control signal: low or high
– May be active low (e.g., go’, /go, or go_L) data
– Use terms assert (active) and deassert
tsetup tread
– Asserting go’ means go=0
read protocol
• Data signal: not valid or valid
• Protocol may have subprotocols rd'/wr
– Called bus cycle, e.g., read and write
enable
– Each may be several clock cycles
addr
• Read example
– rd’/wr set low,address placed on addr for at
data
least tsetup time before enable asserted, enable
triggers memory to place data on data wires tsetup twrite
by time tread write protocol

3
 Microprocessor interfacing: I/O
addressing
• A microprocessor communicates with other devices
using some of its pins
– Port-based I/O (parallel I/O)
• Processor has one or more N-bit ports
• Processor’s software reads and writes a port just like a register
• E.g., P0 = 0xFF; v = P1.2; -- P0 and P1 are 8-bit ports
– Bus-based I/O
• Processor has address, data and control ports that form a single
bus
• Communication protocol is built into the processor
• A single instruction carries out the read or write protocol on the
bus

4
 Types of bus-based I/O:
memory-mapped I/O and
standard I/O
• Processor talks to both memory and peripherals using
same bus – two ways to talk to peripherals
– Memory-mapped I/O
• Peripheral registers occupy addresses in same address space as memory
• e.g., Bus has 16-bit address
– lower 32K addresses may correspond to memory
– upper 32k addresses may correspond to peripherals
– Standard I/O (I/O-mapped I/O)
• Additional pin (M/IO) on bus indicates whether a memory or peripheral
access
• e.g., Bus has 16-bit address
– all 64K addresses correspond to memory when M/IO set to 0
– all 64K addresses correspond to peripherals when M/IO set to 1 5
 Memory-mapped I/O vs.
Standard I/O
• Memory-mapped I/O
– Requires no special instructions
• Assembly instructions involving memory like MOV and ADD
work with peripherals as well
• Standard I/O requires special instructions (e.g., IN, OUT) to move
data between peripheral registers and memory
• Standard I/O
– No loss of memory addresses to peripherals
– Simpler address decoding logic in peripherals possible
• When number of peripherals much smaller than address space
then high-order address bits can be ignored
– smaller and/or faster comparators

6
Consider a simple processor.
I call it the simple processing unit
(SPU).

7
The memory read and I/O read timing
for a simple processor is shown below.

8
The Memory write and I/O write
timing for a simple processor is shown
below.

9
I/O Ports

10
11
 Some Real processors

No separate I/O address

space.

MRD  VMA  R / W
MWR  VMA  R / W
12
 No separate I/O address
space.

MRD  R / W
MWR  R / W
13
MRD  RD  IO / M  RD  IO / M MWR  WR  IO / M  WR  IO / M
IORD  RD  IO / M  RD  IO / M IOWR  WR  IO / M  WR  IO / M
14
MRD  RD  MREQ  RD  MREQ MWR  WR  MREQ  WR  MREQ
IORD  RD  IOREQ IOWR  WR  IOREQ
15
 RD
WR

MRD  RD  M / IO  RD  M / IO MWR  WR  IO / M  WR  M / IO

IORD  RD  M / IO  RD  M / IO IOWR  WR  M / IO  WR  M / IO

16
 The 8051 U1 Atmel AVR
U4
21 39 39 21
P2.0/A8 P0.0/AD0 38 PA0/AD0 PC0/A8 22
22 38
P2.1/A9 P0.1/AD1 37 PA1/AD1 PC1/A9 23
23 37
P2.2/A10 P0.2/AD2 36 PA2/AD2 PC2/A10 24
24 36
P2.3/A11 P0.3/AD3 35 PA3/AD3 PC3/A11 25
25 35
P2.4/A12 P0.4/AD4 34 PA4/AD4 PC4/A12 26
26 34 PA5/AD5 PC5/A13
27 P2.5/A13 P0.5/AD5 33 33 27
P2.6/A14 P0.6/AD6 32 PA6/AD6 PC6/A14 28
28 32 PA7/AD7 PC7/A15
P2.7/A15 P0.7/AD7
10 1 1 10
P3.0/RXD P1.0 2 PB0/T0 PD0/RXD 11
11 2 PB1/T1 PD1/TXD
12 P3.1/TXD P1.1 3 3 12
P3.2/INT0 P1.2 4 PB2/AIN0 PD2/INT0 13
13 4 PB3/AIN1 PD3/INT1
14 P3.3/INT1 P1.3 5 5 14
P3.4/T0 P1.4 6 PB4/SS PD4 15
15 6 PB5/MOSI PD5/OC1A
16 P3.5/T1 P1.5 7 7 16
P3.6/WR P1.6 8 PB6/MISO PD6/WR 17
17 8 PB7/SCK PD7/RD
P3.7/RD P1.7
29 19 19 30
PSEN X1 18 XTAL1 ALE 29
18 XTAL2 OC1B
30 X2
ALE/PROG 31 31
EA/VPP 9 ICP
9 RST
RST
40 40
VCC VCC

AT90S8515 17
8751
18
8051

19
20
21
 A basic memory protocol
D<0...7>
P0 Adr. 7..0 Data P0 D Q
A<0...15
/CS >
P2 Adr. 15…8 /OE
ALE G /WE
Q Adr. 7…0 74373 CS2 /CS1
8 HM6264
ALE P2
/WR /CS
/RD /RD
D<0...7>
/PSEN
A<0...14>
/OE
8051 27C256

• Interfacing an 8051 to external memory

– Ports P0 and P2 support port-based I/O when 8051 internal memory
being used
– Those ports serve as data/address buses when external memory is being
used
– 16-bit address and 8-bit data are time multiplexed; low 8-bits of address
must therefore be latched with aid of ALE signal

22
8051 instructions for addressing external code and data
memory.

23
 D<0...7>
D Q

P0 A<0...15>
/CS
74373
/OE
HM6264

ALE G
/WE

CS2 /CS1

8051 8

P2
/WR /CS

/RD D<0...7>

/ 27C256
A<0...14> Ex: XM(0)  XM(1)
PSE Ex: XM(0)  XM(1) CLR P2
MOV DPTR,#0 /OE
N MOVX A,@DPTR
CLR R0
MOV R1,#1
INC DPTR MOVX A,@R0
MOV R7,A MOV R7,A
MOVX A,@DPTR MOVX A,@R1
XCH A,R7 MOVX @R0,A
MOVX @DPTR,A MOV A,R7
DEC DPTR MOVX @R1,A
XCH A,R7
MOVX @DPTR,A 24
 5 Vd 5 Va

C10
AIN R5 U8
200 .1uF
1 1 28
ANAIN Vdig
27 U9
Vana
2

BNC R4 R6 22 D0 39 21
50 33.2K 2 D0 21 D1 38 P0.0/AD0 P2.0/A8 22
AGND1 D1 20 D2 37 P0.1/AD1 P2.1/A9 23
2.2uF D2 19 D3 36 P0.2/AD2 P2.2/A10 24
C8 3 D3 18 D4 35 P0.3/AD3 P2.3/A11 25
REF D4 17 D5 34 P0.4/AD4 P2.4/A12 26
D5 16 D6 33 P0.5/AD5 P2.5/A13 27
4 D6 15 D7 32 P0.6/AD6 P2.6/A14 28
CAP D7 13 P0.7/AD7 P2.7/A15
2.2uF D8 12 1 10
C9 5 D9 11 2 P1.0 P3.0/RXD 11
AGND2 D10 10 3 P1.1 P3.1/TXD 12
D11 9 4 P1.2 P3.2/INT0 13
23 D12 8 5 P1.3 P3.3/INT1 14
BYTE D13 7 6 P1.4 P3.4/T0 15
D14 6 7 P1.5 P3.5/T1 16
D15 8 P1.6 P3.6/WR 17
25 26 #busy PORTF0 P1.7 P3.7/RD
CS BUSY 19 29
14 24 R/#C PORTF1 18 X1 PSEN
DGND R/C X2 30
31 ALE/PROG
AD976/S0 9 EA/VPP
GND DIG RST
40
VCC

8751

RnC EQU P1.1

n_BUSY EQU P1.2
BYTE EQU P1.3

25
RnC EQU P1.1
n_BUSY EQU P1.2
BYTE EQU P1.3
CLR RnC
SETB RnC
JNB n_BUSY,$
MOV R7,P0
CPL BYTE
MOV R6,P0 26
The 8255

27
28
29
30
31
Change individual bits on Port C

32
 U4 U1
21 39 D0 D0 34 4
22 P2.0/A8 P0.0/AD0 38 D1 D1 33 D0 PA0 3
23 P2.1/A9 P0.1/AD1 37 D2 D2 32 D1 PA1 2
24 P2.2/A10 P0.2/AD2 36 D3 D3 31 D2 PA2 1
25 P2.3/A11 P0.3/AD3 35 D4 D4 30 D3 PA3 40
26 P2.4/A12 P0.4/AD4 34 D5 D5 29 D4 PA4 39
27 P2.5/A13 P0.5/AD5 33 D6 D6 28 D5 PA5 38
28 P2.6/A14 P0.6/AD6 32 D7 D7 27 D6 PA6 37
P2.7/A15 P0.7/AD7 D7 PA7
10 1 5 18
11 P3.0/RXD P1.0 2 U3 36 RD PB0 19
12 P3.1/TXD P1.1 3 9 WR PB1 20
13 P3.2/INT0 P1.2 4 D0 3 2 8 A0 PB2 21
14 P3.3/INT1 P1.3 5 D1 4 D0 Q0 5 35 A1 PB3 22
15 P3.4/T0 P1.4 6 D2 7 D1 Q1 6 6 RESET PB4 23
/WR 16 P3.5/T1 P1.5 7 D3 8 D2 Q2 9 CS PB5 24
/RD 17 P3.6/WR P1.6 8 D4 13 D3 Q3 12 PB6 25
P3.7/RD P1.7 D5 14 D4 Q4 15 PB7
29 19 D6 17 D5 Q5 16 14
PSEN X1 18 D7 18 D6 Q6 19 PC0 15
30 X2 D7 Q7 PC1 16
ALE/PROG 31 ALE 11 PC2 17
EA/VPP 9 1 LE PC3 13
RST OE PC4 12
40 PC5 11
VCC 74LS373 PC6 10
PC7
8751 82C55A

U2
D0 34 4
D1 33 D0 PA0 3
D2 32 D1 PA1 2
D3 31 D2 PA2 1
D4 30 D3 PA3 40
D5 29 D4 PA4 39
D6 28 D5 PA5 38
D7 27 D6 PA6 37
D7 PA7
5 18
36 RD PB0 19
9 WR PB1 20
8 A0 PB2 21
35 A1 PB3 22
6 RESET PB4 23
CS PB5 24
PB6 25
PB7
14
PC0 15
PC1 16
PC2 17
PC3 13
PC4 12
PC5 11
PC6
33
PC7
10

82C55A
RESET_8255 EQU P1.0
CTL1 EQU 111111111011B ;ONE POSSIBLE ADDRESS FOR CONTROL PORT OF 8255 #1
PRTA1 EQU 111111111000B ;ONE POSSIBLE ADDRESS FOR PORT A OF 8255 #1
PRTB1 EQU 111111111001B ;ONE POSSIBLE ADDRESS FOR PORT A OF 8255 #1
PRTC1 EQU 111111111010B ;ONE POSSIBLE ADDRESS FOR PORT A OF 8255 #1
CTL2 EQU 111111110111B ;ONE POSSIBLE ADDRESS FOR CONTROL PORT OF 8255 #2
PRTA2 EQU 111111110100B ;ONE POSSIBLE ADDRESS FOR PORT A OF 8255 #2
PRTB2 EQU 111111110101B ;ONE POSSIBLE ADDRESS FOR PORT A OF 8255 #2
PRTC2 EQU 111111110110B ;ONE POSSIBLE ADDRESS FOR PORT A OF 8255 #2

CLR RESET_8255 ;REMOVE RESET FROM 8255

;DO ADDITION C2|C1 <-- A2|A1 + B2|B1
MOV DPTR,#(CTL1 AND CTL2);POINT DPTR TO CONTROL REG OF 8255 #1 AND #2
MOV A,10010010B ;PRTA, PRTB IN, PRTC OUT
MOVX @DPTR,A ;OUTPUT TO BOTH CONTROL REGS AT SAME TIME
MOV DPTR,#PRTA1 ;SELECT PORT A OF 8255 #1
MOVX A,@DPTR ;GET PRTA1
MOV R7,A ;SAVE IT
MOV DPTR,#PRTB1 ;SELECT PORT B OF 8255 #1
MOVX A,@DPTR ;READ PORT B OF 8255 #1
ADD A,R7 ;ADD PRTA1 TO PRTB1
MOV DPTR,#PRTC1 ;SELECT PORT C OF 8255 #1
MOVX @DPTR,A ;OUTPUT TO PRTC1
END

34
 U4 U1
A8 21 39 D0 D0 34 4
A9 22 P2.0/A8 P0.0/AD0 38 D1 D1 33 D0 PA0 3
A10 23 P2.1/A9 P0.1/AD1 37 D2 D2 32 D1 PA1 2
A11 24 P2.2/A10 P0.2/AD2 36 D3 D3 31 D2 PA2 1
A12 25 P2.3/A11 P0.3/AD3 35 D4 D4 30 D3 PA3 40
A13 26 P2.4/A12 P0.4/AD4 34 D5 D5 29 D4 PA4 39
A14 27 P2.5/A13 P0.5/AD5 33 D6 D6 28 D5 PA5 38
A15 28 P2.6/A14 P0.6/AD6 32 D7 D7 27 D6 PA6 37
P2.7/A15 P0.7/AD7 D7 PA7
10 1 5 18
11 P3.0/RXD P1.0 2 36 RD PB0 19
12 P3.1/TXD P1.1 3 9 WR PB1 20
13 P3.2/INT0 P1.2 4 A8 8 A0 PB2 21
14 P3.3/INT1 P1.3 5 A9 35 A1 PB3 22
15 P3.4/T0 P1.4 6 A10 6 RESET PB4 23
/WR 16 P3.5/T1 P1.5 7 A11 CS PB5 24
/RD 17 P3.6/WR P1.6 8 A12 PB6 25
P3.7/RD P1.7 A13 PB7
29 19 A14 14
PSEN X1 18 A15 PC0 15
30 X2 PC1 16
ALE/PROG 31 PC2 17
EA/VPP 9 PC3 13
RST PC4 12
40 PC5 11
VCC PC6 10
PC7
8751 82C55A

U2
D0 34 4
D1 33 D0 PA0 3
D2 32 D1 PA1 2
D3 31 D2 PA2 1
D4 30 D3 PA3 40
D5 29 D4 PA4 39
D6 28 D5 PA5 38
D7 27 D6 PA6 37
D7 PA7
5 18
36 RD PB0 19
9 WR PB1 20
8 A0 PB2 21
35 A1 PB3 22
6 RESET PB4 23
CS PB5 24
PB6 25
PB7
14
PC0 15
PC1 16
PC2 17
PC3 13
PC4 12
PC5 11
PC6 10
35
PC7
82C55A
 U1

39 21
38 PA0/AD0 PC0/A8 22
37 PA1/AD1 PC1/A9 23
36 PA2/AD2 PC2/A10 24
35 PA3/AD3 PC3/A11 25
34 PA4/AD4 PC4/A12 26
33 PA5/AD5 PC5/A13 27
32 PA6/AD6 PC6/A14 28
PA7/AD7 PC7/A15
1 10
2 PB0/T0 PD0/RXD 11
3 PB1/T1 PD1/TXD 12
4 PB2/AIN0 PD2/INT0 13
5 PB3/AIN1 PD3/INT1 14
6 PB4/SS PD4 15
7 PB5/MOSI PD5/OC1A 16
8 PB6/MISO PD6/WR 17
PB7/SCK PD7/RD
19 30
18 XTAL1 ALE 29
XTAL2 OC1B
31
9 ICP
RST
40
VCC

AT90S8515 36
37
 U2
D0 18 19 A0
D1 17 8D 8Q 16 A1
D2 14 7D 7Q 15 A2
D3 13 6D 6Q 12 A3
D4 8 5D 5Q 9 A4 U4
D5 7 4D 4Q 6 A5
D6 4 3D 3Q 5 A6 A0 12 13 D0
D7 3 2D 2Q 2 A7 A1 11 A0 I/O0 14 D1
11 1D 1Q A2 10 A1 I/O1 15 D2
1 C A3 9 A2 I/O2 17 D3
OC A4 8 A3 I/O3 18 D4
A5 7 A4 I/O4 19 D5
U1 74LS373 A6 6 A5 I/O5 20 D6
A7 5 A6 I/O6 21 D7
D0 39 21 A8 A8 27 A7 I/O7
D1 38 PA0/AD0 PC0/A8 22 A9 A9 26 A8
D2 37 PA1/AD1 PC1/A9 23 A10 A10 23 A9
D3 36 PA2/AD2 PC2/A10 24 A11 A11 25 A10
D4 35 PA3/AD3 PC3/A11 25 A12 A12 4 A11
D5 34 PA4/AD4 PC4/A12 26 A13 A13 28 A12
D6 33 PA5/AD5 PC5/A13 27 A14 A14 29 A13
D7 32 PA6/AD6 PC6/A14 28 A15 A15 3 A14
PA7/AD7 PC7/A15 2 A15
1 10 A16
2 PB0/T0 PD0/RXD 11 n_RD 24
3 PB1/T1 PD1/TXD 12 n_WR 31 OE
4 PB2/AIN0 PD2/INT0 13 22 WE
5 PB3/AIN1 PD3/INT1 14 CE
6 PB4/SS PD4 15 32
7 PB5/MOSI PD5/OC1A 16 n_WR VCC
8 PB6/MISO PD6/WR 17 n_RD VCC
Y1 PB7/SCK PD7/RD AT49BV001N
8 MHz 19 30
18 XTAL1 ALE 29
XTAL2 OC1B
C1 C2 31
22 pf 22 pf 9 ICP
RST
40
VCC
VCC
AT90S8515

Figure 1. AT90S8515 with expanded memory. What should we do with A16? Answer: connect it to an unused port pin.
Question: How could we map the entire 128K bytes of memory to the top 32 Kbytes of the AVR address space.
Answer: Connect AVR A15 to /CE on U4. Now the memory is selected only when the AVR addresses the top have of the memory address space
where A15 = 1. Connect A15 and A16 of U4 to unused AVR port pins. By changing these port pin, any of the four 32 K byte pages of U4 memory
can be switched in and out of the AVR address space.
38
39
40
41
42