Lecture 7: Registers, Shift Registers

and Counters
Ebrahim Karami
ENGI-9819
Computer Hardware Foundations
Winter 2023
Building Complex Memory Elements

• Flipflops: most primitive "packaged" sequential circuits

• More complex sequential building blocks:

Registers, Shift registers, Counters

Available as components in the TTL Catalog

• How to represent and design simple sequential circuits: counters

• Problems and pitfalls when working with counters:

Start-up States
Asynchronous vs. Synchronous logic
Registers
Storage unit. Can hold an n-bit value
Composed of a group of n flip-flops
Each flip-flop stores 1 bit of information
Normally use D flip-flops
D Q
Dff
clk

D Q
Dff
clk

D Q
Dff
clk

D Q
Dff
clk
Controlled Register D Q
Dff
clk

D Q
Dff
clk

D Q
Dff
clk

D Q
Dff
clk
Registers
Group of storage elements read/written as a unit
 Shift Registers
Storage + ability to circulate data among storage elements

Q1 Q2 Q3 Q4

1 0 0 0
Shift
0 1 0 0
Shift
0 0 1 0
Shift
0 0 0 1

Shift
Shift from left storage Q1
element to right neighbor
on every lo-to-hi transition Q2
on shift signal
Q3
Wrap around from rightmost Q4
element to leftmost element
Master Slave FFs: sample inputs while
clock is high; change outputs on
falling edge
 Shift Registers I/O
Serial vs. Parallel Inputs
Serial vs. Parallel Outputs
Shift Direction: Left vs. Right

Serial Inputs: LSI, RSI

Parallel Inputs: D, C, B, A
Parallel Outputs: QD, QC, QB, QA
QD Clear Signal
QC Positive Edge Triggered Devices
QB
QA S1,S0 determine the shift function
S1 = 1, S0 = 1: Load on rising clk edge
synchronous load
S1 = 1, S0 = 0: shift left on rising clk edge
LSI replaces element D
74194 4-bit Universal S1 = 0, S0 = 1: shift right on rising clk edge
Shift Register RSI replaces element A
S1 = 0, S0 = 0: hold state

Multiplexing logic on input to each FF!

Shifters well suited for serial-to-parallel conversions,

such as terminal to computer communications
 Application of Shift Registers
Parallel to Serial Conversion
Sender Receiver
S1 S1
S0 194 S0 194
LSI LSI
D7 D QD D QD D7
D6 C QC C QC D6
D5 B QB B QB D5
D4 A QA A QA D4
RSI RSI
Clock CLK
CLK
Parallel CLR CLR Parallel
Inputs Outputs
S1 S1
S0 194 S0 194
LSI LSI
D3 D QD D QD D3
D2 C QC C QC D2
D1 B QB B QB D1
D0 A QA A QA D0
RSI RSI
CLK CLK
CLR CLR

Serial
transmission
Counters
Proceed through a well-defined sequence of states in response to
count signal

3 Bit Up-counter: 000, 001, 010, 011, 100, 101, 110, 111, 000, ...

3 Bit Down-counter: 111, 110, 101, 100, 011, 010, 001, 000, 111, ...

Binary vs. BCD vs. Gray Code Counters

A counter is a "degenerate" finite state machine/sequential circuit

where the state is the only output
Counter Design Procedure
This procedure can be generalized to implement ANY finite state
machine

Counters are a very simple way to start:

no decisions on what state to advance to next
current state is the output

Example: 3-bit Binary Upcounter

Present Next Flipflop
State State Inputs
C B A C+ B+ A+ TC TB TA Decide to implement with
Toggle Flipflops
0 0 0 0 0 1 0 0 1
What inputs must be
0 0 1 0 1 0 0 1 1
presented to the T FFs
0 1 0 0 1 1 0 0 1 to get them to change
0 1 1 1 0 0 1 1 1 to the desired state bit?
1 0 0 1 0 1 0 0 1
1 0 1 1 1 0 0 1 1 This is called
1 1 0 1 1 1 0 0 1 "Remapping the Next
1 1 1 0 0 0 1 1 1 State Function"
 Resultant Circuit for Counter
K-maps for Toggle Resulting Logic Circuit:
Inputs: +
C
CB
A 00 01 11 10

0 1 1 1 1

1 1 1 1 1 QA QB QC
TSQ T SQ T SQ
CLK CLK CLK
B Q Q Q
TA = 1 R R R
\Reset
C
CB
Count
A 00 01 11 10

0 0 0 0 0
Timing Diagram:
1 1 1 1 1
100
B
TB = A \Reset

CB
C QC
A 00 01 11 10
QB
0 0 0 0 0
QA
1 0 1 1 0
Count
B
TC = A • B
Ripple Counter

In a ripple counter, the

flip-flop output
transitions serve as the
sources for triggering
the changes in other
flip-flops.
More Complex Counter Design
Step 1: Derive the State Transition Diagram
Count sequence: 000, 010, 011, 101, 110

Present Next
State State

Step 2: State Transition Table

000 0 1 0
010 0 1 1
011 1 0 1
101 1 1 0
110 0 0 0
Complex Counter Design (Contd)
Step 1: Derive the State Transition Diagram
Count sequence: 000, 010, 011, 101, 110

Present Next
State State

Step 2: State Transition Table

000 0 1 0
001 XXX
010 0 1 1
011 1 0 1
100 XXX
101 1 1 0
110 0 0 0 Note the Don't Care conditions
111 XXX
Counter Design (Contd)

Step 3: K-Maps for Next State Functions

CB CB
A 00 01 11 10 A 00 01 11 10
0 0
1 1

C+ = B+ =

CB
A 00 01 11 10
0

A+ =
Counter Design

Step 4: Choose Flipflop Type for Implementation

Use Excitation Table to Remap Next State Functions

Present Toggle
State Inputs
CBA TC TB TA
Q Q+ T
000 0 1 0
0 0 0 001 XXX
0 1 1 010 0 0 1
1 0 1 011 1 1 0
1 1 0 100 XXX
101 0 1 1
110 1 1 0
Toggle Excitation 111 XXX
Table
Remapped Next State
Functions
Resultant Counter Design
Remapped K-Maps
CB CB
A 00 01 11 10 A 00 01 11 10
0 0
1 1

TC TB

CB
A 00 01 11 10
0

TA
TC = A’ C + A C’ = A xor C

TB = A + B’ + C

TA = A’ B C + B’ C
Resultant Circuit for Complex Counter
Resulting Logic:
5 Gates
13 Input Literals + TC S Q C TB B TA A
T T S Q T S Q
Flipflop connections CLK Q CLK Q CLK Q
R \C R \B R \A
Count

\Reset

A
C TC \A
B
C TA
A
Timing Waveform: TB \B
\B
C
C
100

Count
\Reset
0 0 0 0 1 1 0
C
B 0 0 1 1 0 1 0

A 0 0 0 1 1 0 0
Implementing Counters with Different FFs
 Different counters can be implemented best with different
FFs
 Steps in building a counter
 Build state diagram
 Build state transition table
 Build next state K-map
 Implementing the next state function with different FFs
 Toggle flip flops best for binary counters
 Existing CAD software for finite state machines favor D
FFs
 Implementing 5-state counter with RS FFs

Continuing with the 000, 010, 011, 101, 110,

000, ... counter example

Present Next Rmepped next state

Q Q+ R S State State
000 0 1 0 RC
X SC
0 RB
0 1SB RA 0SA
X
0 0 X 0 001 XXX X X X X X X
0 1 0 1 010 0 1 1 X 0 0 X 0 1
1 0 1 0 011 1 0 1 0 1 1 0 0 X
1 1 0 X 100 XXX X X X X X X
Q+ = S + R Q 101 1 1 0 0 X 0 1 1 0
110 0 0 0 1 0 1 0 X 0
RS Exitation Table
111 XXX X X X X X X

Remapped Next State Functions

Implementation with RS FFs
RS FFs Continued

CB CB
A 00 01 11 10 A 00 01 11 10
0 X X 1 X 0 0 0 0 X

1 1 X 1 X X
X 0 X 0
RC = A
RC SC
CB CB SC = A
A 00 01 11 10 A 00 01 11 10
0 0 0 1 X 0 1 X 0 X
RB = A B + B C

1 1 SB = B
X 1 X 0 X 0 X 1
RB SB RA = C

CB CB SA = B C
A 00 01 11 10 A 00 01 11 10
0 X 0 X X 0 0 1 0 X
1
X 0 X 1 1
X X X 0

RA SA
Implementation With RS FFs

C B A
\A R Q RB R Q C R Q
CLK CLK CLK
A S Q \B S Q SA S Q
\C \B \A
Count

A
RB B SA
C
B \C

Resulting Logic Level Implementation:

3 Gates, 11 Input Literals + Flipflop connections
 Implementing with JK FFs

Continuing with the 000, 010, 011, 101, 110,

000, ... counter example

Present Next Rmepped next state

Q Q+ J K State State JC KC JB KB JA KA

0 0 0 X 000 0 1 0 0 X 1 X 0 X
0 1 1 X 001 XXX X X X X X X
1 0 X 1 010 0 1 1 0 X X 0 1 X
1 1 X 0 011 1 0 1 1 X X 1 X 0
Q+ = S + R Q 100 XXX X X X X X X
RS Exitation Table 101 1 1 0 X 0 1 X X 1
110 0 0 0 X 1 X 1 0 X
111 XXX X X X X X X

Remapped Next State Functions

 Implementation with JK FFs
CB CB
A 00 01 11 10 A 00 01 11 10
0 0

1 1
JC = A
JC KC
CB CB KC = A/
A 00 01 11 10 A 00 01 11 10
0 0 JB = 1

1 1 KB = A + C

JB KB JA = B C/

CB CB KA = C
A 00 01 11 10 A 00 01 11 10
0 0

1 1

JA KA
Implementation with JK FFs
+

A J Q C J Q B JA J Q A
CLK CLK CLK
\A K Q KB K Q C K Q
\C \B \A
Count

A B
KB JA
C \C

Resulting Logic Level Implementation:

2 Gates, 10 Input Literals + Flipflop Connections
Implementation with D FFs
Simplest Design Procedure: No remapping needed!

DC = A

DB = A C + B

DA = B C

C B A
A D Q DB D Q DA D Q

CLK Q CLK Q CLK Q

\C \B \A
Count

\C
B
\A DB DA
\C
\B

Resulting Logic Level Implementation:

3 Gates, 8 Input Literals + Flipflop connections
Comparison with Different FF Types
• T FFs well suited for straightforward binary counters

But yielded worst gate and literal count for this example!

• No reason to choose R-S over J-K FFs: it is a proper subset of J-K

R-S FFs don't really exist anyway

J-K FFs yielded lowest gate count

Tend to yield best choice for packaged logic where gate count is key

• D FFs yield simplest design procedure

Best literal count

D storage devices very transistor efficient in VLSI

Best choice where area/literal count is the key