Computer Architecture and

Assembly language
CHAPTER 1 : INTRODUCTION
 Architecture & Organization

• Two jargons that are often confusing

• Computer organization: refers to the
operational units and their interconnections that
realize the architectural specifications (!)
• Control signals, Interface, Memory technology.
• Computer Architecture refers to those
attributes of a system visible to a programmer, or
put another way, those attributes that have a
direct impact on the logical execution of a program
(!)
• Instruction set, no. of bits used for data
representation, I/O mechanisms
 1. 1. Introduction - continued
• Architecture concerns more about the basic instruction
design, that may lead to better performance of the system
• Organization, is the implementation of computer system,
in terms of its interconnection of functional units : CPU,
memory, bus and I/O devices.
• Example : IBM/S-370 family architecture. There are plenty
of IBM products having the same architecture (S-370) but
different organization, depending on its price/performance
measures. Cost and performance differs the organizations
• So, organization of a computer is the implementation of its
architecture, but tailored to fit the intended price and
performance measures.
 Structure & Function

• Structure is the way in which component

relate to each other

• Function is the operation of individual

components as part of the structure
 1. 2. Introduction - Structure and Function
• Computer system may be seen from different angles. One
may see it from the structures, or the others may look it
from its functions.
• From the structure point of view, we may see a system as
an interrelated components, while from its function we
may learn the operational details of each components.
• It is up to us to see, we may start from the bottom up
(learn the operational details of each component) and
then we study how are they interrelated; or the other way
around or top down approach.
• The book we are using, use the top-down approach.
 1. 2. Introduction - Structure and Function
• Function of a computer :
Data processing
Data storage
Data Movement
Control
• Primary Function is data processing
• Second most important function is data storage
• Another important function is “control”
• And sometimes it can function to move data (transfer)
Functional View
 1.2. Introduction - Structure of Computer

• Four main structure are :

Central Processing Unit (CPU)
Main Memory : Stores data temporarily
I/O (Input Output) : Moves Data between computer and external
environment
System Interconnection : Provides communication among CPU,
Memory and I/O
• CPU consists of :
Control Unit, ALU (x,:,+,-), Registers (internal
Storage), CPU bus/interconnections
 1.3. Introduction - outline of the book

• Computer Evolution and Performance

• Computer Interconnection Structures
• Cache Memory
• Internal Memory
• External Memory
• Input/Output
• Instruction Sets
• CPU structure & Functions
• Pipelined, RISC
• Superscalar, Parallel Processor
• etc.
Computer Evolution and
Performance
 Brief History

• From ENIAC (Electronic Numerical Integrator and

Computer) John Mauchly and John P Eckert, University of
Pennsylvania (1943 - 1946)
• For war purposes
• Weighted 30 tons, consumes 140 kwatts of electric power,
15.000 square feet of space, only 5000 addition per second
• Not a digital computer, it was a decimal computer (analog)
• John von Neuman proposed : EDVAC (Electronic Discrete
Variable Computer) - first stored program computer -1945
ENIAC
ENIAC
 2. 1.Evolution and Performance - history
• 1946 Von Neuman and his gang proposed IAS (Institute
for Advanced Studies)
• The design included :
– main memory
– ALU
– Control Unit
– I/O
• First Stored Program, able to perform :
+, -, x, :
• The “father” of all modern computer/processor
Structure of IAS
IAS
 2. 1. Evolution and Performance -history
IAS components are :
• MBR (memory buffer register), MAR (memory address
register), IR (instruction register), IBR (instruction buffer
register), PC (program counter), AC (accumulator and MQ
(multiplier quotient), memory (1000 locations)
• 20 bit instruction : 8 bit opcode, 12 bit address
(addressing one of 1000 memory locations - 0 to 999)
• 39 bit data (with sign bit - 1 bit)
• Operations : data transfer between registers and ALU,
unconditional branch, conditional branch, arithmetic,
address modify
 History of Commercial computers

• First Generation : 1950 Mauchly & Eckert developed UNIVAC

I, used by Census Beureau
• Then appeared UNIVAC II, and later grew to UNIVAC 1100
series (1103, 1104,1105,1106,1108) - vacuum tubes and
later transistor
• Second Generation : Transistors, IBM 7094 (although there
are NCR, RCA and others tried to develop their versions -
commercially not successful)
• Third Generation : Integrated Circuit (IC) - SSI. IBM S/360 was
the successful example
• Later generations (possibly fourth and fifth) : LSI and VLSI
technology
 history of commercial computers
Approx Speed
Generation Time Technology (opr/sec)
----------------------------------------------------------------------------------------------
1. 1946-57 Vacuum tube 40,000
2. 1958-64 Transistor 200,000
3. 1965-71 SSI & MSI
1,000,000
4. 1972-77 LSI
10,000,000
5. 1978-VLSI
100,000,000
----------------------------------------------------------------------------------------------
 Evolution - System 360 Family

Model Model Model Model Model

Characteristic 30 40 50 65 75
------------------------------------------------------------------------------------------
Max memory size (Bytes) 64K 256K 256K 512K 512K
Memory data-rate(MB/s) 0.5 0.8 2.0 8.0 16.0
Processor cycle time (s) 1.0 0.625 0.5 0.25 0.2
Relative Speed 1 3.5 10 21 50
Max Number data channel 3 3 4 6 6
Max chan. data-rate(KB/s) 250 400 800 1250 1250
---------------------------------------------------------------------------------------
• Family architecture menyebabkan adanya istilah : upward dan
downward compatible
 Evolution - Later generations

• Semiconductor memories :
1K,4K,16K,64K,256K,1M,4M,16 Mbits on a single chip
• Microprocessors appeared :
Intel 4004 (1971), Intel 8008 (72), Intel 8080 (8 bit-74),
8086 (16bit-81), 80386 (32bit-85) onward.
• At almost the same time : Motorola, 6800(8bit), 68000
(16bit), 68010(16bit), 68020 (32bit), 68030/40 (32bit)
• Then Motorola’s product disappeared commercially
• Intel products dominated the market, since the
appearance of IBM PC
 Evolution of Microprocessors
------------------------------------------------------------------------------------------
Feature 8008 8080 8086 80386 80486
------------------------------------------------------------------------------------------
Year introduced 1972 1974 1978 1985 1989
# of instructions 66 111 133 154 235
Address bus width 8 16 20 32 32
Data bus width 8 8 16 32 32
# of registers 8 8 16 8 8
Memory addressability 16KB 64KB 1 MB 4 GB 4 GB
Bus Bandwidth (MB/s) - 0.75 5 32 32
Reg-Reg add time (s) - 1.3 0.3 0.125 0.06
------------------------------------------------------------------------------------------
 8086 (1978)
• 20-bit address bus : 1M byte(1024Kbytes) memory
• instruction : over 20,000 variation
– 4004 : 45, 8085 : 246
• A separate BIU and EU
– Fetch and Execute instruction simultaneously
• 16-bit Internal processor registers
– with the ability to access the high and low 8 bits separately
if desired
• hardware multiply and divide built in
• support for an external math coprocessor
– perform floating-point math operations as much as 100
times faster than the processor alone via software emulation
26
 8088
• 8086(1978) : 16-bit data bus
– requirement of two separate 8-bit memory banks to
supply its 16-bit data bus
– quite expensive memory chip at the time
• 8088(1979) : external 8-bit data bus
• IBM announced the PC : 1981.8
– 8088, 16K memory(expandable 64K),
4.77MHz(clock speed)
– PC standard
 80186/80188
• High-Integration CPUs
– schematic diagram for IBM’s original PC
• 8088 microprocessor
• several additional chips are required
– 80186 = 8086 + several additional chips
• added 9 new instructions
• clock generator
• programmable timer
• programmable interrupt controller
• circuitry to select the I/O devices
30
 80286 (1982)
• some instruction executed : 250ns(4.0MIPS) at 8MHz
• 24-bit address bus : 16M byte memory
• added 16 new instructions
• Real Mode: 1st powered on
– functions exactly like an 8086
– uses only its 20 least significant address lines(1M)
• Protected :
• A “Fatal Flaw” ?
– once switched to Protected mode, should not be able to
switch back to Real mode
– 286 chips are operated in Real mode and thus function only
as fast 8086s
• IBM AT(advanced technology) Computer :1984
 80386
• flexible 32-bit Microprocessor(1986) : data bus, registers
• very large address space : 32-bit address bus(4G byte physical)
– 64 terabyte virtual
– 4G maximum segment size
• integrated memory management unit
– virtual memory support, optional on-chip paging
– 4 levels of protection
• added 16 new instructions
• Real Mode, Protected mode
• Virtual 8086 mode : in a protected and paged system
• 386SX : 16-bit external data bus, 24-bit address bus
• 386EX : 16-bit external data bus, 26-bit address bus
– 1995, called embedded PC
 80486
• Intel released 80486 in 1989
• maintaining compatibility : standard(8086,286,386)
– polished & refined 386 : twice as fast as 386
• redesigned using RISC concept :
– frequently used instruction : a single clock cycle
– new 5-stage execution pipeline
• highly integrated
– 8K memory cache
– floating-point processor(equivalent of the external 387)
• added 6 new instructions : for used by OS
 80486
• 486SX :
– for low-end applications that do not require a coprocessor or
internal cache
– clock speed limited 33MHz
• 486DX2 & DX4 :
– internal clock rate is twice or 3 times external clock rate
– 486DX4 100 : internal 100MHz, external 33MHz
• Overdrive Processor:
– 486DX2 or DX4 chips with overdrive socket pin-outs
– to upgrade low-speed 486DX, SX with 486DX2, DX4
 Pentium
• increasing the complexity of the IC: to scale the chip
down
– if every line could be shrunk in half, same circuit could be
built in one-forth the area
• Superscaler : support 2 instruction pipelines(5 stage)
– ALU, address generation circuit, data cache interface
– actually execute two different instruction simultaneously
• Pentium(1993) : originally labeled P5(80586)
– 60, 66MHz(110MIPS)
– 8K code cache, 8K data cache
– coprocessor : redesign(8-stage instruction pipeline)
– external data bus : 64 bit(higher data transfer rates)
– added 6 new instructions : for used by OS
 Pentium pro
• codenamed P6 : 1995
– basic clock frequency : 150, 166MHz
• two chips in one : two separate silicon die
– processor(large chip), 256K level two cache
• Superscaler processor of degree three(12 stage)
• internal cache :
– level one(L1) : 8K instruction and data cache
– level two(L2) : 256K(or 512K)
• 36-bit address bus : 64G byte memory
• has been optimized to efficiently execute 32-bit code
– bundled with Windows NT : server market
PentiumⅡand PentiumⅡXeon Microprocessor

• PentiumⅡmicroprocessor released in 1997

• PentiumⅡ module : small circuit board
– Pentium pro with MMX : no internal L2 cache
– 512K L2 cache(operated at speed of 133MHz)
• main reason :
– L2 cache found main board of Pentium : 60, 66MHz
– not fast enough to justify a new microprocessor
– Pentium pro : not well yield
• 266~333MHz with 100MHz bus speed : in 1998
– bottleneck : external bus speed 66MHz
– use of 8ns SDRAM :
PentiumⅡand PentiumⅡXeon Microprocessor

• new version of PentiumⅡcalled Xeon : mid-1998

– for high-end workstation and server applications
• main difference from PentiumⅡ :
– L1 cache size : 32K bytes
– L2 cache size : 512K, 1M, 2M
• change in Intel’s strategy :
– professional version and home/business version of
PentiumⅡ microprocessor
 Pentium Ⅲ Microprocessor
• 1. used faster core than PentiumⅡ
– is still P6 or Pentium pro processor
• 2. Two version :
– bus speed : 100MHz
– 1. slot 1 version mounted on a plastic cartridge
– 512K cache : one-half the clock speed
– 2. socket 370 version called flip-chip : looks like the
older Pentium package → Intel claim cost less
– 256K cache : clock speed
• 3. clock frequency : 1 GHz
 Pentium 4 Microprocessor

• release in late 2000 : used Intel P6 architecture

• main difference :
• 1. clock speed : 1.3, 1.4, 1.5 GHz
• 2. support to use RAMBUS memory technology
– DDR(double-data-rate) SDRAM : both edge
• 3. interconnection : from aluminum to copper
– copper : is better conductor → increase clock frequency
– bus speed : from current max. of 133MHz to 200MHz or
higher
 The Future of Microprocessors
• no one can really make accurate prediction :
– success of Intel family should continue for quite a few years
• what may occur is : will occur
– a change to RISC technology,
– but more likely a change to a new technology being
developed jointly by Intel and Hewlett-Packard
• new technology :
– even will embody CISC instruction set of 80X86 family ,
– so that software for system will survive
• basic premise behind this technology : many 
– will communicate directly with each other, allowing parallel
processing without any change to instruction set or program