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Lecture17 Flip Flops

Sequential logic circuits have memory and their output depends on both the input and present state. A basic sequential circuit is a flip-flop, which has two stable states. An SR flip-flop is based on two NOR gates and can reduce switching noise. Edge-triggered flip-flops change state only when the clock changes, either on the rising or falling edge. Master-slave flip-flops prevent race conditions by isolating the output from feedback during state changes.

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39 views23 pages

Lecture17 Flip Flops

Sequential logic circuits have memory and their output depends on both the input and present state. A basic sequential circuit is a flip-flop, which has two stable states. An SR flip-flop is based on two NOR gates and can reduce switching noise. Edge-triggered flip-flops change state only when the clock changes, either on the rising or falling edge. Master-slave flip-flops prevent race conditions by isolating the output from feedback during state changes.

Uploaded by

zoro goh
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PPT, PDF, TXT or read online on Scribd
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Flip Flops

Clock Signal

Sequential logic circuits have memory


Output is a function of input and present state
Sequential circuits are synchronized by a periodic “clock” signal
Clock Signal generator

Clock signals can be generated using odd number of inverters

v0 v1 v2 v3 v4 v5

v0 v1 v5

T = 2  tp N
Flip Flop

A basic sequential circuit is a flip-flop


Flip-flop has two stable states of complementary output values
SR Flip Flop

SR (set-reset) flip-flop based on two nor gates


SR Flip Flop
Noise Reduction in SR Flip Flop
SR flip flop can reduce a switching noise
When switch is pulled down some oscillations may occur at B
They will be eliminated by the flip-flop
Exercise
For a given S and R inputs to SR flip-flop,
sketch the output signal Q

t
Exercise
SR Flip Flop

SR (set-reset) flip-flop based on two nand gates


Clocked SR Flip Flop Circuit

Clock controlled flip-flop changes its state


only when the clock C is high
Clocked SR Flip Flop Circuit with Reset
Some flip-flops have asynchronous
preset Pr and clear Cl signals.
Output changes once these signals change, however
the input signals must wait for a change in clock
to change the output
Edge Triggered Flip Flop

Edge triggered flip-flop changes only


when the clock C changes
Positive Edge Triggered Flip Flop

Positive-edge triggered flip-flop changes only


on the rising edge of the clock C
Exercise
The input D to a positive-edge triggered flip-flop is shown
Find the output signal Q

t
Exercise
Negative Edge Triggered JK Flip Flop
Other Flip Flops

T J D J
Q Q
   
Q Q
K K

T Q D Q

 Q  Q

Toggle Flip-Flop Delay Flip-Flop (D-latch)


Race Problem

tloop
t


D Q t

1  Q

Signal can race around during  = 1


Master-Slave Flip Flop Implementation
MASTER SLAVE

SI
J S Q S Q Q

RI
K R Q R Q Q

Master transmits the signal


PRESET
to the output during the
high clock phase and
J Q slave is waiting for the
 clock to change this
Q
K prevents race conditions
CLEAR
Shift Registers
Shift Registers
Counter

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