Week-2

80x86 Processor Architecture:

Introduction, Processor Model,
Programmer’s model, Register Set,
Flags, Memory Segmentation,
Address Calculation (2 lectures)
 Introduction Fifth Generation Pentium

Fourth Generation
During 1980s
Low power version of HMOS technology
(HCMOS)
Third Generation 32 bit processors
During 1978 Physical memory space 224 bytes = 16 Mb
HMOS technology  Faster speed, Higher Virtual memory space 240 bytes = 1 Tb
packing density Floating point hardware
16 bit processors  40/ 48/ 64 pins Supports increased number of addressing
Easier to program modes
Dynamically relatable programs
Processor has multiply/ divide arithmetic Intel 80386
hardware
More powerful interrupt handling
capabilities Second Generation
Flexible I/O port addressing During 1973
NMOS technology  Faster speed, Higher
Intel 8086 (16 bit processor) density, Compatible with TTL
4 / 8/ 16 bit processors  40 pins
First Generation Ability to address large memory spaces
Between 1971 – 1973 and I/O ports
PMOS technology, non compatible with TTL Greater number of levels of subroutine
4 bit processors  16 pins nesting
8 and 16 bit processors  40 pins Better interrupt handling capabilities
Due to limitations of pins, signals are
multiplexed Intel 8085 (8 bit processor)
 The Intel Family Addressable
Memory, bytes
= 2A

(A)

 (1978)

Microcontrollers)

 (2000)

Increase Increase
•First 16- bit processor released by
INTEL in the year 1978

•Approximately 29000 transistors,

40 pin DIP, 5V supply

•Does not have internal clock;

external asymmetric clock source
with 33% duty cycle

•20-bit address to access memory

 can address up to 220 = 1 MB of
memory space.
•16 bit data bus

•Operates in two modes: minimum

mode and maximum mode
1- CPU 2- Co-Processor socket 3- RAM 4-CMOS battery 5-Floppy connector 6- Riser slot
Architecture Intel 8086
8086 microprocessor
Architecture

Execution Unit (EU) Bus Interface Unit (BIU)

EU executes instructions that have BIU fetches instructions, reads data

already been fetched by the BIU. from memory and I/O ports, writes
data to memory and I/ O ports.
BIU and EU functions separately.
8086 microprocessor Execution Unit (EU)

EU decodes and
executes instructions.

A decoder in the EU
control system
translates instructions.

16-bit ALU for performing

arithmetic and logic operation

Four general purpose registers(AX,

BX, CX, DX);

Pointer registers (Stack Pointer,

Base Pointer);

and
Some of the 16 bit registers can be
Index registers (Source Index, used as two 8 bit registers as :
Destination Index) each of 16-bits
AX can be used as AH and AL
BX can be used as BH and BL
CX can be used as CH and CL
DX can be used as DH and DL
8086 microprocessor Bus Interface Unit (BIU)

Dedicated Adder to generate 20 bit

address

Four 16-bit segment registers

Code Segment (CS)

Data Segment (DS)
Stack Segment (SS)
Extra Segment (ES)

Segment Registers >>

8086 microprocessor

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

OF DF IF TF SF ZF AF PF CF

Sl.No. Type Register width Name of register

1 General purpose register 16 bit AX, BX, CX, DX

8 bit AL, AH, BL, BH, CL, CH, DL, DH

2 Pointer register 16 bit SP, BP

3 Index register 16 bit SI, DI

4 Instruction Pointer 16 bit IP

5 Segment register 16 bit CS, DS, SS, ES

6 Flag (PSW) 16 bit Flag register

 Memory Segmentation of 8086
•When programmed the 1MB main memory is logically divided into
64KB sections, called segments.
•Depending on the contents, segments are named. There are four
types of segments:
Code Segment contains codes
Data Segment contains data
Extra segment contains data in case of string data transfer
instructions
Stack segment is used for special purposes
•Maximum size of a segment = 64 KB
•Segments could be continuous, disjoint, partially overlapped,
fully overlapped.
•Each program must use at least one Code Segment
•A Program may require more than one Code, Data, Stack and
Extra segments depending on tasks and size.
17
 01101111 1111 1111 1111 (End of Extra
Segment)
----

ES register(16 bits) --- Extra Segment (64KB)

0110 0000 0000 0000 0000H (Base
0110 0000 0000 0000 address -20 bits)
01011111 1111 1111 1111 (end of Stack
Segment)
---- Stack Segment(64KB)

SS register(16 bits) ---

0101 0000 0000 0000 0000H (Base
0101 0000 0000 0000 address - 20 bits)

00101111 1111 1111 1111 (End of Data

Segment)
-----
DS register (16 bits) --- Data Segment(64KB)
0010 0000 0000 0000 0010 0000 0000 0000 0000H (Base
address- 20 bits)
0001 1111 1111 1111 1111 (End of Code
Segment)
----
CS register(16 bits) ---- Code Segment(64KB)
0001 0000 0000 0000 0001 0000 0000 0000 0000H (Base
 Memory Segmentation of 8086
Microprocessor contains 4 Segment registers: CS(Code Segment),
DS(Data Segment), ES(Extra segment) and SS(Stack segment)
to point segments.
Segment registers are 16 bits.
Memory addresses are 20 bits
Segment registers point starting address(also called Base Address)
of corresponding segments.
Since Segment registers hold Upper 16 bits of Base Address
whereas lower 4 bits are assumed to be zeros. So Given the
contents of any segment register, 4 zeros are added to the right to
form Base address. In Hexadecimal code one Zero(0) is added!
Example: Contents of Code Segment Register CS:
0 1 1 0 0 1 1 1 0 1 1 0 1 0 1 1

Base Address of Code Segment is:

0 1 1 0 0 1 1 1 0 1 1 0 1 0 1 1 0 0 019 0
 6FFFFH (End of Extra Segment)
----

ES register(16 bits) --- Extra Segment (64KB)

60000H (Base address -20 bits)
6000H
5FFFFH (end of Stack Segment)
---- Stack Segment(64KB)
---
SS register(16 bits) 50000H (Base address - 20 bits)
5000H

2FFFFH (End of Data Segment)

-----

DS register (16 bits) --- Data Segment(64KB)

20000H (Base address- 20 bits)
2000H
1FFFFH (End of Code Segment)
----
---- Code Segment(64KB)
CS register(16 bits) 10000H (Base address -20 bits)

1000H
 Memory Segmentation of 8086
A 16-digit binary number is reduced to a 4-digit in
Hexadecimal number system. Since 4-digit binary number
is represented by a single digit in Hexadecimal number
system.
So Given the contents of any segment register in
Hexadecimal format, one zero is added to the right to form
Base address.
Example: Contents of Code Segment Register CS: 2A10H
2 A 1 0

Base Address of Code Segment is: 2A100H

2 A 1 0 0
 6FFFFH (End of Extra Segment)
----

ES register(16 bits) --- Extra Segment (64KB)

60000H (Base address -20 bits)
6000H
5FFFFH (end of Stack Segment)
---- Stack Segment(64KB)
---
SS register(16 bits) 50000H (Base address - 20 bits)
5000H

2FFFFH (End of Data Segment)

-----

DS register (16 bits) --- Data Segment(64KB)

20000H (Base address- 20 bits)
2000H
1FFFFH (End of Code Segment)
----
---- Code Segment(64KB)
CS register(16 bits) 10000H (Base address -20 bits)

1000H
The 8086 memory-addressing scheme, using a
segment address plus an offset.
– this shows a memory
segment beginning at
10000H, ending at
location 1FFFFH
• 64K bytes in length

– also shows how an

offset address, called a
displacement, of
F000H selects location
1F000H in the memory

23
 (11MB)
MB

EA (Effective Address) of byte accessed

20-bit (5-byte) 64 KB +
Physical Segment 16-bit each
Memory address

Appended 4 bits (0H)

Segment number
In Segment Register
How does 8086 Microprocessor calculate Physical address
of any memory location?
• Step-1: Segment must be specified and segment register
(CS/SS/DS/ES) should be specified accordingly.
• Step-2: Source of OFFSET/Logical address should be specified
based on Segment.

Segment Offset (16-bit) Purpose

8080, 8086, 80286
IP Program
CS
SP, BP Stack
SS
BX, DI, SI, 8-bit or 16-bit # Data
DS
DI, with string instructions String destination
ES
 Physical Addresses
• Step-3: Base Address/Starting Address of
Segment is formed by converting the 16 bit
contents into 20 bits(4 digits in Hex) by adding
4 zeros (a zero in Hex)to the right to the
contents of segment register.
• Example: CS = [1000H]
• Base address = 10000H
• Step-4: OFFSET/Logical address is added to
Base address to form the Physical address
• Example: IP= [500H]
• Physical address = 10000H + 500H = 10500H
26
 Segmentation: Pros and Cons
Advantages:
• Programs use offsets as logical address, independent of where
segments are located (relocatable)
• Allows easy and efficient relocation of code and data
• To relocate code or data, only the number in the relevant segment
register needs to be changed
Consequences:
A program can be located anywhere in memory without making any
changes to it (addresses are not absolute, but offsets relative to start
of segments)
Program writer needs not worry about actual memory structure
(map) of the computer used to execute it
Disadvantages:
• Complex hardware and for address generation
• Address computation delay for every memory access
• Software limitation: Program size limited by segment size (64KB with
the 8086)
 Calculate Physical Address of Main memory
• Given the contents of CS:IP = [3000H]:[100H]
• Given the contents of SS:SP = [50A0H]:[300H]
• Given the contents of ES:DI = [60C0H]:[200H]
• Given the contents of DS:SI = [A1C0H]:[2F00H]
8086 microprocessor Bus Interface Unit (BIU)

Segment Code Segment Register

Registers
16-bit
CS contains the base or start of the current
code segment; IP contains the distance or
offset from this address to the next instruction
byte to be fetched.
BIU computes the 20-bit physical address by
logically shifting the contents of CS 4-bits to
the left and then adding the 16-bit contents of
IP.
That is, all instructions of a program are
relative to the contents of the CS register
multiplied by 16 and then offset is added
provided by the IP.
8086 microprocessor Bus Interface Unit (BIU)

Segment Data Segment Register

Registers

16-bit

Points to the current data segment;

operands for most instructions are
fetched from this segment.

The 16-bit contents of the Source

Index (SI) or Destination Index (DI) or a
16-bit displacement are used as offset
for computing the 20-bit physical
address.
8086 microprocessor Bus Interface Unit (BIU)
Stack Segment Register

Segment
Registers
16-bit
Points to the current stack.
The 20-bit physical stack address is
calculated from the Stack Segment
(SS) and the Stack Pointer (SP) for
stack instructions such as PUSH and
POP.
In based addressing mode, the 20-
bit physical stack address is
calculated from the Stack segment
(SS) and the Base Pointer (BP).
8086 microprocessor Bus Interface Unit (BIU)

Segment Extra Segment Register

Registers
16-bit

Points to the extra segment in

which data (in excess of 64K
pointed to by the DS) is stored.

String instructions use the ES

and DI to determine the 20-bit
physical address for the
destination.
8086 microprocessor Bus Interface Unit (BIU)

Instruction Pointer

Segment
Registers
16-bit
Always points to the next
instruction to be executed within
the currently executing code
segment.
So, this register contains the
16-bit offset address pointing to
the next instruction code within
the 64Kb of the code segment
area.
Its content is automatically
incremented as the execution of
the next instruction takes place.
8086 microprocessor Bus Interface Unit (BIU)

Instruction queue

A group of First-In-
First-Out (FIFO) in
which up to 6 bytes
of instruction code
are pre fetched from
the memory ahead
of time.
This is done in order
to speed up the
execution by
overlapping
instruction fetch with
This mechanism is execution.
known as pipelining.
8086 microprocessor Execution Unit (EU)

Accumulator Register (AX)

EU Consists of two 8-bit registers AL
Registers and AH, which can be combined
together and used as a 16-bit register
AX.

AL in this case contains the low

order byte of the word, and AH
contains the high-order byte.

The I/O instructions use the AX or

AL for inputting / outputting 16 or 8
bit data to or from an I/O port.

Multiplication and Division

instructions also use the AX or AL.
8086 microprocessor Execution Unit (EU)

Base Register (BX)

EU Consists of two 8-bit registers BL and

Registers
BH, which can be combined together
and used as a 16-bit register BX.

BL in this case contains the low-order

byte of the word, and BH contains the
high-order byte.

This is the only general purpose

register whose contents can be used for
addressing the 8086 memory.

All memory references utilizing this

register content for addressing use DS
as the default segment register.
8086 microprocessor Execution Unit (EU)

Counter Register (CX)

EU
Consists of two 8-bit registers CL and
Registers CH, which can be combined together
and used as a 16-bit register CX.
When combined, CL register contains
the low order byte of the word, and CH
contains the high-order byte.
Instructions such as SHIFT, ROTATE
and LOOP use the contents of CX as a
counter.
Example:
The instruction LOOP START automatically
decrements CX by 1 without affecting flags and
will check if [CX] = 0.

If it is zero, 8086 executes the next instruction;

otherwise the 8086 branches to the label
START.
8086 microprocessor Execution Unit (EU)
Data Register (DX)
Consists of two 8-bit registers DL and
EU DH, which can be combined together
Registers
and used as a 16-bit register DX.

When combined, DL register contains

the low order byte of the word, and DH
contains the high-order byte.

Used to hold the higher 16 bit result

(data) in 16X16 multiplication

Used to hold the higher 16 bit

dividend (data) before a 32 ÷ 16
division and the 16 bit reminder after
division.
8086 microprocessor Execution Unit (EU)

Stack Pointer (SP) and Base

EU Pointer (BP)
Registers SP and BP are used to access data in
the stack segment.
SP is used as an offset from the
current SS during execution of
instructions that involve the stack
segment in the external memory.
SP contents are automatically
updated (incremented/ decremented)
due to execution of a POP or PUSH
instruction.
BP contains an offset address in the
current SS, which is used by
instructions utilizing the based
addressing mode.
 8086 Execution Unit (EU)
Microprocessor

EU Source Index (SI) and

Registers
Destination Index (DI)
Used in indexed
addressing.
Instructions that process
data strings use the SI and
DI registers together with
DS and ES respectively in
order to distinguish between
the source and destination
addresses.
 8086 Execution Unit (EU)
Microprocessor
EU
Registers
Source Index (SI) and Destination
Index (DI)

Used in indexed addressing.

Instructions that process data

strings use the SI and DI registers
together with DS and ES
respectively in order to
distinguish between the source
and destination addresses.
 Flag Register and Flag bits Determined
by last
operation
Flag Bits of 8086: Output, Input bits
• CF – Carry flag (carry/borrow from last operation)
• PF – the parity flag (little used today) Set/Reset
explicitly by the
• AF – auxiliary flag Half-carry between bits 3 and 4, programmer
used with BCD arithmetic
• ZF – zero (indicates whether result is zero) Some flag bits can be both,
• SF – sign (indicates sign of result) e.g. the C flag
• OF – Overflow (indicates overflow if occur)
• DF – direction - Determines auto increment/decrement direction for
SI and DI registers with string instructions
• IF – interrupt - Enables (using STI) or disables (using CLI) the
processing of hardware interrupts arriving at the INTR input pin of
the processor
• TF – Trap - Turns trapping interrupt (for program debugging) on/off
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

OF DF IF TF SF ZF AF PF CF
8086 microprocessor Execution Unit (EU)

Auxiliary Carry Flag

Carry Flag
Flag Register This is set, if there is a carry from the lowest
nibble, i.e, bit three during addition, or borrow This flag is set, when there is a carry
for the lowest nibble, i.e, bit three, during out of MSB in case of addition or a
subtraction. borrow in case of subtraction.

Sign Flag Zero Flag Parity Flag

This flag is set, when the result of This flag is set, if the result of the This flag is set to 1, if the lower byte of the
any computation is negative computation or comparison performed result contains even number of 1’s ; for
by an instruction is zero odd number of 1’s set to zero.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

OF DF IF TF SF ZF AF PF CF

Tarp Flag
Over flow Flag If this flag is set, the processor enters
This flag is set, if an overflow occurs, i.e, if the result of a signed operation is large
the single step execution mode by
enough to accommodate in a destination register. The result is of more than 7-bits
in size in case of 8-bit signed operation and more than 15-bits in size in case of 16-
generating internal interrupts after the
bit sign operations, then the overflow will be set. execution of each instruction

Interrupt Flag
Direction Flag
This is used by string manipulation instructions. If this flag bit is ‘0’, the string
is processed beginning from the lowest address to the highest address, i.e., Causes the 8086 to recognize external mask
auto incrementing mode. Otherwise, the string is processed from the highest interrupts; clearing IF disables these
address towards the lowest address, i.e., auto incrementing mode. interrupts.
8086 microprocessor Architecture Registers and Special Functions

Register Name of the Register Special Function

AX 16-bit Accumulator Stores the 16-bit results of arithmetic and logic operations

AL 8-bit Accumulator Stores the 8-bit results of arithmetic and logic operations

BX Base register Used to hold base value in base addressing mode to access memory
data

CX Count Register Used to hold the count value in SHIFT, ROTATE and LOOP
instructions

DX Data Register Used to hold data for multiplication and division operations

SP Stack Pointer Used to hold the offset address of top stack memory

BP Base Pointer Used to hold the base value in base addressing using SS register to
access data from stack memory

SI Source Index Used to hold index value of source operand (data) for string
instructions

DI Data Index Used to hold the index value of destination operand (data) for string
operations
Instruction-1 Fetch Execute
(BIU) (EU)
Instruction-2 Fetch Execute
(BIU) (EU)
Instruction-3 Fetch Execute
(BIU) (EU)
Instruction-4 Fetch Execute
(BIU) (EU)
Instruction-5 Fetch Execute
(BIU) (EU)
Time T1 T2 T3 T4 T5 T6 T7 T8

Advantage: Lets assume that BIU and EU units require 5 seconds each for Fetch and
Execution of each instruction. So processing of each instruction requires: 5 + 5 = 10
seconds.
In a non-pipelined processor, processing of 1000 instructions would require: 1000 X
10 = 10,000 seconds
In a pipelined processor, to get the output of 1 st instruction, we have to wait for 10
seconds. For the remaining instructions, we get outputs after each 5 seconds!
So the processing of 1000 instructions would require:
10 sec ; (for 1st instructions)
+ 999 X 5; (remaining instructions 1000-1 X 5 seconds)
= 5005 Seconds
For 2-stage pipelining: speed-up factor = (10,000 seconds ÷ 5005 Seconds ) ≈ 2
 Pipelining
• Pipelining is an implementation technique where multiple instructions are
overlapped in execution. The computer pipeline is divided in stages. Each stage
completes a part of an instruction in parallel. The stages are connected one to the
next to form a pipe - instructions enter at one end, progress through the stages,
and exit at the other end.
• Pipelining does not decrease the time for individual instruction execution. Instead,
it increases instruction throughput. The throughput of the instruction pipeline is
determined by how often an instruction exits the pipeline.
• Because the pipe stages are hooked together, all the stages must be ready to
proceed at the same time. We call the time required to move an instruction one
step further in the pipeline a machine cycle . The length of the machine cycle is
determined by the time required for the slowest pipe stage.
• The pipeline designer's goal is to balance the length of each pipeline stage . If the
stages are perfectly balanced, then the time per instruction on the pipelined
machine is equal to

Time per instruction on nonpipelined machine

Number of pipe stages
Under these conditions, the speedup from pipelining equals the number of pipe
stages. Usually, however, the stages will not be perfectly balanced; besides, the
pipelining itself involves some overhead.
 Pipelining
• A form of computer organization in which successive steps of an instruction sequence are
executed in turn by a sequence of modules able to operate concurrently, so that another
instruction can be begun before the previous one is finished.
• In computing, a pipeline is a set of data processing elements connected in series, where
the output of one element is the input of the next one. The elements of a pipeline are
often executed in parallel or in time-sliced fashion; in that case, some amount of
buffer storage is often inserted between elements.
• Computer-related pipelines include:
• Instruction pipelines, such as the classic RISC pipeline, which are used in
central processing units (CPUs) to allow overlapping execution of multiple instructions
with the same circuitry. The circuitry is usually divided up into stages, including instruction
decoding, arithmetic, and register fetching stages, wherein each stage processes one
instruction at a time.
• Graphics pipelines, found in most graphics processing units (GPUs), which consist of
multiple arithmetic units, or complete CPUs, that implement the various stages of
common rendering operations (perspective projection, window clipping, color and light
calculation, rendering, etc.).
• Software pipelines, where commands can be written where the output of one operation is
automatically fed to the next, following operation. The Unix system call pipe is a classic
example of this concept, although other operating systems do support pipes as well
 Probable questions
1. Draw the internal architecture of 8086 microprocessor and indicate its different function units in detail.
2. List CPU registers within execution unit and state their special/default uses in assembly language programming.
3. List CPU registers within BIU and state their special/default uses in assembly language programming.
4. What is flag register? Briefly describe the functions of each flag bit of 8086.
5. State the functions of control flag bits? List some instructions used to set/reset the control flag bits.
6. State the significance of flag register and flag bits? How/why these are used in programs.
7. List the registers and other parts in the 8086/8088 execution and bus interface unit.
8. Describe how the 8086/8088 calculates memory addresses. Give example.
9. What is IP? What is its function?
10. Describe the function of the 8086 instruction queue. State its benefits. Also indicate its possible drawback, if any.
11. What do you understand by pipelining? What is its advantage?
12. What do you understand by memory segmentation technique? State its benefits.
13. How does 8086 microprocessor calculate physical addresses of memory locations within code segment and stack?
14. State the number of stages of pipelining used in 8086. How does it affect the CPU performance?
15. State the benefits of memory segmentation technique used in 8086/8088.
16. How does CPU calculate physical address of a memory location? Explain with suitable examples.
17. List the segment registers and default registers used to hold offset addresses in memory address calculation. Also
mention purpose for each case.
18. What is the maximum size of a segment? How many segments can be used in a program? Briefly state.
19. Given the contents of following register pairs, calculate the physical address of main memory location pointed by
each:
[CS]:[IP]=[1F0AH]:[15A6H],
[SS]:[SP]=[82FFH]:[0FA1H]