Serial I/O Transfers

o Today’s computers operate on digital data in

a parallel fashion.
o Many peripherals handle data in a serial
fashion. Examples are magnetic tapes and
telephone lines.
o A good example of asynchronous serial
communication is the interface between a
keyboard and a computer. In this case, the
keyboard is the transmitter and the computer
is the receiver.
Serial I/O interface is usually a programmable unit
that performs serial to parallel and parallel to serial
conversions as shown in fig. 1
Modem
Modulator (D/A) Demodulator (A/D) converter
Types
Simplex: Device receives or transmits only
Half duplex: Alternate reception and
transmission of data
Full duplex: Simultaneous reception and
transmission of data
Level Normalization
• Voltages of signals from modem or any other
peripheral device are not compatible with the
levels required by digital circuitry.
• These voltage levels are normalized to those
that are used by digital equipment.
• Synchronizing the signals with the timing of
the digital circuitry is also necessary.
• Fig. 2 shows circuits for normalization
Data identification
• When serial strings of continuous word or bytes come
in, the receiving logic has no way of knowing where
one byte ends and where the next one begins.
• It is also not possible to know when there is no
transmitted data
Two methods of identification are used:
• Asynchronous: It is a mode of transmission where
the device stops transmitting any time there is no
legitimate data.
• Synchronous: It sends information in packets rather
than individual in form of a continuous fashion with
dummy characters in the blank slots.
Universal Asynchronous Receiver transmitter (UART)
Asynchronous:
• Asynchronous transmission is used in systems
that utilise serial peripherals at low data rates (as
low as 30 characters per second).
• Common data lengths are 7 bit in length to
accommodate the 7 bit ACII character and the 8-
bit length for extended ASCII characters.
• Such systems require interface that generate and
check parity bits, recognise or add start and stop
bits so that bits can be properly be identified.
• Fig. 3 shows a asynchronous data frame.
• The systems are also required to accept the
appropriate control and status signals.
• In most protocols the start bit is a logic 0 while the
stop bit is logic 1. Therefore, when no data is being
sent the data line is continuously HIGH.
• Medium speeds range from 30 to 500 characters per
seconds. High speeds can go up to 115200 bits per
seconds
Functions:
• Serial data into parallel and vice versa formats .
• Generate appropriate parity bits and frame of the data.
• Receive data, check parity, format and synchronize the
system, establish voltage levels.
Timing and synchronization
• UART generally use a clock rate that is either 16
or 64 times the frequency of the bit rate or bit
time.
• The high to low transition on the signal line starts
the clock in the receiver portion of the UART or
the peripheral.
• Bit time (tb): Time duration of any of the bits of
a character which includes the start bit, parity and
stop bits.
Tb = K X tcp where tcp is the clock period
of the receiver clock
Baud and Data rates:

• Baud rate is the bit rate at which serial transmission of data takes
place. It establishes the number of bits transmitted per second.
• B = Nc x C where C is the number of characters transmitted per second.
tb =1/B
• Data rates Dr = Db x C, where Dr = data rate expressed in bits / sec,
Db = Data bits per character.

Elimination of false start / true start

• High to low transition starts a counter in the receiver.
Methods:
1. Consecutive zeros
2. Half bit length wait
Preference is method 2
• To combat this, on a 1 to 0 transition the
receiver waits for one half bit length and then
tests the RXD line again.
• If RXD is still at logic 0 then this qualifies as a
genuine start bit and the receiver shifts the eight
data bits into the shift register.
UART Initiation

SF-Status flag enable (1) /disable (0), Baud rate (0-

clock rate = 16, 1- clock rate 64)
SB-Stop bit (0-1, 1-2 stop bits), PS-parity status (0-
odd, 1-even)
PI-Parity initialization (0-No parity, 1-parity used)
DWL-Data word length (00-5 bits, 01-16, 10-7 and
11-8), MC-Master clear.
Synchronous Data transfer
• Information is transmitted continuously without gaps
between adjacent groups of bits.
• Note that synchronous data links are often used to
transmit entire blocks of data instead of ASCII-
encoded characters.
• This type of link involves long streams of data.
• Clocks at the receiving and transmitting end must be
permanently synchronized.
• A clock line can be used to link transmitter and
receiver. However, a better solution is to encode the
data in such a way that the synchronizing signal is
included in the data signal.
• Figure below shows one of the many methods which
may be used. In this case the data is phase-encoded
(or Manchester encoded) by combining the clock
signal with the data signal.
• A logical one is thus represented by a positive
transition in the centre of the bit and a logical zero by
a negative transition.
• At the receiver, the data signal may easily be split into
the clock and pure data components using
demodulator circuits.
• The incoming data must be examined for recognizable
bit groups which signify the beginning of a block of
data, the end of it or some other control character. 
USART
• Most equipment used in microcomputer systems
receives and transmits serial data in synchronous
mode.
• To accommodate such systems an interface chip
called Universal Synchronous Asynchronous
Receiver Transmitter is available.
• The difference between UART and USRT is the
use of SYNC pattern to capture the data word.
• The USART has both modes of operation and
hence an additional mode bit is included in the
control word.