UNIT-IV

• Introduction to HDLs: VLSI Design flow, Basic Concepts of Verilog HDL,

Data Types, System Tasks and Compiler Directives. Gate Level
Modelling: Gate Types and Gate Delays. Dataflow Modeling:
Continuous Assignment and Delays.Design of Stimulus Block.

07/19/2023 Dr.B.KHALEELU REHMAN,Assoc Proff ECE Dept,CBIT(A) 1

Text Books:
1. Morris Mano M. and Michael D.Ciletti, “Digital Design, With an
Introduction to Verilog HDL”, 5th Edition,Pearson 2013.
2. Samir Palnitkar, “Verilog HDL, A guide to Digital design and
synthesis”, 2nd Edition, Pearson Education, 2008.

07/19/2023 Dr.B.KHALEELU REHMAN,Assoc Proff ECE Dept,CBIT(A) 2

 Dataflow Modeling
• module • module ful_add(s,cr,a,b,c);
logic_gates(y0,y1,y2,y3,y4,y5,a,b);
• input a,b; • input a,b,c;
• output y0,y1,y2,y3,y4,y5; • output s,cr;
• assign y0=a&b; • assign s=(a^b^c);
• assign y1=a|b;
• assign cr=((a&b)|(b&c)|(a&c));
• assign y2=a^b;
• assign y3=~(a&b); • endmodule
• assign y4=~(a|b);
• assign y5=~(a^b);
• endmodule

07/19/2023 Dr.B.KHALEELU REHMAN,Assoc Proff ECE Dept,CBIT(A) 3

Dataflow Modeling examples
• module
comparator_2b(l,e,g,a1,a0,b1,b0);
• module comparator(l,e,g,a,b); • input a1,a0,b1,b0;
• input a,b; • output l,e,g;
• output l,e,g; • assign l=(a1&~b1)|(~a1&~a0&b0)|
• assign l=(~a&b); • (a1&~a0&b1&b0);
• assign e=(~a1&~a0&~b1&~b0)|
• assign e=(~a&~b)|(a&b); (~a1&a0&~b1&b0)|
• assign g=(a&~b); • (a1&a0&b1&b0)|(a1&~a0&b1&~b0);
• endmodule • assign g=(a1&~b1)|(a0&~b1&~b0)|
• (a1&a0&b1&~b0);
• endmodule

07/19/2023 Dr.B.KHALEELU REHMAN,Assoc Proff ECE Dept,CBIT(A) 4

 Multiplexer and demultiplexer
• module mux4b1_data(i0,i1,i2,i3,s0,s1,y); • module
• input i0,i1,i2,i3,s0,s1; demux4b1(y0,y1,y2,y3,s0,i,s1);
• output y;
• wire d,e,f,g,h,i;
• input s0,s1,i;
• assign h= ~s0; • output y0,y1,y2,y3;
• assign i= ~s1;
• assign y0=(~s0)&(~s1)&i;
• assign d=(i0&h&i);
• assign e=(i1&h&s1); • assign y1=s0&(~s1)&i;
• assign f=(i2&s0&i); • assign y2=(~s0)&s1&i;
• assign g=(i3&s0&s1);
• assign y=(d|e|f|g);
• assign y3=s0&s1&i;
• endmodule • endmodule
07/19/2023 Dr.B.KHALEELU REHMAN,Assoc Proff ECE Dept,CBIT(A) 5
 Continuous Assignments
The statement is evaluated at any time any of the source operand value changes, and the
result is assigned to the destination net after the delay unit.

The LHS of the assign statement must always be a scalar or vector net or a concatenation. It
cannot be a register.

Continuous statements are always active statements, which means that if any value on the
RHS changes, LHS changes automatically.

Registers or nets or function calls can come in the RHS of the assignment.

The RHS expression is evaluated whenever one of its operands changes. Then the result is
assigned to the LHS.
Delays can be specified in the assign statement.
07/19/2023 Dr.B.KHALEELU REHMAN,Assoc Proff ECE Dept,CBIT(A) 6
07/19/2023 Dr.B.KHALEELU REHMAN,Assoc Proff ECE Dept,CBIT(A) 7
Data flow modelling Delays
• 1. Regular Assignment Delay
• We assign a delay value in the continuous assignment statement. The delay value is
specific
• This delay is applicable when the signal in LHS is already defined, and this delay
represents the delay in changing the value of the already declared net. For example,ed
after the assign keyword.
• If there is any change in the RHS operands, then RHS expression will be evaluated after
10 units of time and the evaluated expression will be assigned to LHS.
• At time t, if there is a change in one of the operands in the above example, then the
expression is calculated at t+10 units of time.
• It means that if in0 or in1 changes value before 10-time units, then the values of in1
and in2 at the time of re-computation (t+10) are considered.
• assign #10 out = in0 & in1;   

07/19/2023 Dr.B.KHALEELU REHMAN,Assoc Proff ECE Dept,CBIT(A) 8

Regular Assignment Delay example

07/19/2023 Dr.B.KHALEELU REHMAN,Assoc Proff ECE Dept,CBIT(A) 9

2. Implicite Continuos Assignement Delay
• Here, we use an implicit continuous assignment to specify both a
delay and an assignment on the net.
• wire #10 out = in0 ^ in1;        //implicit Continuous Assignment Delay.  

07/19/2023 Dr.B.KHALEELU REHMAN,Assoc Proff ECE Dept,CBIT(A) 10

3. Net Declaration Delay
• In this case, the delay is associated with the net instead of the
assignment.
• Here, a delay is added when the net is declared without putting
continuous assignment

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 Verilog Operators

• 1. Arithmetic Operators

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 1. Arithmetic Operators
• 2. Bitwise Operators

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 These operators reduce the 3. vectors toOperators
Reduction only one bit. If there are the
characters z and x, the result can be a known value

07/19/2023 Dr.B.KHALEELU REHMAN,Assoc Proff ECE Dept,CBIT(A) 14

 4. Relational Operators
These operators compare operands and results in a 1-bit scalar Boolean value. The case
equality and inequality operators can be used for unknown or high impedance values (z or x),
and if the two operands are unknown, the result is a 1.

07/19/2023 Dr.B.KHALEELU REHMAN,Assoc Proff ECE Dept,CBIT(A) 15

5. Shift Operators

• These operators shift operands to the right or left, the size is kept
constant, shifted bits are lost, and the vector is filled with zeroes.

Other Operators

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Conditional Operator

07/19/2023 Dr.B.KHALEELU REHMAN,Assoc Proff ECE Dept,CBIT(A) 17

Stimulus block or test bench or DUT
module tb_full_add;
reg a;reg b;reg c;
wire sum;wire cout;
full_add uut (.a(a),.b(b),.c(c),.sum(sum),.cout(cout));
initial begin
$monitor($time, "input a=%b,b=%b,c=%b,output:sum=
%b, cout=%b",a,b,c,sum,cout);
a = 0;b = 0;c =0;
#100 a=0;b=1;c=0;
#50 a=1;b=1;c=0;
#50 a=1;b=1;c=1;
#50 a=1;b=0;c=1;
#50 a=0;b=1;c=1;
end
endmodule
07/19/2023 Dr.B.KHALEELU REHMAN,Assoc Proff ECE Dept,CBIT(A) 18
module tb_full_add;
reg a;reg b;reg c;
wire sum;wire cout;
full_add uut (.a(a),.b(b),.c(c),.sum(sum),.cout(cout));
initial begin
$monitor($time,"\tinput:a=%d,b=%d,c=%d,output:sum=
%d, cout=%d",a,b,c,sum,cout);
a = 0;b = 0;c =0;
#100 a=0;b=1;c=0;
#50 a=1;b=1;c=0;
#50 a=1;b=1;c=1;
#50 a=1;b=0;c=1;
end
endmodule

07/19/2023 Dr.B.KHALEELU REHMAN,Assoc Proff ECE Dept,CBIT(A) 19

UNIT-V
• Behavioral Modeling: Structured Procedures, Procedural
Assignments, Timing control, Conditional statements, Sequential and
Parallel Blocks. Switch level Modelling. Introduction to tasks and
functions. Design of Mealy and Moore state models using Verilog
HDL. Introduction to Logic Synthesis. Concept of Programming using
FPGA.

07/19/2023 Dr.B.KHALEELU REHMAN,Assoc Proff ECE Dept,CBIT(A) 20