Chapter 2:

x86 Processor Architecture

Chapter Overview
•General Concepts
•x86 Processor Architecture details
•x86 Memory Management
•Components of an x86 Microcomputer
•Input-Output System

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General Concepts
•Basic microcomputer design
•Instruction execution cycle
•Reading from memory
•How programs run

3
Basic Microcomputer Design
•clock synchronizes CPU operations
•control unit (CU) coordinates sequence of execution steps
•ALU performs arithmetic and bitwise processing

data bus

registers

I/O I/O
Central Processor Unit Memory Storage
Device Device
(CPU) Unit
#1 #2

ALU CU clock

control bus

address bus

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Clock
•synchronizes all CPU and BUS operations
•machine (clock) cycle measures time of a
single operation
•clock is used to trigger events
•The duration of a clock cycle is calculated as
the reciprocal of the clock’s speed, which in
turn is measured in oscillations per second.
•A clock that oscillates 1 billion times per
second(1 GHz), for example, produces a clock
cycle with a duration of one billionth of a
second (1 nanosecond).
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 Instruction Execution Cycle
•Fetch: The control unit fetches the next instruction from
the instruction queue and increments the instruction
pointer (IP). The IP is also known as the program counter.
•Decode: The control unit decodes the instruction’s
function to determine what the instruction will do.
•Fetch operands: If the instruction uses an input operand
located in memory, the control unit uses a read operation
to retrieve the operand and copy it into internal registers.
•Execute :The ALU executes the instruction using the
named registers and internal registers as operands and
sends the output to named registers and/or memory.
•Store output

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7
Reading from Memory
•Multiple machine cycles are required when reading from memory,
because it responds much more slowly than the CPU. The steps are:
– address placed on address bus
– Read Line (RD) set low
– CPU waits one cycle for memory to respond
– Read Line (RD) goes to 1, indicating that the data is on the data bus

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Cache Memory
•High-speed expensive static RAM both inside
and outside the CPU.
– Level-1 cache: inside the CPU
– Level-2 cache: outside the CPU
•Cache hit: when data to be read is already in
cache memory
•Cache miss: when data to be read is not in
cache memory.

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 How programs run
 The operating system (OS) searches for the program’s filename in the
current disk directory. If the OS fails to find the program filename, it
issues an error message.
 If the program file is found, the OS retrieves basic information about the
program’s file from the disk directory, including the file size and its
physical location on the disk drive.
 The OS determines the next available location in memory and loads the
program file into memory. It allocates a block of memory to the program
and enters information about the program’s size and location into a table
(sometimes called a descriptor table).
 The OS begins execution of the program’s first machine instruction. As
soon as the program begins running, it is called a Process . The OS
assigns the process an identification number ( process ID )
 The process runs by itself. It is the OS’s job to track the execution of the
process and to respond to requests for system resources.
 When the process ends, it is removed from memory.

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Multitasking
•OS can run multiple programs at the same time.
•Multiple threads of execution within the same
program.
•Scheduler utility assigns a given amount of CPU
time to each running program.
•Rapid switching of tasks
– gives illusion that all programs are running at once
– the processor must support task switching.

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X86 Processor Architecture Details
•Modes of operation
•Basic execution environment
•Floating-point unit
•Intel Microprocessor history

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Modes of Operation
•Protected mode
– native mode (Windows, Linux)
•Real-address mode
– native MS-DOS
•System management mode
– power management, system security, diagnostics

Virtual-8086 mode
 hybrid of Protected
 each program has its own 8086 computer

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Basic Execution Environment
•Addressable memory
•General-purpose registers
•Index and base registers
•Specialized register uses
•Status flags
•Floating-point, MMX, XMM
registers

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Addressable Memory
•Protected mode
– 4 GB
– 32-bit address
•Real-address and Virtual-8086
modes
– 1 MB space
– 16-bit address

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General-Purpose Registers
Named storage locations inside the CPU, optimized for speed.

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Accessing Parts of Registers
•Use 8-bit name, 16-bit name, or 32-bit name
•Applies to EAX, EBX, ECX, and EDX

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Index and Base Registers
•Some registers have only a 16-bit name for
their lower half:

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Some Specialized Register Uses
•General-Purpose
– EAX – accumulator
– EBX – Base Register
– ECX – loop counter
– ESP – stack pointer
– ESI, EDI – index registers
– EBP – extended frame pointer (stack)
•Segment
– CS – code segment
– DS – data segment
– SS – stack segment
– ES, FS, GS - additional segments
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Some Specialized Register Uses
•EIP – instruction pointer
•EFLAGS
– status and control flags
– each flag is a single binary bit

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Status Flags
•Carry
– unsigned arithmetic out of range
•Overflow
– signed arithmetic out of range
•Sign
– result is negative
•Zero
– result is zero
•Auxiliary Carry
– carry from bit 3 to bit 4
•Parity
– sum of 1 bits is an even number

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Floating-Point, MMX, XMM
Registers 80-bit Data Registers
•Eight 80-bit floating-point data registers 48-bit Pointer Registers
ST(0)
– ST(0), ST(1), . . . , ST(7) ST(1)
FPU Instruction Pointer

– arranged in a stack ST(2) FPU Data Pointer

ST(3)
– used for all floating-point arithmetic ST(4) 16-bit Control Registers
•Eight 64-bit MMX registers ST(5) Tag Register
•Eight 128-bit XMM registers for single-instruction ST(6) Control Register
multiple-data (SIMD) operations ST(7) Status Register

Opcode Register

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Intel Microprocessor History
•Intel 8086, 80286
•IA-32 processor family
•P6 processor family
•CISC and RISC

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Early Intel Microprocessors
•Intel 8080
– 64K addressable RAM
– 8-bit registers
– CP/M operating system
– S-100 BUS architecture
– 8-inch floppy disks!
•Intel 8086/8088
– IBM-PC Used 8088
– 1 MB addressable RAM
– 16-bit registers
– 16-bit data bus (8-bit for 8088)
– separate floating-point unit (8087)

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The IBM-AT
•Intel 80286
– 16 MB addressable RAM
– Protected memory
– several times faster than 8086
– introduced IDE bus architecture
– 80287 floating point unit

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Intel IA-32 Family
•Intel386
– 4 GB addressable RAM, 32-bit registers,
paging (virtual memory)
•Intel486
– instruction pipelining
•Pentium
– superscalar, 32-bit address bus, 64-bit
internal data path

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64-bit Processors
•Intel64
– 64-bit linear address
– Intel: Pentium Extreme, Xeon, Celeron D, Pendium
D, Core 2, and Core i7
•IA-32e Mode
– Compatibility mode for legacy 16- and 32-bit
applications
– 64-bit Mode uses 64-bit addresses and operands

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Intel Technologies
•HyperThreading technology
– two tasks execute on a single processor at the same
time

•Dual Core processing

– multiple processor cores in the same IC package
– each processor has its own resources and
communication path with the bus

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Intel Processor Families
Currently Used:
•Pentium & Celeron – dual core
•Core 2 Duo - 2 processor cores
•Core 2 Quad - 4 processor cores
•Core i7 – 4 processor cores

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CISC and RISC
•CISC – complex instruction set
– large instruction set
– high-level operations
– requires microcode interpreter
– examples: Intel 80x86 family
•RISC – reduced instruction set
– simple, atomic instructions
– small instruction set
– directly executed by hardware
– examples:
• ARM (Advanced RISC Machines)
• DEC Alpha (now Compaq)

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IA-32 Memory Management
•Real-address mode
•Calculating linear addresses
•Protected mode
•Multi-segment model
•Paging

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Real-Address mode
•1 MB RAM maximum addressable
•Application programs can access any
area of memory
•Single tasking
•Supported by MS-DOS operating
system

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Segmented Memory
Segmented memory addressing: absolute (linear) address is a
combination of a 16-bit segment value added to a 16-bit offset
Each segment begins with an address having a 0 as it’s last hex digit

F0000
E0000 8000:FFFF
8FFFF
D0000 Linear Address
C0000
B0000
linear addresses

A0000
90000
one segment
80000
70000
60000
8000:0250
50000
0250
40000
30000 8000:0000
80000
20000
10000
seg ofs
00000

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Calculating Linear Addresses
•Given a segment address, multiply it by 16
(add a hexadecimal zero), and add it to the
offset
•Example: convert 08F1:0100 to a linear
address
Adjusted Segment value: 0 8 F 1 0
Add the offset: 0 1 0 0
Linear address: 0 9 0 1 0

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example
What linear address corresponds to the segment/offset address 028F:0030?

028F0 + 0030 = 02920

Always use hexadecimal notation for addresses.

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Another example
What segment addresses correspond to the linear address 28F30h?

Many different segment-offset addresses can produce the linear address

28F30h. For example:
28F0:0030, 28F3:0000, 28B0:0430, . . .

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Protected Mode
•4 GB addressable RAM
– (00000000 to FFFFFFFFh)
•Each program assigned a memory
partition which is protected from other
programs
•Designed for multitasking
•Supported by Linux & MS-Windows

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Protected mode
•Segment descriptor tables
•Program structure
– code, data, and stack areas
– CS, DS, SS segment descriptors
– global descriptor table (GDT)
•MASM Programs use the Microsoft flat
memory model

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Flat Segment Model
•Single global descriptor table (GDT).
•All segments mapped to entire 32-bit address space

FFFFFFFF
(4GB)

not used
Segment descriptor, in the
Global Descriptor Table
00040000

base address limit access

physical RAM
00000000 00040 ----

00000000

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Multi-Segment Model
•Each program has a local descriptor table (LDT)
– holds descriptor for each segment used by the program

RAM

Local Descriptor Table

26000
base limit access
00026000 0010
00008000 000A
00003000 0002 8000

3000

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Paging
•Supported directly by the CPU
•Divides each segment into 4096-byte blocks
called pages
•Sum of all programs can be larger than physical
memory
•Part of running program is in memory, part is on
disk
•Virtual memory manager (VMM) – OS utility that
manages the loading and unloading of pages
•Page fault – issued by CPU when a page must be
loaded from disk
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Components of an IA-32
Microcomputer
•Motherboard
•Video output
•Memory
•Input-output ports

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Motherboard
•CPU socket
•External cache memory slots
•Main memory slots
•BIOS chips
•Sound synthesizer chip (optional)
•Video controller chip (optional)
•IDE, parallel, serial, USB, video, keyboard,
joystick, network, and mouse connectors
•PCI bus connectors (expansion cards)
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 Intel D850MD Motherboard mouse, keyboard, parallel,
serial, and USB connectors
Video

Audio chip

PCI slots
memory controller hub
Pentium 4 socket
AGP slot

dynamic RAM

Firmware hub

I/O Controller
Speaker Power connector
Battery
Diskette connector
Source: Intel® Desktop Board D850MD/D850MV Technical Product Specification IDE drive connectors

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Intel 965 Express Chipset

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Video Output
•Video controller
– on motherboard, or on expansion card
– AGP (accelerated graphics port
technology)
•Video memory (VRAM)
•Video CRT Display
– uses raster scanning
– horizontal retrace
– vertical retrace
•Direct digital LCD monitors
– no raster scanning required

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Sample Video Controller (ATI Corp.)
 128-bit 3D graphics
performance powered by
RAGE™ 128 PRO
 3D graphics performance
 Intelligent TV-Tuner with
Digital VCR
 TV-ON-DEMAND™
 Interactive Program Guide
 Still image and MPEG-2
motion video capture
 Video editing
 Hardware DVD video playback
 Video output to TV or VCR

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Memory
•ROM
– read-only memory
•EPROM
– erasable programmable read-only memory
•Dynamic RAM (DRAM)
– inexpensive; must be refreshed constantly
•Static RAM (SRAM)
– expensive; used for cache memory; no refresh required
•Video RAM (VRAM)
– dual ported; optimized for constant video refresh
•CMOS RAM
– complimentary metal-oxide semiconductor
– system setup information

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Input-Output Ports
•USB (universal serial bus)
– intelligent high-speed connection to
devices
– up to 12 megabits/second
– USB hub connects multiple devices
– enumeration: computer queries devices
– supports hot connections
•Parallel
– short cable, high speed
– common for printers
– bidirectional, parallel data transfer
– Intel 8255 controller chip

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Input-Output Ports (cont)
•Serial
– RS-232 serial port
– one bit at a time
– uses long cables and modems
– 16550 UART (universal asynchronous
receiver transmitter)
– programmable in assembly language

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Device Interfaces
•ATA host adapters
– intelligent drive electronics (hard drive, CDROM)
•SATA (Serial ATA)
– inexpensive, fast, bidirectional
•FireWire
– high speed (800 MB/sec), many devices at once
•Bluetooth
– small amounts of data, short distances, low
power usage
•Wi-Fi (wireless Ethernet)
– IEEE 802.11 standard, faster than Bluetooth

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Input output
Levels of Input-Output
•Level 3: High-level language function
– examples: C++, Java
– portable, convenient, not always the fastest
•Level 2: Operating system
– Application Programming Interface (API)
– extended capabilities, lots of details to master
•Level 1: BIOS
– drivers that communicate directly with devices
– OS security may prevent application-level code from working at this level

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Displaying a String of Characters

When a HLL program

displays a string of
characters, the following
steps take place:

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Programming levels
Assembly language programs can perform input-output
at each of the following levels:

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Summary
•Central Processing Unit (CPU)
•Arithmetic Logic Unit (ALU)
•Instruction execution cycle
•Multitasking
•Floating Point Unit (FPU)
•Complex Instruction Set
•Real mode and Protected mode
•Motherboard components
•Memory types
•Input/Output and access levels 55