COE 202: Digital Logic Design

Courtesy of Dr Radwan E Abdel-Aal

Logic and Computer Design Fundamentals

Chapter 3Unit 11
– Combinational
Sequential Circuits
Logic Design
Part 1 – Implementation Technology and Logic
Design
Charles Kime & Thomas Kaminski
© 2004 Pearson Education, Inc.
Terms of Use
(Hyperlinks are active in View Show mode)
 Unit 11: Sequential Circuits
1. Sequential Circuit Definitions, Types of Latches: SR,
Clocked SR, and D Latches
2. Flip-Flops: SR, D, JK, and T Flip-Flops
3. Flip-Flop Timing Parameters: Setup, hold,
propagation, clocking
4. Flip-Flops: Characteristic and Excitation Tables
5. Analysis of Sequential Circuits with D flip-flops:
Deriving the input equations, state table, and state
diagram. Timing.
6. Design of Sequential Circuits with D flip-flops:
Determining the state diagrams and tables, State
assignment, Combinational Logic

Chapter 3 - Part 1 2
Logic and Computer Design Fundamentals
Chapter 3 – Combinational
Chapter 5Logic Design Circuits
- Sequential
Part 1 – Implementation Technology and Logic
Design
Charles Kime & Thomas Kaminski
© 2004 Pearson Education, Inc.
Terms of Use
(Hyperlinks are active in View Show mode)
 Introduction to Sequential Circuits

State
Variables

 A Sequential circuit consists of: The storage elements isolate

The next state from the present
• Data Storage elements: state, So that the change occurs
(Latches / Flip-Flops) only when required
• Combinatorial Logic:
 Implements a multiple-output function
 Inputs are signals from the outside
 Outputs are signals to the outside
 State inputs (Internal): Present State from storage elements
 State outputs, Next State are inputs to storage elements
Chapter 3 - Part 1 4
 Introduction to Sequential Circuits

(State) (State)

 Combinatorial Logic
• Next state function
Next State = f(Inputs, State)
• 2 output function types : Mealy &Moore
• Output function: Mealy Circuits
Outputs = g(Inputs, State)
• Output function: Moore Circuits
Outputs = h(State)
 Output function type depends on specification and affects the
design significantly
Chapter 3 - Part 1 5
 Timing of Sequential Circuits
Two Approaches
 Behavior depends on the times at which storage elements ‘see’ their inputs
and change their outputs (next state  present state)
 Asynchronous
• Behavior defined from knowledge of inputs at any instant of time and the
order in continuous time in which inputs change
 Synchronous
• Behavior defined from knowledge of signals at discrete instances of
time
• Storage elements see their inputs and change state only in relation to a
timing signal (clock pulses from a clock)
• The synchronous abstraction allows handling complex designs!

Storage Elements

Chapter 3 - Part 1 6
 Data Storage Logic Structures
tpd
Data In (Change data stored)

Output-Supporting
feedback

Delay in Feedback across

A non-inverting Two inverting buffers
Buffer Connected in series
Set-Reset
Non-inverting buffer
NOR Latch
Problem: With feedback- indefinite
Data stored only Problem: No separate input for data. Separate inputs for
for short time, i.e. Difficult to change data stored Data in and for
Propagation delay tpd feedback
Chapter 3 - Part 1 7
 Basic NOR Set–Reset (SR) Latch
 Cross-coupling two R (reset)
Q
NOR gates gives the
S – R Latch:
 Which has the time S (set) Q
sequence
Time R S Q Q Comment
behavior: 0 0 ? ? Stored state unknown
00 = Normal input condition
0 1 1 0 “Set” Q to 1 (change data)
No input change 0 0 1 0 Now Q “remembers” 1
1 0 0 1 “Reset” Q to 0 (change data)
Input R S stored in Q Q 0 0 0 1 Now Q “remembers” 0
(remains at O/P after input 1 1 0 0 Both Q and Q go low (Avoid)
is removed)
0 0 ? ? Undefined!

S = 1, R = 1 is a forbidden input pattern Chapter 3 - Part 1 8

 Basic NOR Set–Reset (SR) Latch

Should not try to Set

and Reset at the same time!
Reset then 00 Set then 00 Forbidden I/Ps

0
Which
Changes
First?
0
Unpredictable

Q_b = Q Chapter 3 - Part 1 9

 Basic NAND Set–Reset (SR) Latch
 Cross-coupling two R (reset)
Q
NAND gates gives the
S – R Latch:
 Which has the time S (set) Q
sequence
Time S R Q Q Comment
behavior: 1 1 ? ? Stored state unknown
11 = Normal input condition
0 1 1 0 “Set” Q to 1 (change data)
No input change 1 1 1 0 Now Q “remembers” 1
1 0 0 1 “Reset” Q to 0 (change data)
Input S R stored in Q Q 1 1 0 1 Now Q “remembers” 0
(remains at O/P after input 0 0 1 1 Both Q and Q go high (Avoid)
is removed)
1 1 ? ? Undefined!

S = 0, R = 0 is a forbidden input pattern Chapter 3 - Part 1 10

 Clocked (or controlled) SR NAND Latch
 Adding two NAND
gates to the basic
S - R NAND latch
gives the clocked
S – R latch: This latch is also
Transparent:
 C = normally 0  S R inputs to the latch = normally 1 1O/P changes directly
(No output change) With the I/P at C = 1
i.e. this prevents the forbidden conditions S R = 0 0 with C = 0
 C = 1 Opens the two input NANDs
for the S R, inverting them.
This gives normal S R (not S R)
latch operation  Allow changes in latch state
But here S R = 1 1 during C = 1 still a problem
 C means “control” or “clock”. Changes
introduced by SR only during the clock pulse Chapter 3 - Part 1 11
 The D Latch
S
 Adding an inverter D
Q
to the S-R Latch,
C
gives the D Latch
 Now S R can not become 1 1 Q

 So we got rid of the remaining R

To get ‘no change’:
block the clock pulse
unwanted condition
(SR =11 with C = 1)
This latch
is transparent:
With C = 1,
Input D is C=1 C = 0:
Freeze Output at last value Function Table
‘connected’ entered when C was 1,
to output Q (store it till next time C becomes 1)
Chapter 3 - Part 1 12
Flip-Flops
 The latch timing problem
 Solution: Flip-Flop
• Master-slave flip-flop
• Edge-triggered flip-flop
 Standard symbols for storage elements
 Direct inputs to flip-flops
 Flip-flop timing

Chapter 3 - Part 1 13
The Transparent Latch as a Storage Element:
Timing Problem of the transparent Latch
 Consider the following circuit: t Y-Y
Represents
 Transparent latch
The Combinational
is problematic! Circuit part
Clock Pulse Width
tCW
Clock t Y-Y
Y The latch was supposed
to isolate outputs of
 Suppose that initially Y = 0. Combinational circuit
 As long as C = 1, the value of Y keeps changing! from its inputs
 Changes occur based on the delay in the Y-to-Y loop
 If tY-Y < tCW this causes unwanted multiple state changes to occur
during one clock pulse- unacceptable!
 Desired behavior: Y changes only once per clock pulse,
i.e. one state transition per clock pulse
Chapter 3 - Part 1 14
 Solving the Latch Timing Problem
Flip flops instead of latches
 Two approaches:
• Break the closed path from Y to Y within the storage element
into 2 successive (mutually exclusive) steps in time:
- 1. Sense the change in the input D (then stop)
- 2. Apply that change to the output Y (then stop)
This uses a master-slave (Pulse Triggered) flip-flop
• Use an edge-triggered flip-flop:
Change in D is sensed and applied to the Q output in
one go at the clock pulse edge (+ ive or – ive)
This is similar to effectively having a 0 width of the clock
pulse which solves the problem

Chapter 3 - Part 1 15
 S-R Master-Slave (Pulse-Triggered)
Flip-Flop
C=1
X
 Consists of two clocked S S X Q S
C=0
Q Q
S-R latches in series C C Master C Slave
with the clock to the R R Q R Q Q
second latch inverted
 C = 1: - Master is open C =1 C =0

- Slave is blocked
Only “input is sensed” by master for this pulse duration
(pulse-triggered) while output is unchanged by slave
 C = 0: - Master is Blocked
- Slave is open  “output is changed”
 The path from input to output is thus broken by the difference in
clocking values for the two latches (C = 1 and C = 0)
 Sensing I/P and changing O/P are now two separate steps -
not one transparent step as with the transparentChapter
D latch
3 - Part 1 16
 Z
S-R Master-Slave S
Flip-Flop: Simulation
Ideally, changes in S, R inputs from combinational circuit
Should arrive before the next clock interval 2 pulses
(C=1 pulse) arrives. On S, R inputs arrive late
Data appears during + ive Clk 1 pulse
at slave O/P  But no problem On S input
arrives late
Clock Set Reset during + ive Clk
Interval T  Problem

M S
X Forbidden
0 0 Condition
S = 1, R = 1
Still
0 0 possible
X
X
In Out X
Delay T/2
= T/2 X
Z 0 0 1

Consider O/P Error

Delay in Combinational Performance of the due to the
Circuit Latch as a whole Chapter
pulse on3S- Part 1 17
 Problems with the S-R Master-Slave Flip-
Flop
 The undesirable condition of S = 1 and R = 1 simultaneously is still
possible (latches are S-R not D)  Master-Slave D type is possible
 T/2 input-to-output delay (width of the C = 1 pulse), which may slow
down the sequential circuit
 While C = 1, master stage is open, and any changes in the input
S, R affect FF operation  The 1s catching behavior
• Suppose Q = 0 and S goes to 1 and back to 0 and R goes to 1
and back to 0 (all within C = 1 pulse)
 The master latch sets and then resets so slave not affected
 A 0 is transferred to the slave (correct)
• Suppose Q = 0 and S goes to 1 and then back to 0 with R
remaining at 0 (all within C = 1 pulse)
 The master latch sets to 1
 A 1 is transferred to the slave (wrong)
Solution:
Ensure data input to FF (to master) is valid before start of + ive clock
Chapter pulse
3 - Part 1 18
 Edge-Triggered D-type Flip-Flop
 This is a Positive
Edge-triggered D flip-flop

 This is the preferred FF

used nowadays to build
most sequential
circuits DQ

 The D data input is transferred to the Q output only at

the rising edge of the clock, subject to timing constraints
on the D input must relative to effective clock edge:
Setup time before edge and Hold time after edge

Chapter 3 - Part 1 19
 Flip-Flop Timing Parameters:
Edge Triggered FF
Q
Requirements:
Negative Edge-Triggered
 tw - clock
pulse width D Flip Flop
(for both low & high)

 ts : setup time
Input transitions allowed
 th : hold time
Valid, Stable
(usually 0 ns)
Outcomes:
 tp: propagation delay Old Data on Q New Data on Q
• tPHL :High-to-Low Output transitions occur
D input can still change up to here!
• tPLH :Low-to-High Better utilization of time
• tp :max (tPHL, tPLH)  faster design compared to Master-Slave FF, see next

Chapter 3 - Part 1 20
 Flip-Flop Timing Parameters:
S-R Master Slave FF
Requirements: M-S, S-R Flip Flop
 tw : clock
pulse width
(Positive Pulse Triggered)
(for both low & high) Data from master appears on
slave (i.e. FF) output here
 ts : setup time Master is open here
 th : hold time Input transitions allowed
(usually 0 ns)
Outcomes:
 tpd : propagation delay
• tPHL : High-to-Low
• tPLH : Low-to-High Output transitions occur

• tpd : max (tPHL, tPLH) Why tsetup = tw here?

D input should be stable here! We want to avoid things
More time wasted compared to like 1’s catching
Edge-triggered and slower - so S,R should be valid
design compared to the edge and stable before Master
triggered FF Pulse begins (see slide 17)
Chapter 3 - Part 1 21
Standard Symbols for Storage Elements
In a sequential that uses different S S D D Transparent
Type of FFs, Ensure all FFs Latches,
circuit change their outputs No
R R C C
at the same clock edge. Invert I-O isolation
Signal to FF clock if needed SR SR D, Active high Clk D, Active low Clk

 Master-Slave: (a) Clocked Latches

Postponed output S S D D
M-S (Pulse
Triggered) FF
indicators C C M-S D-type I-O Isolation,
O/P affected during width of the R R C C But caution!
given pulse and changed at its end Triggered D
Triggered SR Triggered SR Triggered D
 Edge-Triggered: (b) Master-Slave Flip-Flops

Dynamic
D D One problem with D type FF
indicator is that no D inputs produce
C C
“no change” at output
Solution:
Triggered D Triggered D - Gate out the clock pulses
O/P affected and changed (c) Edge-Triggered Flip-Flops
- Feed back the O/P to the D
on the given one clock edge input when noChapter 3 - Part
change 1 22
is required
 Direct Inputs
 At power up the state of a sequential circuit Bubble = Asynchronous
I/P active low
could be anything! (Direct) S,R  Q

 We usually need to initialize it to a known Q

state before operation begins Synchronous
(clocked) DQ
 This initialization is often done
directly outside of the clocked behavior Q
Edge-
of the circuit, i.e., asynchronously. Triggered
 Direct R and/or S inputs that control the
state of the latches within the flip-flops are
added to FFs for this initialization. Asynchronous
Action- Regardless
 For the example flip-flop shown of clock
• 0 applied to R directly resets the flip-flop to the 0
state regardless of the clock
• 0 applied to S directly sets the flip-flop to the 1
state regardless of the clock Synchronous
Action
Chapter 3 - Part 1 23
 Other Types of Flip-Flops
 We know about the master-slave S-R and D flip-flops
 We will briefly introduce J-K and T flip-flops
• Implementation
• Behavior

Chapter 3 - Part 1 24
 Basic Flip-Flop Descriptors
 For use in analysis: Circuit, given state  Next state?
(FF: present output, inputs  next output?)
• Characteristic table - defines the next state of the flip-flop in
terms of flip-flop inputs and current state
• Characteristic equation - defines the next state of the flip-flop
as a Boolean function of the flip-flop inputs and the current
state
 For use in design: Specified state transitions  Circuit?
(FF: Present, Next states  inputs that give this
state transition?)
• Excitation table - defines the flip-flop inputs that give a
specified present to next output transition
Chapter 3 - Part 1 25
 S-R Flip-Flop
 Characteristic Table
Given FF inputs  Present to Next ?
Analysis

Input-
Driven

 Characteristic Equation

 Excitation Table Given Present to next  Inputs = ?

Design

Output-
Change
Driven

Chapter 3 - Part 1 26
D Flip-Flop

 Characteristic Table
D(t) Q(t + 1) Operation
0 0 Reset
1 1 Set

 Characteristic Equation
Q(t+1) = D(t)
 Excitation Table
Q(t +1) D(t) Operation
0 0 Reset
1 1 Set

Chapter 3 - Part 1 27
J-K Flip-Flop- Improvement on SR
Avoids SR = 11 problem, JK = 11  Toggle, i.e. Q(t+1) = Q(t)
 Characteristic Table
J K Q(t+1) Operation

0 0 Q(t) No change
0 1 0 Reset
1 0 1 Set
1 1 Q(t) Complement
(Toggle)
 Characteristic Equation

 Excitation Table J D
Q(t) Q(t +1) J K Operation K
0 0 0 X No change
C
0 1 1 X Set
Change
1 0 X 1 Reset
1 1 X 0 No Change
Chapter 3 - Part 1 28
T (Toggle) Flip-Flop
D FF with “No change” & “toggling: capabilities

 Characteristic Table
T Q(t+1) Operation
T D
0 Q(t) No change
1 Q(t) Complement (Toggle) C
 Characteristic Equation
Q(t+1) = D(t) = T Å Q(t)
 Excitation Table

Q(t 1) T Operation
+
Q(t) 0 No change
Q(t) 1 Complement

Chapter 3 - Part 1 29
 Sequential Circuit Analysis
 General Model
• Current State (state) at time (t) is stored in an array of flip-flops 
• Next State at (t+1) is a combinational function of State & Inputs
• Outputs at time (t) are a combinational function of State (t) and
(sometimes) Inputs (t)
(t) (t)

O’ (t)
(t)
State (t)

FF Provides isolation between in and out:
State Bits
(one FF per bit)

State (t) is not affected by Q’(t) until…..

…. the next clock pulse comes:

How many states does the Circuit above have?  t becomes t+1,
How many FFs needed for a circuit with 5 states?  O’(t) is moved to FF output, thus
becoming State (t+1)3 - Part 1
Chapter 30
Analysis:
Given a Sequential Circuit determine the way it behaves
External Feedback
 Input: x(t) Inputs
 Output: y(t) x D Q A
 State: (A(t), B(t)) Combinational C Q A
Analysis answers questions: Logic Flip Flops State
 What is the function(s) for
the External Output(s) ? D Q B

(what is the output given a Clock CP C Q

present state and inputs?)
 What is the function for the y
External
Next State? Output(s)
 Synchronous or asynchronous?
(what is the next state given  Mealy or Moore?
a present state and inputs) Chapter 3 - Part 1 31
Analysis Example 1: A Mealy Circuit, Output = F (states, inputs)
Deriving flip flop input equations

 Right at the outset, there

are things we can do:
Derive Boolean
expressions for all
outputs of the
combinational logic (CL)
circuits
 These CL outputs are:
 Inputs to the flip flops + ive Edge
(Will form the next state) Triggered D FFs

DA = AX + BX
DB = AX
 Output(s) to the
outside world Note: Flip flop input equations required
depend on the flip flop type used, e.g. D, SR, etc.
Y = (A+B) X
Chapter 3 - Part 1 32
Determine FF D’s Then transfer FF D’s to FF Q’s
Combinationally on the effective clock edge
here just before clk

1
0
1
0 0
X
0 1 State variables change only at clock edges
X
0

Output in Mealy can change asynchronous

Reset state to all to 0 To clock (with changes in external input X)
(asynchronously?) Chapter 3 - Part 1 33
 Sequential Circuit Analysis
 Given a sequential Circuit
 Objective: Derive outputs & state behavior
(outputs and next state) from (present
states and inputs)
 Two equivalent approaches to represent
the results:
• State table: A truth table-like approach
• State diagram: A graphical, more intuitive way
of representing the state table and expressing
the sequential circuit operation
Chapter 3 - Part 1 34
 State Table Characteristics
 State table – a multiple variable table with the
following four sections:
 CL Inputs:
• Present State – the values of the state variables for each
allowed state (FF outputs)
• External Inputs
 CL Outputs:
• Next-state – the value of the state (FF outputs) at time
(t+1) based on the present state and the inputs.
Determined by FF inputs & FF characteristics
• Outputs – the value of the outputs as a function of the
present state and (sometimes- Mealy) the inputs.
Chapter 3 - Part 1 35
 FF Input Equations: One-Dimensional State Table

# of rows in Table = 2(# of FFs+ # of inputs)

Get from:
x D Q A
- Equations for FF input (CL)
- Then FF Characteristics.
Two State Variables:
Purely
C Q A A, B:  4 states Combinational

D Q B

CP C Q

4 states, 1 input
outputs check
inputs
Chapter 3 - Part 1 36
 Two-Dimensional State Table
a step closer to Sate Diagrams
# of rows in Table = 2(# of FFs)
For Moore type
and I/P conditions considered with O/Ps
O/P = f (state) &
1. FF input Equations (CL) only one column
x D Q A 2. Then FF Characteristics.
Two State Variables A, B
Purely
C Q A  4 states Combinational

(Mealy)

D Q B

CP C Q

4 states. As many Next State Output

rows as states = f (State, I/P) = f (State, I/P)
Chapter 3 - Part 1 37
 Sate Diagram,
Input/output

Mealy Circuits Directed arc

To next state

State Transition
For a given input value,
x D Q A
Corresponding O/P is also marked
State
C Q A

Number of transition combinations exiting a state

= Number of input combinations = 2 here

D Q B

CP C Q

Chapter 3 - Part 1 38
Moore and Mealy Models

 Sequential Circuits or Sequential Machines are

also called Finite State Machines (FSMs). Two
formal models exist:
 Moore Model  Mealy Model
• Named after E.F. Moore. • Named after G. Mealy
• Outputs are a function of
• Outputs are a function of
external inputs AND states
states ONLY • Usually specified on the
• O/Ps are usually specified state transition arcs
on the states (in the circles)
 In contemporary design, models are sometimes
mixed Moore and Mealy

Chapter 3 - Part 1 39
Analysis Example 2: A Moore Circuit
Output = F (States only)
 Right at the outset, there
are thing we can do:
Derive Boolean
expressions for all
outputs of the One + ive Edge
Triggered D FF,
combinational logic (CL) =DA 21 = 2 states
circuits
O/P Determined only by state
 These CL outputs are:
 Inputs to the flip flops
DA = XY A
 Output to the outside
world Output associated with the
State only (inside the circle)
Z=A I/P combinations State, Output
Does not depend on Affect state transitions only
inputs, only on state 
Moore model How many I/P combinations
Chapter 3 - Part 1 40
Emanate from a state?
 Sequential Circuit Design:
The Design Procedure
1. Specification – e.g. Verbal description
2. Formulation – Interpret the specification to obtain a state
diagram and a state table
3. State Assignment - Assign binary codes to symbolic states
4. Flip-Flop Input Equation Determination - Select flip-flop
types and derive flip-flop input equations from next state entries in
CAD Help Available

the state table

5. Output Equation Determination - Derive output equations
from output entries in the state table
6. Optimization - Optimize the combinational logic equations in
4, 5 above, e.g. using K-maps
7. Technology Mapping - Find circuit from equations and map to
a given gate & flip-flop technology
8. Verification - Verify correctness of final design

Chapter 3 - Part 1 41
Specification

 Specification can be through:

• Written description
• Mathematical description
• Hardware description language*
• Tabular description*
• Logic equation description*
• Diagram that describes operation*
 Relation to Formulation
• If a specification is rigorous at the binary
level (marked with * above), then all or part
of formulation would have been completed
Chapter 3 - Part 1 42
Formulation:
Get a State Diagram/Table from the Specifications
 A state is an abstraction of the history of the past applied inputs to the
circuit (including power-up reset or system reset).
• The interpretation of “past inputs” is tied to the synchronous operation of
the circuit. e. g., an input value (other than an asynchronous reset) is
measured only during the setup-hold time interval for an edge-triggered
flip-flop.
 Examples:
• State A may represent the fact that three successive 1’s have occurred at
the input
• State B may represent the fact that a 0 followed by a 1 have occurred as
the most recent past two inputs

0001100011011100
Machine enters State A here
Machine enters State B here
• Machine can only be in one state at any given time

Chapter 3 - Part 1 43
State Initialization
 When a sequential circuit is turned on, the state of the flip
flops is unknown (Q could be 1 or 0)
 Before meaningful operation, we usually bring the circuit to
an initial known state, e.g. by resetting all flip flops to 0’s
 This is often done asynchronously through dedicated direct
S/R inputs to the FFs
 It can also be done synchronously by going through the
clocked FF inputs

Chapter 3 - Part 1 44
Example: Bit Sequence Recognizer: 1101
1. Specifications- Verbal
Verbal Specifications:

X 1101 Z
Input Recognizer Output

 Detect the occurrence of bit sequence 1101 whenever it occurs

on input X and indicate this detection by raising an output Z high
 i.e. normally output Z = 0 until sequence 1101 occurs
i.e. until input X = 1 and
110 was the last sub-sequence received
i.e. system was in the state ‘110 received’
 Is this a Mealy or a Moore model?

Chapter 3 - Part 1 45
Example: Bit Sequence Recognizer: 1101
2. Formulation: State Diagram Strategy
 Begin in an initial state in which NONE of the
initial portion of the sequence has occurred
(typically “reset” state)
 Add a state which recognizes that the first symbol
in the target sequence (1) has occurred
 Add states that recognize each successive
symbol occurring
 The final state represents:
• Occurrence of the required input sequence (Moore)
• Occurrence of the required input sequence less the last input (Mealy)
 Add state transition arcs which specify what
happens when a symbol not contributing to the
target sequence has occurred
Chapter 3 - Part 1 46
 Recognizer for Sequence 1101
Has sub-sequences: 1, 11, 110
1/0 1/0 0/0
A B C D
Initial or
Input/output = X/Z
No Progress State 1/1 When does Z become 1?

 The states have the following abstract meanings:

• A: No proper sub-sequence of the sequence has occurred.
Could be also the initialization (Reset) state
• B: Remembers the occurrence of sub-sequence ‘1’
• C: Remembers the occurrence of sub-sequence ‘11’
• D: Remembers the occurrence of sub-sequence ‘110’
• The 1/1 arc from D means full sequence is detected & Z = 1.
But why does it go to B? Since this ‘1’ could be the first 1 in
a new sequence and thus needs to be remembered as1 ‘1’!47
Chapter 3 - Part
 Is this the complete state diagram?
What is missing? 1101
 At each state, the input X could have any of two values, so 2 arcs
must emanate from each state (X = 0 and X = 1)
 Also A is not entered!
1/0 1/0 0/0
A B C D
Initial or
No Progress State
Transitions that help build 1/1
the target sequence:
Go to B (1) or C (11) 0/0 1/0 11101
111
Transitions that
do not help build 1/0 1/0 0/0
A B C11 D
the required 1 110

sequence:
go to A A 0 after only one 1
0/0 1/1 1101101
is not a help! 1101
0/0
Chapter
Each state must have3 - 2Part
arcs1 exiting
48
 “Symbolic” State Table (Mealy Model)
 From the State Diagram, we can fill in the 2-D State Table
 There are 4 states, one 0/0 1/0
input, and one output.
1/0 1/0 0/0
 Two dimensional table A B C D
with four rows, one for
0/0 1/1
each current state
0/0 O/P depends on I/P,
 Mealy

Present Next State Output

From “symbolic” state table State x=0 x=1 x=0 x=1
A A B 0 0
To binary State Table: B A C 0 0
What is needed? C D C 0 0
 State Assignment Issues D A B 0 1

Chapter 3 - Part 1 49
 Formulation Example:
State Diagram (Moore Model)
 With the Moore model, output is associated with only a state
not a state and an input as seen with the Mealy model
 This means we need a fifth state (remembers the full target
sequence (1101)) and produces the required Z = 1 output
0 1 0/0 1/0
O/P tied to state

1 1 0 1/0 1/0 0/0

A/0 B/0 C/0 D/0 A B C D

0 1 0/0 1/1
1
0 Moore 0/0 Mealy
E/1
New State
Produces the Z O/P
0

Now 5 states needed Note: O/P does not

An extra FF! Chapter
depend on3I/P
- Part
(only11 column)
50
 3. State Assignment: From abstract symbols
to binary bit representation of states
Need to represent m states  ? FFs
 Each of the m symbolic states must be assigned a
unique binary code
 Minimum number of state bits (state variables) (FFs)
required is n, such that 2n ≥ m

i.e.n ≥ log2 m

where x is the smallest integer ≥ x

 If 2n > m, this leaves (2n – m) unused states
 Utilize them as don’t care conditions to simplify CL design
 But may need caution: e.g. what if the circuit enters an
unused state by mistake
 Also which code is given to which state?  different CL
implementations  may influence optimization, e.g.
(with 2 FFs) State A is assigned 00 or 01 or 10 or 11?
Chapter 3 - Part 1 51
 4, 5, 6: Determination and Optimization: The Mealy Model
4 states (A, B, C, D)  2 FFs, No unused states
Let A = 00 (to suit being a Reset state), B = 01, C = 11, D = 10
Symbolic State Table Binary State Table
(t) (t+1) (t)
(The 2 FFs)
AB AB

Assign
States

For optimization of FF input equations we express A(t+1), B(t+1), Z(t) in terms of

A(t), B(t) and X(t) (using one dimensional state table)

= DA(t) = DB(t)

Using D flip flops: Optimized

Use standard order to D (t) = A (t+1) Results
A
Simplify entering
DB (t) = B (t+1)
Data into the K-maps Chapter 3 - Part 1 52
Sequential Circuit
SOP: AND-OR

A
D

C
R
Z

B
X D

Clock C
R
Reset
Asynchronous Reset
To Initial State A (AB = 00)
Chapter 3 - Part 1 53
 7. Technology-Mapped Circuit –
Final Result
 Design Library SOP using NANDs only

contains:
A
• D Flip-flops D
with Reset
(Active High) OR-AND
C
R
• NAND gates Z
with up to 4
inputs and X B AND
D
inverters
Clock C
R
Reset

Chapter 3 - Part 1 54
 8. Verification
Manual or Using CAD Simulation 1/0
0/0
1/0 1/0 0/0
A B C D

A Reset State 0/0

B 1/1
C
D 0/0
+ive
Edges
Asynch.
1
1 1 1 0 1
0 0

0 0

1 0

0 1
1 1

1 1

1 0
Async. Reset
(A) (B) (C) (C) (D) (B)

Changes directly
with input (Mealy)
Chapter 3 - Part 1 55
Sequential Circuits
Analysis Versus Design
0/0 1/0

A 1/0 B 1/0 C
0/0
D
0/0 1/1
0/0

Analysis
1-D
Design 2-D
• For Analysis of a given circuit:
Given circuit, get its behavior [state table (state diagram)]:
{Present state, inputs}  Next state?
Flip Flop Consideration: (inputs outputs?)
 We use FF Characteristic tables/equations
• For Design to achieve a specified circuit performance
Given desired behavior [(state diagram (State table)], get circuit
(behavior: Present to next changes  FF Inputs? CL circuit)
Flip Flop Considerations: (O/P behavior  inputs to give this behavior?)
 We use FF Excitation tables Chapter 3 - Part 1 56
Another Analysis Example:
Circuit  Behavior in a State Diagram form

2 D-type Flip Flops

+ive edge triggered

 22 = 4 states
AB = 00, 01, 10, 11
1 input x
1 output y

State Variables are?

Mealy or Moore?
Chapter 3 - Part 1 57
 1-D State Table Comb  Seq Link

Analysis Example, Contd. (Ds)

Lower

2-D State Table (closer to state diagram)

Chapter 3 - Part 1 58
 Analysis Example, Contd.

2-D Truth Table (closer to state diagram)

Input/Output

Chapter 3 - Part 1 59
 Another Design Example
Behavior in a State Diagram form  Circuit
4 states
00, 01, 10, 11
2 flip-flops A,B
1 input, x
1 output, y
Mealy or Moore? Seq  Comb Link
Inputs Outputs

1-D (Ds)
State Table

2-D State Table

Chapter 3 - Part 1 60
 Design Example, Contd.
Inputs Outputs Straight forward Combinational Logic
design problem:

Index 3 inputs: {A, B, x}

DA DB
3 Outputs: {DA, DB, y}
0
1
The D type flip flop data inputs,
2
Will be the next state on the next
3
+ ive clock edge
4
5
6
7

Chapter 3 - Part 1 61
 Design Example, Contd.

State
Input

ChapterOutput
3 - Part 1 62
 Unit 11: Sequential Circuits
Chapters 5 & 6: Sequential Circuits
1. Sequential Circuit Definitions, Types of Latches: SR,
Clocked SR, and D Latches
2. Flip-Flops: SR, D, JK, and T Flip-Flops
3. Flip-Flop Timing Parameters: Setup, hold,
propagation, clocking
4. Flip-Flops: Characteristic and Excitation Tables
5. Analysis of Sequential Circuits with D flip-flops:
Deriving the input equations, state table, and state
diagram. Timing
6. Design of Sequential Circuits with D flip-flops:
Determining the state diagrams and tables, State
assignment, Combinational Logic
Chapter 3 - Part 1 63