Pertemuan 3
Pertemuan 3
William Stallings
Computer Organization
and Architecture
10th Edition
Hardwired program
The result of the process of connecting the various components in the
desired configuration
MAR
Processor- Processor-
memory I/O
Data
Control
processing
Classes of Interrupts
An I/O
module is
allowed to
exchange
Processor
Processor data directly
reads an Processor Processor
reads data with memory
instruction writes a unit sends data to
from an I/O without
or a unit of of data to the I/O
device via an going
data from memory device
I/O module through the
memory
processor
using direct
memory
access
Inter
time period their signals will overlap
and become garbled
conn
Typically consists of multiple
communication lines Computer systems contain a
ectio
• Each line is capable of transmitting
signals representing binary 1 and
binary 0
number of different buses that
provide pathways between
components at various levels of
n
the computer system hierarchy
System bus
• A bus that connects major computer
components (processor, memory, I/O)
The most common computer
interconnection structures are
based on the use of one or more
system buses
Principal reason for change was At higher and higher data rates
the electrical constraints it becomes increasingly difficult
encountered with increasing the to perform the synchronization
frequency of wide synchronous and arbitration functions in a
buses timely fashion
Memory I/O
The memory space includes This address space is used for
system main memory and PCIe legacy PCI devices, with
I/O devices reserved address ranges used to
Certain ranges of memory address legacy I/O devices
addresses map into I/O devices
Configuration Message
This address space enables the This address space is for control
TL to read/write configuration signals related to interrupts,
registers associated with I/O error handling, and power
devices management