COMPUTER ORGANIZATION AND ARCHITECTURE

MOD ULE-2 PART ON E

- LIPSA SUBHADARSHINI

Subject Code- BC 2007

No. of Credits- 4
BCA 3rd Semester

Kalinga Institute of Industrial Technology (Deemed to be University), Bhubaneswar 07/01/2023 1

 R E G I S T E R T R A N S F E R A N D M I C R O - O P E R AT I O N S

• Register Transfer Language

• Register Transfer
• Bus and Memory Transfers
• Arithmetic Micro-operations
• Logic Micro-operations
• Shift Micro operations
• Basic Computer Organization and Design
• Computer Registers
• Bus system
• Instruction set
• Timing and Control
• Instruction Cycle
• Memory reference
• Input- Output and Interrupt

Kalinga Institute of Industrial Technology (Deemed to be University), Bhubaneswar 07/01/2023 2

 R E G I S T E R T R A N S F E R L A N G U A G E

• A digital system is an interconnection of digital hardware modules that accomplish a specific information processing task.
• Digital modules are defined by the registers they contain and the operations that are performed on the data stored in them.
The operations executed on data stored in registers are called microoperations.
• Microoperation- It’s an elementary operation performed on information stored in one or more registers. The result of the
operation may replace the previous binary information or store it in another register
• Ex: shift, count, clear, load etc
• The internal hardware organization of a digital computer is best defined by specifying:
• The set of register it contains and their function
• The sequence of microoperations performed on the binary information stored in the registers
• The control that initiates the sequence of microoperations
• The symbolic notation used to describe the microoperation transfers among registers is called a register transfer language.
• The term “Register Transfer” implies the availability of hardware logic circuits that can perform a stated micro operation
and transfer the result to the same or another register.

Kalinga Institute of Industrial Technology (Deemed to be University), Bhubaneswar 07/01/2023 3

 R E G I S T E R T R A N S F E R L A N G U A G E

• A register transfer language is a system for expressing in symbolic form the microoperation sequences among the
registers of a digital module.
• Application:
• Convenient tool for describing the internal organization of a computer in concise and precise manner
• Can be used to facilitate the design process of digital systems

Kalinga Institute of Industrial Technology (Deemed to be University), Bhubaneswar 07/01/2023 4

 R E G I S T E R T R A N S F E R

• Examples of Computer register

• MAR- Memory address register
• PC- Program Counter register
• IR- Instruction Register
• R1- Processor Register

Kalinga Institute of Industrial Technology (Deemed to be University), Bhubaneswar 07/01/2023 5

 R E G I S T E R T R A N S F E R

• The data transfer from one register to another is named in representative design using a replacement operator. The statement is
R2←R1
• It indicates a transfer of the content of register R1 into register R2. It labelled a replacement of the content of R2 by the content of
R1. The content of the source register R1 does not shift after the transfer.
• A statement that specifies a register transfer involves that circuits are accessible from the outputs of the source register to the inputs
of the destination register and that the destination register has a corresponding load efficiency.
• We need the transfer to appear only under a fixed control condition. This can be displayed using an if-then statement.
• If (P = 1) then (R2 ← R1) where P is a control signal created in the control area. A control function is a Boolean variable that is
similar to 1 or 0. The control function is contained in the statement as follows, P: R2 ← R1
• The control condition is terminated with a colon. It represents the specification that the transfer operation is implemented by the
hardware only if P = 1. Each statement written in a register transfer notation indicates a hardware structure for executing the transfer.
• The diagram demonstrates the block diagram that shows the transfer from R1 to R2. The n outputs of register R1 are linked to the n
inputs of register R2. The letter n can denote any number of bits for the register. It will be restored by an actual number when the
duration of the register is established.
• Register R2 has a load input that is activated by the control variable P. It is considered that the control variable is synchronized with
the equivalent clock like the one used to the register.

Kalinga Institute of Industrial Technology (Deemed to be University), Bhubaneswar 07/01/2023 6

 R E G I S T E R T R A N S F E R

Transfer of R1 to R2 when P=1

Kalinga Institute of Industrial Technology (Deemed to be University), Bhubaneswar 07/01/2023 7

 R E G I S T E R T R A N S F E R

Kalinga Institute of Industrial Technology (Deemed to be University), Bhubaneswar 07/01/2023 8

 R E G I S T E R T R A N S F E R

Simultaneous operation

Kalinga Institute of Industrial Technology (Deemed to be University), Bhubaneswar 07/01/2023 9

 B U S A N D M E M O RY T R A N S F E R S

Bus system for four Registers

Kalinga Institute of Industrial Technology (Deemed to be University), Bhubaneswar 07/01/2023 10

 B U S A N D M E M O RY T R A N S F E R S

• The bus system will multiplex k registers of n bits each to produce an ‘n’ line common bus
• No. of Multiplexers needed is equal to “n” which is equal to the no of bits of the registers.
• Bus Line with three states buffers

Kalinga Institute of Industrial Technology (Deemed to be University), Bhubaneswar 07/01/2023 11

 B U S A N D M E M O RY T R A N S F E R S

Bus Line of Three State Buffers

Kalinga Institute of Industrial Technology (Deemed to be University), Bhubaneswar 07/01/2023 12

 M E M O RY T R A N S F E R

• Most of the standard notations used for specifying operations on memory transfer are stated below.
• The transfer of information from a memory unit to the user end is called a Read operation.
• The transfer of new information to be stored in the memory is called a Write operation.
• A memory word is designated by the letter M.
• We must specify the address of memory word while writing the memory transfer operations.
• The address register is designated by AR and the data register by DR.
• Thus, a read operation can be stated as: Read:  DR ← M [AR]  
• The Read statement causes a transfer of information into the data register (DR) from the memory word (M) selected by the address
register (AR).
• And the corresponding write operation can be stated as: Write: M [AR] ← R1
• The Write statement causes a transfer of information from register R1 into the memory word (M) selected by address register (AR).

Kalinga Institute of Industrial Technology (Deemed to be University), Bhubaneswar 07/01/2023 13

 A R I T H M E T I C M I C R O O P E R AT I O N S

The Microoperations most often encountered in digital computers are classified into four categories:
• Register Transfer Microoperation- transfers binary information from one register to another
• Arithmetic Microoperation- performs arithmetic operations on numeric data stored in the register
• Logic Microoperation- performs bit manipulation operations on non numeric data stored in the register
• Shift Microoperation- performs shift operation on the data stored in the register
The basic Arithmetic Micro-operations are classified in the following categories:
1. Addition
2. Subtraction
3. Increment
4. Decrement
5. Shift
Some additional Arithmetic Micro-operations are classified as:
6. Add with carry
7. Subtract with borrow
8. Transfer/Load, etc.
Kalinga Institute of Industrial Technology (Deemed to be University), Bhubaneswar 07/01/2023 14
 A R I T H M E T I C M I C R O O P E R AT I O N S

The following table shows the symbolic representation of various Arithmetic Micro-operations.

Symbolic Representation Description

R3 ← R1 + R2 The contents of R1 plus R2 are transferred to R3.

R3 ← R1 - R2 The contents of R1 minus R2 are transferred to R3.

R2 ← R2' Complement the contents of R2 (1's complement)

R2 ← R2' + 1 2's complement the contents of R2 (negate)

R3 ← R1 + R2' + 1 R1 plus the 2's complement of R2 (subtraction)

R1 ← R1 + 1 Increment the contents of R1 by one

R1 ← R1 - 1 Decrement the contents of R1 by one

Kalinga Institute of Industrial Technology (Deemed to be University), Bhubaneswar 07/01/2023 15

 AR IT HME T I C M IC R O O P E R AT IO N S

Binary Adder
• The Add micro-operation requires registers that can hold the data and the digital components that can perform the
arithmetic addition.
• A Binary Adder is a digital circuit that performs the arithmetic sum of two binary numbers provided with any
length.
• A Binary Adder is constructed using full-adder circuits connected in series, with the output carry from one full-
adder connected to the input carry of the next full-adder.
• The following block diagram shows the interconnections of four full-adder circuits to provide a 4-bit binary adder.

Kalinga Institute of Industrial Technology (Deemed to be University), Bhubaneswar 07/01/2023 16

 A R I T H M E T I C M I C R O O P E R AT I O N S

Binary Adder
• The augend bits (A) and the addend bits (B) are designated by subscript numbers from right to left, with subscript
'0' denoting the low-order bit.
• The carry inputs starts from C0 to C3 connected in a chain through the full-adders. C4 is the resultant output carry
generated by the last full-adder circuit.
• The output carry from each full-adder is connected to the input carry of the next-high-order full-adder.
• The sum outputs (S0 to S3) generates the required arithmetic sum of augend and addend bits.
• The n data bits for the A and B inputs come from different source registers. For instance, data bits for A input
comes from source register R1 and data bits for B input comes from source register R2.
• The arithmetic sum of the data inputs of A and B can be transferred to a third register or to one of the source
registers (R1 or R2).

Kalinga Institute of Industrial Technology (Deemed to be University), Bhubaneswar 07/01/2023 17

 A R I T H M E T I C M I C R O O P E R AT I O N S

Binary Adder-Subtractor
• The Subtraction micro-operation can be done easily by taking the 2's compliment of addend bits and adding it to
the augend bits.
• The Arithmetic micro-operations like addition and subtraction can be combined into one common circuit by
including an exclusive-OR gate with each full adder.
• The block diagram for a 4-bit adder-subtractor circuit can be represented as:

Kalinga Institute of Industrial Technology (Deemed to be University), Bhubaneswar 07/01/2023 18

 A R I T H M E T I C M I C R O O P E R AT I O N S

Binary Adder-Subtractor
• When the mode input (M) is at a low logic, i.e. '0', the circuit act as an adder and when the mode input is at a high
logic, i.e. '1', the circuit act as a subtractor.
• The exclusive-OR gate connected in series receives input M and one of the inputs B.
• When M is at a low logic, we have B⊕ 0 = B.
• The full-adders receive the value of B, the input carry is 0, and the circuit performs A plus B.
• When M is at a high logic, we have B⊕ 1 = B' and C0 = 1.
• The B inputs are complemented, and a 1 is added through the input carry. The circuit performs the operation A plus
the 2's complement of B.

Kalinga Institute of Industrial Technology (Deemed to be University), Bhubaneswar 07/01/2023 19

 A R I T H M E T I C M I C R O O P E R AT I O N S

Binary Incrementor
• The increment micro-operation adds one binary value to the value of binary variables stored in a register. For
instance, a 4-bit register has a binary value 0110, when incremented by one the value becomes 0111.
• The increment micro-operation is best implemented by a 4-bit combinational circuit incrementor. A 4-bit
combinational circuit incrementor can be represented by the following block diagram.

Kalinga Institute of Industrial Technology (Deemed to be University), Bhubaneswar 07/01/2023 20

 A R I T H M E T I C M I C R O O P E R AT I O N S

Binary Incrementor
• A logic-1 is applied to one of the inputs of least significant half-adder, and the other input is connected to the least
significant bit of the number to be incremented.
• The output carry from one half-adder is connected to one of the inputs of the next-higher-order half-adder.
• The binary incrementer circuit receives the four bits from A0 through A3, adds one to it, and generates the
incremented output in S0 through S3.
• The output carry C4 will be 1 only after incrementing binary 1111.

Kalinga Institute of Industrial Technology (Deemed to be University), Bhubaneswar 07/01/2023 21

 A R I T H M E T I C M I C R O O P E R AT I O N S

4 Bit Arithmetic Circuit

• Arithmetic circuits can perform seven different arithmetic operations using a single composite circuit. 
It uses a full adder (FA) to perform these operations. A multiplexer (MUX) is used to provide different inputs to the circuit in order
to obtain different arithmetic operations as outputs.
• 4-bit Arithmetic Circuit : 
Consider the following 4-bit Arithmetic circuit with inputs A and B. It can perform seven different arithmetic operations by varying
the inputs of the multiplexer and the carry (C0).
• Hence, the different operations for the inputs A and B are –
1. A + B (adder)
2. A + B + 1 (add with carry)
3. A + B’ (Subtract with borrow)
4. A – B (subtracter)
5. A (Transfer)
6. A + 1 (incrementer)
7. A – 1 (decrementer)

Kalinga Institute of Industrial Technology (Deemed to be University), Bhubaneswar 07/01/2023 22

 A R I T H M E T I C M I C R O O P E R AT I O N S

Kalinga Institute of Industrial Technology (Deemed to be University), Bhubaneswar 07/01/2023 23

 L O G I C M I C R O O P E R AT I O N S

• Logic operations are binary micro-operations implemented on the bits saved in the registers. These operations
treated each bit independently and create them as binary variables.
• For example, the exclusive-OR micro-operation with the contents of two registers R1 and R2 is denoted by the
statement
• P: R1←R1⊕R2
• It determines a logic micro-operation to be implemented on the single bits of the registers supported that the control
variable P = 1. Consider that each register has four bits. Let the content of R1 be 1010 and the content of R2 be
1100.
• The exclusive-OR micro-operation stated above represent the following logic computation −
1010 Content of R1
1100 Content of R2
0110 Content of R1 after P = 1
• The content of R1, after the implementation of the micro-operation, is similar to the bit-by-bit exclusive-OR
operation on pairs of bits in R2 and previous values of R1.

Kalinga Institute of Industrial Technology (Deemed to be University), Bhubaneswar 07/01/2023 24

 L O G I C M I C R O O P E R AT I O N S

Special Symbols
• Special symbols will be approved for the logic micro-operations OR, AND, and complement, to categorize them from
the matching symbols that can define Boolean functions. The symbol V can indicate an OR micro-operation and the
symbol can indicate an AND micro-operation.
• The complement micro-operation is similar to the 1's complement and supports a bar on the highest of the symbol that
indicates the registered name. There are various symbols, and it will be applicable to differentiate between a logic micro-
operation and a control (or Boolean) function.
• There is another sense for supporting two sets of symbols can that recognize the symbol +, when can symbolize
arithmetic plus, from a logic OR operation. Although the + symbol has two meanings, it will be available to determine
between them by observing where the symbol appears.
• When the symbol + appears in a micro-operation, it will indicate an arithmetic plus. When it appears in a control (or
Boolean) function, it will indicate an OR operation. We cannot use it to symbolize an OR micro-operation.
• For example, in the statement
• P+Q: R1←R2+R3, R4←R5 V R6
• The + between P and Q is an OR operation between two binary variables of a control function. The + between R2 and
R3 determines an add micro-operation. The OR micro-operation is named by the symbol V between registers R5 and R6.

Kalinga Institute of Industrial Technology (Deemed to be University), Bhubaneswar 07/01/2023 25

 L O G I C M I C R O O P E R AT I O N S

List of Logic Microoperations:

• There are 16 different logic operations that can be performed with two binary variables.
• They can be determined from all possible truth tables obtained with two binary variables as shown in Table below.
• In this table, each of the 16 columns F0 through F15 represents a truth table of one possible Boolean function for the two
variables x and y.

Kalinga Institute of Industrial Technology (Deemed to be University), Bhubaneswar 07/01/2023 26

 L O G I C M I C R O O P E R AT I O N S

Note that the functions are determined from the 16 binary

combinations that can be assigned to F. The 16 Boolean
functions of two variables x and y are expressed in algebraic
form in the first column of Table below.

The 16 logic microoperations are derived from these

functions by replacing variable x by the binary content of
register A and variable y by the binary content of register B.

It is important to realize that the Boolean functions listed

in the first column of Table below represent a relationship
between two binary variables x and y.

The logic microoperations listed in the second column

represent a relationship between the binary content of two
registers A and B.

Each bit of the register is treated as a binary variable and

the microoperation is performed on the string of bits stored
in the registers.

Kalinga Institute of Industrial Technology (Deemed to be University), Bhubaneswar 07/01/2023 27

 L O G I C M I C R O O P E R AT I O N S

Hardware Implementation
• The hardware implementation of logic microoperations requires that logic gates be inserted for each bit or pair of bits
in the registers to perform the required logic function.
• Although there are 16 logic microoperations, most computers use only four-AND, OR, XOR (exclusive-OR), and
complement from which all others can be derived.
• Figure below shows one stage of a circuit that generates the four basic logic microoperations .
• It consists of four gates and a multiplexer. Each of the four logic operations is generated through a gate that performs
the required logic.
• The outputs of the gates are applied to the data inputs of the multiplexer. The two selection inputs S 1 and S0 choose one
of the data inputs of the multiplexer and direct its value to the output.
• The diagram shows one typical stage with subscript i. For a logic circuit with n bits, the diagram must be repeated n
times for i = 0, 1, 2, ... , n - 1.
The selection variables are applied to all stages. The function table in Fig. below lists the logic microoperations
obtained for each combination of the selection variables.

Kalinga Institute of Industrial Technology (Deemed to be University), Bhubaneswar 07/01/2023 28

 L O G I C M I C R O O P E R AT I O N S

Kalinga Institute of Industrial Technology (Deemed to be University), Bhubaneswar 07/01/2023 29

 L O G I C M I C R O O P E R AT I O N S

Applications
• Logic microoperations are very useful for manipulating individual bits or a portion of a word stored in a register.
• They can be used to change bit values, delete a group of bits, or insert new bit values into a register. The following examples show how the bits of one
register (designated by A) are manipulated by logic microoperations as a function of the bits of another register (designated by B).
• In a typical application, register A is a processor register and the bits of register B constitute a logic operand extracted from memory and placed in
register B.
• The selective-set operation sets to 1 the bits in register A where there are corresponding 1's in register B. It does not affect bit positions that have 0's in B.
• The following numerical example clarifies this operation:

• The two leftmost bits of B are 1' s, so the corresponding bits of A are set to 1.
•
One of these two bits was already set and the other has been changed from 0 to 1. The two bits of A with corresponding 0' s in B remain unchanged. The
example above serves as a truth table since it has all four possible combinations of two binary variables.
•
From the truth table we note that the bits of A after the operation are obtained from the logic-OR operation of bits in B and previous values of A.
Therefore, the OR microoperation can be used to selectively set bits of a register.

Kalinga Institute of Industrial Technology (Deemed to be University), Bhubaneswar 07/01/2023 30

 L O G I C M I C R O O P E R AT I O N S

The selective-complement operation complements bits in A where there are selective-clear corresponding 1's in B. It does not affect bit
positions that have 0's in B. For example:

Again the two leftmost bits of B are 1's, so the corresponding bits of A are complemented.
This example again can serve as a truth table from which one can deduce that the selective-complement operation is just an exclusive-OR
microoperation.
Therefore, the exclusive-OR microoperation can be used to selectively complement bits of a register.
The selective-clear operation clears to 0 the bits in A only where there are corresponding 1's in B. For example:

Again the two leftmost bits of B are 1' s, so the corresponding bits of A are cleared to 0.
One can deduce that the Boolean operation performed on the individual bits is AB'. The corresponding logic microoperation is A ← A ∧ B

Kalinga Institute of Industrial Technology (Deemed to be University), Bhubaneswar 07/01/2023 31

 L O G I C M I C R O O P E R AT I O N S

The mask operation is similar to the selective-clear operation except that the bits of A are cleared only where there are corresponding 0's in B. The mask
operation is an AND micro operation as seen from the following numerical example:

The two rightmost bits of A are cleared because the corresponding bits of B are 0' s. The two leftmost bits are left unchanged because the corresponding
bits of B are 1's.
The mask operation is more convenient to use than the selective clear operation because most computers provide an AND instruction, and few provide an
instruction that executes the microoperation for selective-clear.
The insert operation inserts a new value into a group of bits. This is done by first masking the bits and then ORing them with the required value. For
example, suppose that an A register contains eight bits, 0110 1010.
To replace the four leftmost bits by the value 1001 we first mask the four unwanted bits:

and then insert the new value:

The mask operation is an AND microoperation and the insert operation is an OR microoperation
Kalinga Institute of Industrial Technology (Deemed to be University), Bhubaneswar 07/01/2023 32
 S H I F T M I C R O O P E R AT I O N S

Shift micro-operations are those micro-operations that are used for serial transfer of information. These are also used in conjunction
with arithmetic micro-operation, logic micro-operation, and other data-processing operations.
There are three types of shifts micro-operations:
1. Logical :
It transfers the 0 zero through the serial input. We use the symbols shl for logical shift-left and shr for shift-right.
• Logical Shift Left –
In this shift one position moves each bit to the left one by one. The Empty least significant bit (LSB) is filled with zero (i.e, the
serial input), and the most significant bit (MSB) is rejected.

Kalinga Institute of Industrial Technology (Deemed to be University), Bhubaneswar 07/01/2023 33

 S H I F T M I C R O O P E R AT I O N S

• Right Logical Shift – In this one position moves each bit to the right one by one and the least significant bit(LSB) is rejected and the empty MSB
is filled with zero.

2. Arithmetic :
This micro-operation shifts a signed binary number to the left or to the right position. In an arithmetic shift-left, it multiplies a signed binary number
by 2 and In an arithmetic shift-right, it divides the number by 2.
• Left Arithmetic Shift –
In this one position moves each bit to the left one by one. The empty least significant bit (LSB) is filled with zero and the most significant bit
(MSB) is rejected. Same as the Left Logical Shift.

Kalinga Institute of Industrial Technology (Deemed to be University), Bhubaneswar 07/01/2023 34

 S H I F T M I C R O O P E R AT I O N S

Right Arithmetic Shift –

In this one position moves each bit to the right one by one and the least significant bit is rejected and the empty MSB is filled with the value of the
previous MSB.

3. Circular :
The circular shift circulates the bits in the sequence of the register around the both ends without any loss of information.
• Left Circular Shift – • Right Circular shift-

Kalinga Institute of Industrial Technology (Deemed to be University), Bhubaneswar 07/01/2023 35

 S H I F T M I C R O O P E R AT I O N S

Kalinga Institute of Industrial Technology (Deemed to be University), Bhubaneswar 07/01/2023 36

 S H I F T M I C R O O P E R AT I O N S

Hardware Implementation
• A possible choice for a shift unit would be a bidirectional shift register with parallel load
• Information can be transferred to the register in parallel and then shifted to the right or left.
• In this type of configuration, a clock pulse is needed for loading the data into the register, and another pulse is needed to initiate the
shift.
• In a processor unit with many registers it is more efficient to implement the shift operation with a combinational circuit.
• In this way the content of a register that has to be shifted is first placed onto a common bus whose output is connected to the
combinational shifter, and the shifted number is then loaded back into the register.
• This requires only one clock pulse for loading the shifted value into the register.
• A combinational circuit shifter can be constructed with multiplexers as shown in Fig. below. The 4-bit shifter has four data inputs,
A0 through A3, and four data outputs, H0 through H3.
• There are two serial inputs, one for shift left (IL) and the other for shift right (IL). When the selection input S = 0, the input data are
shifted right (down in the diagram). When S = 1, the input data are shifted left (up in the diagram). The function table in Fig. above
shows which input goes to each output after the shift.
• A shifter with n data inputs and outputs requires n multiplexers. The two serial inputs can be controlled by another multiplexer to
provide the three possible types of shifts.

Kalinga Institute of Industrial Technology (Deemed to be University), Bhubaneswar 07/01/2023 37

 S H I F T M I C R O O P E R AT I O N S

Kalinga Institute of Industrial Technology (Deemed to be University), Bhubaneswar 07/01/2023 38