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Basic Hardware Issues

The document discusses basic hardware concepts related to CPU and memory access. It states that the CPU can only directly access main memory and processor registers. For data to be used by instructions, it must be moved into these direct-access storage areas if it is not already there. It also describes caches that help speed up memory access by storing frequently used data and instructions closer to the CPU. The document then discusses memory protection and address translation techniques used in operating systems.

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Rakesh Patil
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0% found this document useful (0 votes)
36 views

Basic Hardware Issues

The document discusses basic hardware concepts related to CPU and memory access. It states that the CPU can only directly access main memory and processor registers. For data to be used by instructions, it must be moved into these direct-access storage areas if it is not already there. It also describes caches that help speed up memory access by storing frequently used data and instructions closer to the CPU. The document then discusses memory protection and address translation techniques used in operating systems.

Uploaded by

Rakesh Patil
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PPTX, PDF, TXT or read online on Scribd
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Basic Hardware Issues

Main memory and the registers built into the processor itself are
the only general-purpose storage that the CPU can access directly.
There are machine instructions that take memory addresses as
arguments, but none that take disk addresses.
Therefore, any instructions in execution, and any data being used
by the instructions, must be in one of these direct-access storage
devices. If the data are not in memory, they must be moved there
before the CPU can operate on them. Registers that are built into
the CPU are generally accessible within one cycle of the CPU clock.
Basic Hardware Issues

CPUs can decode instructions and perform simple operations on


register contents at the rate of one or more operations per clock
tick. The same cannot be said of main memory, which is accessed
via a transaction on the memory bus.
The remedy is to add fast memory between the CPU and main
memory, typically on the CPU chip for fast access. To manage a
cache built into the CPU, the hardware automatically speeds up
memory access without any operating-system control.
Basic Hardware Issues
On multiuser systems, we
must additionally protect
user processes from one
another. This protection
must be provided by the
hardware because the
operating system doesn’t
usually intervene
between the CPU and its
memory accesses
Basic Hardware Issues

For example, if the base register holds 300040 and the limit
register is 120900, then the program can legally access all
addresses from 300040 through 420939 (inclusive). Protection of
memory space is accomplished by having the CPU hardware
compare every address generated in user mode with the registers.
Any attempt by a program executing in user mode to access
operating-system memory or other users’ memory results in a trap
to the operating system, which treats the attempt as a fatal error.
The base and limit registers can be loaded only by the operating
system, which uses a special privileged instruction.
Address Binding
A program resides on a disk as a binary executable file. To be
executed, the program must be brought into memory and placed
within a process. Depending on the memory management in use,
the process may be moved between disk and memory during its
execution. The processes on the disk that are waiting to be brought
into memory for execution form the input queue.
The normal single-tasking procedure is to select one of the
processes in the input queue and to load that process into
memory. As the process is executed, it accesses instructions and
data from memory. Eventually, the process terminates, and its
memory space is declared available.
Address Binding
Addresses may be represented in different ways during these
steps. Addresses in the source program are generally symbolic
(such as the variable count). A compiler typically binds these
symbolic addresses to relocatable addresses (such as “14 bytes
from the beginning of this module”). The linkage editor or loader
in turn binds the relocatable addresses to absolute addresses (such
as 74014). Each binding is a mapping from one address space to
another.
Address Binding
Compile time: If you know at compile time where the process will
reside in memory, then absolute code can be generated. For
example, if you know that a user process will reside starting at
location R, then the generated compiler code will start at that
location and extend up from there.
Load time: If it is not known at compile time where the process will
reside in memory, then the compiler must generate relocatable
code.
Execution time: If the process can be moved during its execution
from one memory segment to another, then binding must be
delayed until run time. Special hardware must be available for this
scheme to work, as will be discussed Most general-purpose
operating systems use this method
Address Binding
Multistep processing of a user program.
Logical Vs Physical Address Space
An address generated by the CPU is commonly referred to as a
logical address.
Address seen by the memory unit—that is, the one loaded into the
memory-address register of the memory—is commonly referred to
as a physical address.
The compile-time and load-time address-binding methods
generate identical logical and physical addresses.
Logical Vs Physical Address Space

If the base is at 14000, then an attempt by the user to address location 0


is dynamically relocated to location 14000; an access to location 346 is
mapped to location 14346. The user program never sees the real physical
addresses. The program can create a pointer to location 346, store it in
memory, manipulate it, and comp]are it with other addresses—all as the
number 346.
Logical Vs Physical Address Space
An address generated by the CPU is commonly referred to as a
logical address.
Address seen by the memory unit—that is, the one loaded into the
memory-address register of the memory—is commonly referred to
as a physical address.
The compile-time and load-time address-binding methods generate
identical logical and physical addresses.
The set of all logical addresses generated by a program is a logical
address space. The set of all physical addresses corresponding to
these logical addresses is a physical address space.
The run-time mapping from virtual to physical addresses is done by
a hardware device called the memory-management unit (MMU).
Logical Vs Physical Address Space
• The user program deals with logical addresses.
• The memory-mapping hardware converts logical addresses into
physical addresses.
• The final location of a referenced memory address is not
determined until the reference is made.
We now have two different types of addresses: logical addresses
(in the range 0 to max) and physical addresses (in the range R + 0
to R + max for a base value R).
Contiguous Memory Allocation
The memory is usually divided into two partitions: one for the
resident operating system and one for the user processes.
We can place the operating system in either low memory or high
memory. The major factor affecting this decision is the location of
the interrupt vector. Since the interrupt vector is often in low
memory, programmers usually place the operating system in low
memory as well.
In contiguous memory allocation, each process is contained in a
single section of memory that is contiguous to the section
containing the next process.
Contiguous Memory Allocation
One of the simplest methods for allocating memory is to divide
memory into several fixed-sized partitions. Each partition may
contain exactly one process. Thus, the degree of
multiprogramming is bound by the number of partitions. In this
multiple partition method, when a partition is free, a process is
selected from the input queue and is loaded into the free partition.
When the process terminates, the partition becomes available for
another process.
Contiguous Memory Allocation
Fixed-partition scheme: It is used primarily in batch environments.
Many of the ideas presented here are also applicable to a time-
sharing environment in which pure segmentation is used for
memory management In the variable-partition scheme, the
operating system keeps a table indicating which parts of memory
are available and which are occupied.
Contiguous Memory Allocation
Initially, all memory is available for user processes and is
considered one large block of available memory, a hole. Eventually,
as you will see, memory contains a set of holes of various sizes. As
processes enter the system, they are put into an input queue. The
operating system takes into account the memory requirements of
each process and the amount of available memory space in
determining which processes are allocated memory. When a
process is allocated space, it is loaded into memory, and it can
then compete for CPU time. When a process terminates, it
releases its memory, which the operating system may then fill with
another process from the input queue. At any given time, then, we
have a list of available block sizes and an input queue.
Contiguous Memory Allocation
The operating system can order the input queue according to a
scheduling algorithm. Memory is allocated to processes until,
finally, the memory requirements of the next process cannot be
satisfied—that is, no available block of memory (or hole) is large
enough to hold that process. The operating system can then wait
until a large enough block is available, or it can skip down the input
queue to see whether the smaller memory requirements of some
other process can be met.
Paging
Segmentation permits the physical address space of a process to
be noncontiguous.

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