Chapter 3 Logic Gates
Chapter 3 Logic Gates
Chapter 3 Logic Gates
Fundamentals
Tenth Edition
Floyd
Logic Gates
• Inverter
• AND Gate
• OR Gate
• Exclusive-OR Gate
• NAND Gate
• NOR Gate
• Exclusive-NOR Gate
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Summary
The Inverter A X
Input Output
A X
LOW (0) HIGH (1)
HIGH (1) LOW(0)
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Summary
The Inverter
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Summary
The Inverter A X
Example waveforms:
A
X
A group of inverters can be used to form the 1’s
complement of a binary number: Binary number
1 0 0 0 1 1 0 1
0 1 1 1 0 0 1 0
1’s complement
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Summary
A A
X & X
The AND Gate B
B
The AND gate produces a HIGH output when all inputs are
HIGH; otherwise, the output is LOW. For a 2-input gate,
the truth table is Inputs Output
A B X
0 0 0
0 1 0
1 0 0
1 1 1
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Summary
The AND Gate
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Summary
A A
X & X
The AND Gate B
B
Example waveforms:
A
B
X
The AND operation is used in computer programming as a
selective mask. If you want to retain certain bits of a binary
number but reset the other bits to 0, you could set a mask
with 1’s in the position of the retained bits.
If the binary number 10100011 is ANDed with
the mask 00001111, what is the result? 00000011
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Summary
The AND Gate
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Summary
A X A ≥1 X
The OR Gate
B B
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Summary
The OR Gate
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Summary
A X A ≥1 X
The OR Gate
B B
Example waveforms:
A
B
X
The OR operation can be used in computer programming to set certain
bits of a binary number to 1.
ASCII letters have a 1 in the bit 5 position for lower case letters
and a 0 in this position for capitals. (Bit positions are numbered
from right to left starting with 0.) What will be the result if you
OR an ASCII letter with the 8-bit mask 00100000?
The resulting letter will be lower case.
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Summary
The OR Gate
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Summary
A X A & X
The NAND Gate
B B
The NAND gate produces a LOW output when all inputs
are HIGH; otherwise, the output is HIGH. For a 2-input
gate, the truth table is Inputs Output
A B X
0 0 1
0 1 1
1 0 1
1 1 0
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Summary
The NAND Gate
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Summary
A X A & X
The NAND Gate
B B
Example waveforms:
A
B
X
The NAND gate is particularly useful because it is a
“universal” gate – all other basic gates can be constructed
from NAND gates.
How would you connect a 2-input NAND gate
to form a basic inverter?
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Summary
The NAND Gate
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Summary
A X A ≥1 X
The NOR Gate
B B
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Summary
A X A ≥1 X
The NOR Gate
B B
Example waveforms:
A
B
X
The NOR operation will produce a LOW if any input is HIGH.
+5.0 V
A
The LED will be on when any of B X
C
the four inputs are HIGH. D
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Summary
The NOR Gate
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Summary
A X A X
The XOR Gate =1
B B
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Summary
The XOR Gate
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Summary
A X A X
The XOR Gate =1
B B
Example waveforms:
A
B
X
Notice that the XOR gate will produce a HIGH only when exactly one
input is HIGH.
If the A and B waveforms are both inverted for the above
waveforms, how is the output affected?
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Summary
The XOR Gate
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Summary
A X A X
The XNOR Gate =1
B B
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Summary
A X A X
The XNOR Gate =1
B B
Example waveforms:
A
B
X
Notice that the XNOR gate will produce a HIGH when both inputs are the
same. This makes it useful for comparison functions.
If the A waveform is inverted but B remains the same, how is
the output affected?
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Summary
The XNOR Gate
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Summary
Integrated Circuits
Pins
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Summary
Fixed Function Logic
Two major fixed function logic families are TTL and CMOS.
A third technology is BiCMOS, which combines the first
two. Packaging for fixed function logic is shown.
0.335 – 0.334 in.
0.740 – 0.770 in. 14 13 12 11 10 9 8
14 13 12 11 10 9 8
1 2 3 4 5 6 7
1 2 3 4 5 6 7
Pin no.1 Lead no.1
identifiers identifier
14
1 14
1
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Summary
Fixed Function Logic
Some common gate configurations are shown.
VCC VCC VCC VCC
14 13 12 11 10 9 8 14 13 12 11 10 9 8 14 13 12 11 10 9 8 14 13 12 11 10 9 8
1 2 3 4 5 6 7 1 2 3 4 5 6 7 1 2 3 4 5 6 7 1 2 3 4 5 6 7
GND GND GND GND
'00 ' 02 '04 '08
1 2 3 4 5 6 7 1 2 3 4 5 6 7 1 2 3 4 5 6 7 1 2 3 4 5 6 7
GND GND GND GND
'10 '11 '20 '21
1 2 3 4 5 6 7 1 2 3 4 5 6 7 1 2 3 4 5 6 7 1 2 3 4 5 6 7
GND GND GND GND
'27 '30 '32 '86
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Selected Key Terms
Gate A logic circuit that performs a basic logic
operations such as AND or OR.
OR gate A logic gate that produces a HIGH output when
one or more inputs are HIGH.
A logic gate that produces a LOW output only
NAND gate
when all of its inputs are HIGH.
NOR gate A logic gate that produces a LOW output when one
or more inputs are HIGH.