.

CHAPTER- 04
BASIC COMPUTER
ORGANIZATION AND DESIGN
PART - ONE

1
 INSTRUCTION CODES
The user of a computer can control the process by means of a
program
A program is a set of instructions that specify the operations,
operand, the sequence(control)
An instruction is a binary code that specifies a sequence of
micro operations
Instruction codes together with data are stored in
memory(=Stored Program Concept)
The computer reads each instruction from memory and places it
in a control register.
The control then interprets the binary code of the instruction and
proceeds to execute itby issuing a sequence of micro operations.

2
 Cont..
Instruction Code :
 A group of bits that instruct the computer to perform a specific
operation
 It is usually divided into parts
Operation Code :
 The most basic part of an instruction code
 A group of bits that define such operations as add, subtract,
multiply, shift, and complement
Address part:
 To specify where the operand is found in the memory.

3
STORED PROGRAM ORGANIZATION
 The simplest way to organize a computer is to have one processor
register(AC) and an instruction code format with two parts.
One processor register : AC(Accumulator)
 The operation is performed with the memory operand and the
content of AC
Instruction code format with two parts: Op. Code + Address
 Op. Code : specify 16 possible operations(4 bit)
 Address : specify the address of an operand(12 bit)
 If an operation in an instruction code does not need an operand
from memory, the rest of the bits in the instruction(address field)
can be used for other.
E.g.:- Clear AC, Increment AC, Complement AC, ...
 Memory : 12 bit = 4096 word(Instruction and Data are stored)
 Store each instruction code(program) and operand (data) in
16-bit memory word
4
STORED PROGRAM ORG.(cont..)

5
ADDRESSING MODE
 Immediate operand address :
 the second part of an instruction code(address field) specifies an
operand
 Address part used as actual operand
 Direct operand address :
 the second part of an instruction code specifies the address of an
operand
 Indirect operand address :
 the bits in the second part of the instruction designate an
address of a memory word in which the address of the operand is found
 One bit of the instruction code is used to distinguish between a
direct and an indirect address :
 Effective Address
 The operand address in computation-type instruction or the target
address in a branch-type instruction
6
ADDRESSING MODES(cont..)

7
COMPUTER REGISTERS
 Computer instructions are normally stored in consecutive memory
locations and are executed sequentially at a time.
 List of Registers for the Basic Computer :
 PROGRAM COUNTER(PC) : hold the address of the next instruction
 DATA REGISTER(DR) : hold the operand(Data) read from memory
 ACCUMULATOR REGISTER(AC) : general purpose processing register
 INSTRUCTION REGISTER(IR) : hold the instruction read from memory
 TEMPORARY REGISTER(TR) : hold a temporary data during processing
 ADDRESS REGISTER(AR) : hold a memory address, 12 bit width
 INPUT REGISTER(INPR) : receive an 8-bit character from input device
 OUTPUT REGISTER(OUTR) : hold an 8-bit character for output device

8
Cont..
Program Counter(PC) :
hold the address of the next instruction to be read from memory
after the current instruction is executed
Instruction words are read and executed in sequence unless a
branch instruction is encountered
A branch instruction calls for a transfer to a nonconsecutive
instruction in the program
The address part of a branch instruction is transferred to PC to
become the address of the next instruction
To read instruction, memory read cycle is initiated, and PC is
incremented by one(next instruction fetch)

9
BASIC COMPUTER REGISTERS
Registers in the Basic Computer

10
COMMON BUS SYSTEM
 The basic computer has eight registers, a memory unit, and a
control unit.
 Paths must be provided to transfer information from one register to
another and between memory and registers
 The registers in the Basic Computer are connected using a bus
 This gives a savings in circuitry over complete connections between
registers
 The connection of the registers and memory of the basic computer
to a common bus system is shown as below :
 The system contain
Multiplexers
Bus
Registers
Memory
11
COMMON BUS SYSTEM

12
Cont..
 The outputs of seven registers and memory are connected to the
common bus
 The specific output is selected by mux(S0, S1, S2) :
 Memory(7), AR(1), PC(2), DR(3), AC(4), IR(5), TR(6)
 The particular register receives the data from the bus when LD is
enable
 The memory place its 16-bits o/p onto bus when the read input
is activated and S2S1S0=111.
 when S2S1S0=011,the o/p of DR is placed on bus.
 The 12-bit registers, AR and PC, have 0’s loaded onto the bus in
the high order 4 bit positions
 Control Input : LD, INC, CLR, Write, Read

13
Cont..
Accumulator(AC) :
 A 16-bits i/p of AC comes from an adder and logic ckt.
This circuit receive the 3 inputs
1) From o/p of AC itself: To clear AC, to shift AC,…
2) From DR : to ADD DR to AC, to AND DR to AC and so on…
3) From INPR : Device(Adder & Logic)
 Note:-Two micro operations can be executed at the same time

 i.e.:-This is done by placing content of AC on bus with S2S1S0=100

and making LD=1 of DR and transferring the content of AC through
adder and logic ckt, enabling the LD of AC .
 The transfer is happens at the end of clock pulse.
14
COMPUTER INSTRUCTIONS

15
Cont..
 The type of instruction is recognized by the computer control unit
from 4-bits in position 12 through 15
E.g.:-
if Op code is not 111, then it is MRI
If Op code=111 and I=0,then it is RRI
If Op code=111 and I=1, then it is IOI
 We have seen that only 3-bts are used for op code.
However, since RRI&IOI use the remaining 12-bits for operation,
the number of instruction will exceed 8.
 In fact, we have about 25 instruction in Basic Computer.

16
BASIC COMPUTER INSTRUCTIONS

17
INSTRUCTION SET COMPLETENESS
 A computer should have a set of instructions so that the user can
construct machine language programs to evaluate any function that is
known to be computable.
 The set of instructions are said to be complete if the computer include
all the following instruction :
 Functional(Computational) Instructions
 Arithmetic, logic, and shift instructions
 ADD, CMA, INC, CIR, CIL, AND, CLA
 Transfer Instructions
Data transfers between the main memory and the processor
registers
LDA, STA
 Control Instructions

Program sequencing and control

BUN, BSA, ISZ
 Input/output Instructions
Input and output
INP, OUT
18
 TIMING AND CONTROL
Clock pulses
 A master clock generator controls the timing for all registers in the
basic computer
 The clock pulses are applied to all F/Fs and registers in system
 The clock pulses do not change the state of a register unless the
register is enabled by a control signal
 The control signals are generated in the control unit
 The control signals provide control inputs for the multiplexers in
the common bus,
control inputs in processor registers, and micro operations for the
accumulator

19
Cont..
Two major types of control organization
1) Hardwired Control
 The control logic is implemented with gates, F/Fs, decoders, and
other digital circuits
 The operation is fast(advantage)
 the Wiring change has to be occur if the design has to be
modified(disdvtg)
2) Micro programmed Control
 The control information is stored in a control memory, and the
control memory is programmed to initiate the required sequence
of micro operations
 Any required change can be done by updating the micro program
in control memory(advantage)
 The operation is slow (disadvantage)
20
Cont..
 Control unit of Basic Computer

21
Cont..
 Control Unit = Control Logic Gate + 3 X 8 Decoder + Instruction
Register + Timing Signal
 Timing control signal is generated by 4-bit sequence counter and
4X16 decoder
 The instruction read from memory is placed in IR and the Op code
part is decoded by 3x8 decoder
 The 4-bits SC(sequence counter) is decoded to 16 timing signals
(T0 –T15)
 The SC can be incremented or cleared synchronously
 But, most time, the counter is incremented to provide the
sequence of timing signals
 Once the SC is cleared, this cause the next active timing signals to
be T0.

22
 Cont..
Let see the following example.
 Consider the case where SC is incremented to provide timing
signals T0,T1,T2,T3 &T4 in sequence
 Assume: At time T4, SC is cleared to 0 if decoder output D3 is
active.
 This is expressed symbolically by statement D3T4: SC 0
 The timing diagram w/c show the r/n s/p of the control signal

23
Cont..
 The SC is respond to the edge of clock pulse
 Initially the CLR I/p of SC is active
 The first edge of clock pulse clears SC to 0,w/c in turn activate the
timing signal T0.
 T0 is active for only one clock cycle
 T0 will trigger only those registers whose control I/p are connected
to timing signal T0.
 SC is incremented with every clock inputs pulse, unless its CLRs I/p is
active and this produce T0,T1,T2,T3 and T4.
 If SC is not cleared, the timing signals will continues with T5,T6,….T15
and back to T0.
 At T4,SC cleared and backed to T0.
 The last three waveforms shows how SC is cleared when :
D3T4=1, D3T4: SC 0
 When T4 is active,D3T4=1 at the end of T4 and this cause T0 active
24
Cont..
 A memory read or write cycle will be initiated with the rising edge
of a timing signals.
 It will be assumed that , a memory cycle time is less than the clock
cycle time,
 According to this assumption, a memory read or write cycle time
will be completed by the time next clock goes through its positive
transition.
 The clock transition will then be used to load the memory word to
a register
Example:- Register transfer statement :
 This specifies a transfer of the content of PC into AR if timing
signal T0=1

25
Cont..
 T0 is active during entire a clock cycle interval.
1) During T0
active, the content of PC is placed onto the bus (S2S1S0=010)
2) LD(load) input of AR is enabled, the actual transfer occurs at the
next positive transition of the clock(T0 rising edge clock)
3)This same clock transition increments the sequence counter SC
from 0000(T0) to 0001(T1).
 Sothat,T1 become active and T0 become inactive.

26
INSTRUCTION CYCLE
 The program is executed in the computer by going through a cycle for
each instruction.
 Each instruction cycle in turn is subdivided into a sequence of sub cycle or
phases.
 In Basic Computer, a machine instruction is executed in the following
cycle:
1.Fetch an instruction from memory
2.Decode the instruction
3.Read the effective address from memory if the instruction has an indirect
address
4.Execute the instruction
5.Go to step 1 : Next Instruction[PC + 1]
 After an instruction is executed, the cycle starts again at step 1, for the
next instruction
 This process continue indefinitely unless HALT instruction is encountered
27
Fetch and Decode

28
Cont..

29
DETERMINING THE TYPE OF INSTRUCTION
 The timing signal that active after decoding is T3.
 During time T3, the control unit determine the type of the
instruction that was just read from memory.
 The following flow chart present an initial configuration
for the instr. cycle and shows how the control determine the
instruction types after decoding.
 The three possible instruction types are
Memory-reference instruction
Register-reference instruction and
Input-output instr.

30
FLOWCHART FOR INSTRUCTION CYCLE TO DETERMINE THE INSTRUCTION TYPES

31
DETERMINE THE INSTRUCTION TYPES (CONT..)

32
REGISTER REFERENCE INSTRUCTIONS

33
Cont..

34
MEMORY REFERENCE INSTRUCTIONS
 The seven MRI are listed below.

 The o/p of Di is come from op code.

 The effective address of the instruction is in AR and was placed there during
timing signal T2when I = 0, or during timing signal T3when I = 1
 Memory cycle is assumed to be short enough to complete in a CPU
cycle
 The execution of MR instruction starts with T4
 The symbolic description is specified in above table in terms of RT
notation.
35
THE CONTROL FUNCTION AND MICROOPERATION
NEEDED FOR EXECUTION OF EACH MRI

36
Cont..

37
EXAMPLE OF BSA INSTR.
 Assume BSA instruction is at address of 20 and address part has
135
 After fetch and decode PC become PC+1=21
 AR hold EA=135,sothat, BSA perform M[AR] 21, AR 135 +
1=136
 Here, save the return address(21) in AR=135
 The next instruction address will be PC PC + 1=21
 The return to original program(to PC=21) is done by means of
indirect BUN instruction at the end of subroutine
 When BUN instruction is executed, the EA 21 is transferred to PC
indirectly .

38
Cont..

39
A FLOW CHART SHOWING ALL MICROOPERATION OF MRI
Memory-reference instruction

40
 Input-Output and Interrupt
 A computer can serve no useful purpose unless it communicates
with the external environment.
 Instructions and data stored in memory must come from some
input device.
 Commercial computers include many types of input and output
devices.
 To demonstrate the most basic requirements for input and output
communication, we will use as an illustration a terminal unit with
a keyboard and printer.

41
 Program Interrupt
 The process of communication just described is referred to as
Programmed Control Transfer
 The computer keeps checking the flag bit, and when it finds it set,
it initiates an information transform (this is sometimes called
Polling)
 This type of transfer is in-efficient due to the difference of
information flow rate between the computer and the I/O device
 The computer is wasting time while checking the flag instead of
doing some other useful processing task
 An alternative to the programmed controlled procedure is to let the
external device inform the computer when it is ready for the
transfer
 This type of transfer uses the interrupt facility

42
 Cont..
 While the computer is running a program, it does not check the flags
 Instead:
When a flag is set, the computer is immediately interrupted from
proceeding with the current program
The computer stops what it is doing to take care of the input or
output transfer
Then, it returns to the current program to continue what it was
doing before the interrupt
 The interrupt facility can be enabled or disabled via a flip-
flop called IEN
 The interrupt enable flip-flop IEN can be set and cleared
with two instructions (IOF, ION):
IOF: IEN  0 (the computer cannot be interrupted)
ION: IEN  1 (the computer can be interrupted)
43
Cont..
 Another flip-flop (called the interrupt flip-flop R) is used in the
computer’s interrupt facility to decide when to go through the
interrupt cycle
 FGI and FGO are different here compared to the way they acted
in an earlier discussion!!
 So, the computer is either in an Instruction Cycle or in an
Interrupt Cycle
 The interrupt cycle is a hardware implementation of a branch and
save return address operation (BSA)
 The return address available in PC is stored in a specific location
where it can be found later when the program returns to the
instruction at which it was interrupted
 This location may be a processor register, a memory stack, or a
specific memory location
44
 Input-output configuration 
 A  computer  can  serve  no  useful  purpose  unless  it  communica
tes  with  the  external environment.
 To exhibit the most basic requirements for input and output comm
unication, we will use a terminal unit with a keyboard and printer.

45
Cont..
 The terminal sends and receives serial information and each quantity of infor
mation has eight bits of an alphanumeric code.
 The serial information from the keyboard is shifted into the input register INP
R.
 The serial information for the printer is stored in the output register OUTR.
 These two registers communicate with a communication interface serially and
 with the AC in parallel.
 The transmitter interface receives serial information from the keyboard and tr
ansmits it to INPR. The receiver interface receives information 
from OUTR and sends it to the printer serially.
 The 1-bit input flag FGI is a control flip flop. It is set to 1 when new 

information is available in the input device and is cleared to 0 when the
 information is accepted by the computer.
 The flag is needed to synchronize the timing rate difference between the input
 device and the computer.
 The process of information transfer is as follows:
46
 Cont..
The process of outputting information:
 The  output  register  OUTR  works  similarly  but  the  direction  o
f  information  flow  is reversed.
 Initially, the output flag FGO is set to 1. The computer checks the f
lag bit; if it is 1, the information from AC is transferred in parallel
 to OUTR and FGO is cleared to 0. The output device accepts the 
coded information, prints the corresponding character, and
when the operation is completed, it sets FGO to 1.
 The computer does not load a new character into OUTR when FG
O is 0 because this condition indicates that the output device is
in the process of printing the character.

47
Cont..
The process of input information transfer:
 Initially, the input flag FGI is cleared to 0. When a key is struck in 
the keyboard, an 8-bit
alphanumeric code is shifted into INPR and the input flag FGI is se
t to 1.
 As long as the flag is set, the information in INPR cannot be chang
ed by striking another
key. The computer checks the flag bit; if it is 1, the information fro
m INPR is transferred in parallel into AC and FGI is cleared to 0.
 Once the flag is cleared, new information can be shifted into INPR 
by striking another key.

48
Input-Output instructions.
 Input and output instructions are needed for transferring informati
on to and from AC register, for checking the flag bits, and for
controlling the interrupt facility.
 Input-output  instructions  have  an  operation  code  1111  and  
are  recognized  by  the control when D7 = 1 and I = 1.
 The remaining bits of the instruction specify the particular operati
on.
 The control functions and micro operations for the input
output instructions are listed below.

49
 Cont..
The INP instruction transfers the input information from INPR into the eig
ht low-order bits of AC and also clears the input flag to 0.
The  OUT  instruction  transfers  the  eight  least  significant  bits  of  AC  
into  the  output register OUTR and clears the output flag
 to 0.
The next two instructions in Table 1. check the status of the flags and caus
e a skip of the next instruction if the flag is 1.
The instruction that is skipped will normally be a branch instruction to ret
urn and check the flag again.
The branch instruction is not skipped if the flag is 0. If the flag is 1, the br
anch instruction is skipped and an input or output instruction is executed.
The last two instructions set and clear an interrupt enable flip-
flop IEN. The purpose of
IEN is explained in conjunction with the interrupt 
operation.
 
50
 Interrupt Cycle
 The way that the interrupt is handled by the computer can be explained 
by means of the flowchart shown in figure 4.13.
 An interrupt flip-flop R is included in the computer.
 When R = 0, the computer goes through an instruction cycle.
 During the execute phase of the instruction cycle IEN is checked by the c
ontrol.
 If it is 0, it indicates that the programmer does not want to use the interru
pt, so control continues with the next instruction cycle.
 If IEN is 1, control checks the flag bits.
 If both flags are 0, it indicates that neither the input nor the output register
s are ready for transfer of information.
 In this case, control continues with the next instruction cycle. If either fla
g is set to 1 while IEN = 1, flip-flop R is set to 1.
 At the end of the execute phase, control checks the value of R, and if it is 
equal to 1, it goes to an interrupt cycle instead of an instruction cycle.
51
Cont..
 The interrupt cycle is a hardware implementation of a branch and 
save return address operation.
 The return address available in PC is stored in a specific location 
where it can be found later when the program returns to the
instruction at which it was interrupted. This location may be a 
processor register, a memory stack, or a specific memory location.
 Here we choose the memory location at address 0 as the place for 
storing the return address.
 Control then inserts address 1 into PC and clears IEN and R so tha
t no more interruptions can occur until the interrupt request
 from the flag has been serviced.
 An example that shows what happens during the interrupt cycle is 
shown in Figure below:
52
 Cont..

Suppose that an interrupt occurs and R = 1, while the control is exe
cuting the instruction
at address 255. At this time, the return address 256 is in PC.
The programmer  has  previously placed  an  input-output  service 
program  in  memory
starting from address 1120 and a BUN 1120 instruction at address 1.
·
53
Cont..
 The content of PC (256) is stored in memory location 0, PC is set to 1, and R is 
cleared to 0.
 At the beginning of the next instruction cycle, the instruction that is read from 
memory is in address 1 since this is the content of 
PC. The branch instruction at address 1 causes the program to
 transfer to the input-output service program at address 1120.
 This program checks the flags, determines which flag is set, and then transfers 
 The
required input or output information. Once this is done, the instruction ION
 is executed to set IEN to 1 (to enable  further interrupts), and the program returns 
to the Location where it was interrupted.
 The instruction that returns the computer to the original place in the main progr
am is a branch indirect instruction with an address part of 0. This instruction is 
placed at the end of the I/O service program.
 The  execution  of  the  indirect  BUN  instruction  results  in  placing  into  PC 

 the  return address from location 0.
54
Cont..
Further Questions:
I. How can the CPU recognize the device requesting an
interrupt?
II. Since different devices are likely to require different interrupt
service routines, how can the CPU obtain the starting address
of the appropriate routine in each case?
III. Should any device be allowed to interrupt the CPU while
another interrupt is being serviced?
IV. How can the situation be handled when two or more interrupt
requests occur simultaneously?

55
.

CHAPTER- 04
PROGRAMMING THE BASIC
COMPUTER
PART - TWO

56
Introduction

57
6-3 Assembly Language
The rules for writing assembly language program
Documented and published in manuals(from the computer
manufacturer)
Rules of the Assembly Language
Each line of an assembly language program is arranged in
three columns
 1) Label field : empty or symbolic address
 2) Instruction field : machine instruction or pseudo
instruction Label Instruction Comment
 3) Comment field : empty or comment

58
Cont..
Symbolic Address(Label field)
One, two, or three, but not more than three alphanumeric characters
 The first character must be a letter; the next two may be letters or
numerals
 A symbolic address is terminated by a comma(recognized as a
label by the assembler)
Instruction Field
 1) A memory-reference instruction(MRI)
 Ex) ADD OPR(direct address MRI), ADD PTR I(indirect
address MRI)
 2) A register-reference or input-output instruction(non-MRI)
 Ex) CLA(register-reference), INP(input-output)
 3) A pseudo instruction with(ORG N) or without(END) an
operand
 Pseudo instruction :Machine Instruction, Assemble
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Cont..

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 Cont..
 An assembler is a program that accepts a symbolic language
program and produces its binary machine language equivalent.
 The input symbolic program is called the source program and the
resulting binary program is called the object program.
 The assembler is a program that operates on character strings and
produces an equivalent binary interpretation.
 The binary program constitutes the output generated by the
assembler.
 We will now describe briefly the major tasks that must be
performed by the assembler during the translation process.

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 Two Pass Assembler
First pass
Assign addresses to all statements in the program
Save the values (addresses) assigned to all labels (including
label and variable names) for use in Pass 2 (deal with forward
references)
Perform some processing of assembler directives (e.g., BYTE,
RESW, these can affect address assignment)
Second pass
Assemble instructions (generate opcode and look up addresses)
Generate data values defined by BYTE, WORD
Perform processing of assembler directives not done in Pass 1
Write the object program and the assembly listing

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A Simple Two Pass Assembler Implementation

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Program Loops
 A program loop is a sequence of instructions that are executed
many times, each time with a different set of data.
Loop
Loops statements are used to repeat the execution of
statement or block.
 Two types of loop structures are:-
 Pretest:- condition is tested before each iteration to check if loop
should occur.
 E.g. for loop and while loop
 Posttest:- condition is tested after each iteration to check if loop
should continue (at least single iteration occurs.
 E.g. Do-while loop

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Programming Arithmetic & Logic Operations
Software Implementation
 Implementation of an operation with a program using machine
instruction set
 Usually used: when the operation is not included in the
instruction set
Hardware Implementation
 Implementation of an operation in a computer with one
machine instruction
Multiplication
 We will develop a program to multiply two numbers.
 Assume positive numbers and neglect the sign bit for simplicity.
 Also, assume that the two numbers have no more than 8
significant bits  16-bit product.

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Cont..

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Double Precision Addition
 When two 16-bit unsigned numbers are multiplied, the result is a
32-bit product that must be stored in two memory words.
 A number stored in two memory words is said to have double
precision.
 When a partial product is computed, it is necessary to add a
double-precision number to the shifted multiplicand, which is also
double-precision.
 One of the double precision numbers is stored in two consecutive
memory locations, AL & AH. The other number is placed in BL &
BH.
 The two low-order portions are added and the carry is transferred
to E. The AC is cleared and E is circulated into the LSB of AC.
 The two high-order portions are added and the sum is stored in CL
& CH.

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Arithmetic Shift Operations
 Arithmetic shift right: it is necessary that the sign bit in the
leftmost position remain unchanged. But the sign bit itself is
shifted into the high-order bit position of the number.
CLE / Clear E to 0
SPA / Skip if AC is positive, E remains 0
CME / AC is negative, set E to 1
CIR / Circulate E and AC
 Arithmetic shift left: it is necessary that the added bit in the LSB
be 0.
CLE
CIL

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Cont..
 The sign bit must not change during this shift.
 With a circulate instruction, the sign bit moves into E.
 The sign bit has to be compared with E after the operation to
detect overflow.
 If the two values are equal  No overflow.
 If the two values are not equal  Overflow.

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Subroutines
 The same piece of code might be written again in many different
parts of a program.
 Write the common code only once.
 Subroutines :A set of common instructions that can be used in a
program many times
 Each time a subroutine is used in the main program, a branch is
made to the beginning of the subroutine. The branch can be made
from any part of the main program.
 After executing the subroutine, a branch is made back to the main
program.
 It is necessary to store the return address somewhere in the
computer for the subroutine to know where to return.
 In the basic computer, the link between the main program and a
subroutine is the BSA instruction.
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Subroutine Parameters and Data Linkage
 When a subroutine is called, the main program must transfer the
data it wishes the subroutine to work with.
 It is necessary for the subroutine to have access to data from the
calling program and to return results to that program.
 The accumulator can be used for a single input parameter and a
single output parameter.
 In computers with multiple processor registers, more parameters
can be transferred this way.
 Another way to transfer data to a subroutine is through the
memory.
 Data are often placed in memory locations following the call.

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