MECHATRONICS - Unit Notes
MECHATRONICS - Unit Notes
• 1969 -The ‘mechatronics’ word introduced by Tessturo Mori. He was a senior engineer of Japanese
company Yaskawa Electric Corporation.
• 1971 – the company was granted the trademark rights on the word.
Signals and
conditioning
Digital logic
systems
Computers and
display devices
Elements of mechatronics system
• Actuators and sensors
• Actuators – pneumatic & Hydraulic actuator, electromechanical actuators,
electrical motor such as DC motor, AC motor, stepper motor, servo motor & piezo
electric actuators
• Sensors – linear and rotational sensor, acceleration sensor, force, torque and
pressure sensor, temperature sensor, proximity sensors, light sensors
• Signals and conditioning
• Two types: input and output
• Input signal conditioning devices: discrete circuits, amplifiers, analog to
digital(A/D) convertors, Digital to Analog (D/A) convertors.
• Output signal conditioning devices: amplifiers, Digital to Analog (D/A) convertors,
display decoders (DD) convertors, power transistors.
Elements of mechatronics system
• Digital logic systems
• Logic circuits, micro controllers, programmable logic controllers(PLC), sequencing
and timing controls, control algorithm.
Control
Microprocessor
Functional Block diagram of
Microprocessor
• ALU (Arithmetic and Logic Unit)
• It carries out arithmetic and logic operations on 8 bit word.
• Arithmetic operation – addition, subtraction , multiplication , division etc.,
• Logic operation - AND,OR,EX-OR
• The content of accumulator and temporary register are the input to the ALU.
• ALU output is stored in accumulator
• Register array
• Register is a storage unit within the microprocessor used to store the data,
address of instruction of any program.
• Microprocessor contained 6 general purpose register it has 8- bit memory
• Registers are B,C,D,E,H and L
• To hold 16-bit data a combination of two 8-bit registers can be used.
• The combination of two 8-bit registers is known as Register Pair (BC, DE and HL).
• These Registers are used to store data temporarily during execution of the
program.
• Control Unit
• The timing and control unit acts as the brain of a computer.
• It controls all operations of the CPU.
• It controls input, output and all other devices connected to the CPU.
Evolution of
Microprocessor
• First generation Microprocessor
• 1st Microprocessor, Intel 4004, a 4 bit PMOS Microprocessor introduced in
1971 by the Intel corporation, USA.45 instructions and 2300 transistors
• It has limited memory-simple aplications.
• An enhanced version of Intel 4004 is Intel 4040.
• e.g., Toshiba’s 73472, Rockwell International’s PPS-4 National IMP-4 etc.,
Evolution of
Microprocessor
• Second generation Microprocessor
• In 1972, Intel introduced 8- bit Microprocessor named as Intel 8008, which
also uses PMOS technology.
• But this technology was slow and not compatible with TTL logic
• In 1973, Intel introduced more powerful and fast 8- bit NMOS
Microprocessor called Intel 8080-3 power supplies.
• 1975-Intel 8085 is the improved version of Intel 8080
• Third generation Microprocessor
• In 1978 Intel introduced a 16- bit Microprocessor called Intel 8086.
• Other 16- bit Microprocessor are Intel 80186, Intel 80286, zilog’s z8000,
Motorola’s 68000, 68010 etc.,
• Forth generation Microprocessor
• In 1980-32bit-Iapx432-not popular
• In 1985 Intel introduced a 32- bit Microprocessor called Intel 60386-desktop -
386MP
• Fifth generation Microprocessor
• Intel i860 is a 64 bit RISC microprocessor
Architecture of
8085
• Three main section
• ALU
• Timing and Control unit-
• Set of register
ARCHITECTURE OF 8085
• ALU
• Addition, Subtraction, Logical AND,OR…etc
• Timing and Control Unit
• timing and control signals –execution of instructions
• Controls the entire operation of the microprocessor
• Register
• 1- 8 bit Accumulator….i.e.-register A (ACC)
• 6-8 bit general purpose register (B,C,D,E,H & L)
• 1- 16 bit register –SP(Stack Pointer)
• 1 -16 bit –PC (Program Counter)
• Instruction register
• Temporary register
• Flag register
• Flag register
• Carry flag (CY) – it is set, If carry or borrow occurs during the arithmetic
operation.
• Parity flag (P) – it is set, if the result has even number of it otherwise made 0.
• Auxiliary carry flag (AC) – Binary coded decimal operations (BCD)
• Zero flag (z) – is set if the result becomes 0
• Sign flag (S) – is set if the result becomes –ve, if +ve, it is set to 0
• 2 bit (don’t care )
Pin diagram
Signals in 8085 IO/M S0 S1
• 6 group of signals
• Power supply and Clock frequency
0 0 1 Memory write
• VCC +5 (WR=0
• VSS-Ground RD=1,INTA=1)
• X1,X2-F=f crystal freq/2=3MHZ
0 1 0 Memory Read
• CLK
(WR=1
• Address bus (A15-A8)-
RD=0,INTA=1)
• Unidirectional
• Data bus (AD7-AD0) 0 1 1 Opcode fetch
• Bi-directional both data and (WR=1
RD=1,INTA=1)
Address bus(Multiplexed)
• Control and Status signals 1 0 1 I/O write(WR=0
• ALE (Address Latch Enable)-Demultiplex RD=1,INTA=1)
Active High
If ALE=1 (AD7-AD0) will act as A7-A0 1 1 0 I/O Read(WR=1
If ALE=0 (AD7-AD0) will act as D7-D0 RD=0,INTA=1)
• RD,WR,IO/M,S0,S1
• IO/M=0 (Memory related operation)
• IO/M=1 (I/O related operation) 1 1 1 INTA (WR=1
• S1,S0-0 1(WR Operation) RD=1,INTA=0)
• 1 0 (RD Operation)
• 1 1 ( Either Opcode fetch or Interrupt Acknowledge)
• Externally initiated signals
• INTR
• INTA(Active low signal )
• TRAP
• RST 7.5,RST6.5,RST 5.5
• READY
• HOLD(Direct Memory Access)
• RESET IN (Active low signal-Internal registers alters randomly (BC,DE…))
• RESET OUT(Outside devices will be reset)
• HLDA (Direct Memory Access)
• Serial I/O Ports
• SID(Only for serial communications—Bit by Bit)
• SOD
ADRESSING MODES IN 8085
• Direct addressing
• Register addressing
• Register indirect addressing
• Immediate addressing
• Implicit addressing
• Direct addressing (Address of the operand is directly specified)
• LDA 5000H (Load accumulator A with the contents of memory location 5000H)- 3
Byte instruction (LDA- Opcode,50- Higher order,00-Lower order)- Memory Address
• STA 3010H (Store the content of the accumulator in the memory location 3010H)
(STA-Opcode, 30- Higher order,10-Lower order)- Memory Address
• MOV B, D (move the content of register D to register B)- Mostly 1 byte instruction
(Only opcode no operand)
• Register indirect addressing (The content of the register pair is used as address
of the operand)
• There are certain instruction which operate the content of the accumulator.
• Such instruction do not require the address of the operand
• CMA (Compliment accumulator)
• RAL (Rotate accumulator left)
• RAR (Rotate accumulator right)
Instruction sets 8085
Instruction format
Opcode, Operand
Based on format
1 Byte instruction MOV A,B -(8 bits) HALT -(8 bits) ----(Only opcode)
2 Byte instruction MOV B, 08H-- MOV B ---(8 bits) 08H-- -(8 bits)
3 Byte instruction STA- -(8 bits) 6020H---(8 bits+8 bits )
Based on Operation
• Data transfer group (Memory to Memory- Data will not be transferred)-
No Flags are affected
• Arithmetic group (Addition, Subtraction…)-All Flags are affected
• Logical group(AND,OR,XOR..)-All Flags are affected
• Branch group (CALL,JUMP)-No Flags are affected
• Stack, I/O and Machine control group (HALT)-No Flags are affected
Data transfer group
Data transfer group
Data transfer group
Data transfer group
Data transfer group
Data transfer group
Data transfer group
Data transfer group
Data transfer group
Data transfer group
Data transfer group
Data transfer group
Data transfer group
Data transfer group
Data transfer group
• MOV Rd, Rs
XRI 71H- XOR immediate with accumulator (The result will be stored
in accumulator)
ORA H- Logical OR with register/memory
Logical group
XRI 71H Immediate OR with register/memory
JMP-Conditional
JN Jump on carry ( Go to alloted memory location)
JNC Jump on No carry
JZ Jump on Zero (Z=1)
JNZ Jump on No Zero (Z=0)
JP Jump possitive
JM Jump minus
JPE Jump on Even parity
JPO Jump on Odd parity
CALL Unconditional
CALL 7010H
Branch Instruction group
CALL Conditional
CC
CNC
CZ
CNZ
CP
CM
CPE
CPO
RET (Return Instrstruction-Unconditional)
RET Contitional
CC,CNC,CZ ,CNZ,CP,CM,CPE,CPO
RST(Restart)
Machine Control Group
NOP
No Operation
Fetch and decode
No oerations
HLT
Halt
Register content not modified
DI- Disable Interrupt
Critical programs-Disable
EI- Disable Interrupt
Critical programs-Enable
RIM –Read Interrupt Mask
Pheriperal data will be sent to MP
0100 0000
SIM-Set Interrupt Mask
Give instruction to interrupt(from accumulator)
RIM (Read Interrupts Mask)
SIM(Set Interrupts Mask)
Timing diagram of
8085
• Opcode fetch cycle (4T or 6T)
• Memory Read cycle (3T)
• Memory write cycle (3T)
• I/O read cycle (3T)
• I/O write cycle (3T)
• Interrupt acknowledge (6T or 12T)
• Bus idle cycle (2T or 3T)
Timing Diagram
OPCODE FETCH
Memory Read
cycle
Memory write
cycle
I/O read
cycle
I/O write
cycle
□ Fetching the Opcode 06H from the memory 2000H. (OF machine cycle)
□ Read (move) the data 43H from memory2001H. (memory read)
STA 526AH
STA means Store Accumulator -The contents of the accumulator is stored in the
specified address(526A).
The opcode of the STA instruction is said to be 32H. It is fetched from the memory
41FFH(see fig). - OF machine cycle
Then the lower order memory address is read(6A). - Memory Read Machine Cycle
Read the higher order memory address (52).- Memory Read Machine Cycle
The combination of both the addresses are considered and the content from
accumulator is written in 526A. - Memory Write Machine Cycle
Assume the memor y addr ess for the instr uction and let the content of
accumulator is C7H. So, C7H from accumulator is now stored in 526A.
IN C0H
• 8 bit CPU
• On chip oscillator
• 4Kb of ROM
• 128 bytes of RAM
• 21 special functions register
• 32 I/O lines
• 64 KB address space for external data memory
• 64 KB address space for program memory
• 2 16-bit timer/counter
Block diagram of
8051
Block diagram of
8051
Program Status word- Current status of the Microcontroller
IR Instruction register
DPTR-Data pointer (All the address)
Program Counter –Next instruction is to be fetched
Buffer-Check the data
Program Additional Register
ROM- Permanent data will be stored
RAM- Both read and write
Stack Register- Details of all Information
SFR-(Special function register)
Port 0,1,2,3-32 Pins
OSC-To generate the Clock
PSEN-(Program Store Enable)-Active low pin-64Kb of external ram-
EA-External Access
Block diagram of
8051
UNIT
3
PROGRAMMABLE PERIPERAL INTERFACE
Content
• Introduction
• Architecture of 8255
• Keyboard interfacing
• LED display –interfacing
• ADC and DAC interface
• Temperature Control
• Stepper Motor Control
• Traffic Control interface
Introduction
• To communicate with the outside world, microprocessor use peripherals
(I/O devices)
• Input devices – Keyboards, A/D converters etc.,
• Output devices – CRT, Printers, LEDs etc.,
• Peripherals are connected to the microprocessors through electronic
circuit known as interfacing circuits.
Microprocessors unit with I/O
devices
Input Output
Micro
devices
(keyboard processor devices
) s (LED)
Input Output
peripherals peripherals
• Some of the general purpose interfacing devices
• I/O ports
• Programmable peripherals interface (PPI)
• DMA controllers
• Interrupt controller
Input
devices Micro Output
PPI 8279
(key 8255 Display
proce device
board) ssors (LED)
Periphera Display
l Interfac
Interface e
Address Space
Partitioning
• The Microprocessors uses 16 bit wide address bus for addressing
memories and I/O devices.
• Using 16 bit wide address bus, it can access 216 = 64k bytes of
memory and I/O devices
• Two schemes for the allocation of addresses to memories
and I/O
devices
• Memory mapped I/O
• I/O mapped I/O
Memory mapped I/O
• When signal is high, then address on the address bus is for an I/O
devices
• When signal is low, then address on the address bus is for memory
locations
• Two extra instruction IN and OUT are used to address I/O devices.
• The IN instruction is used to read the data of an input devices.
• The OUT instruction is used to send the data of an input devices.
• This scheme is suitable for a large system.
PROGRAMMABLE PERIPHERALS INTERFACE
INTER 8255 (PPI)
Operating mode of 8255
CS A1 Ao Result
0 0 0 Port A
0 0 1 Port B
0 1 0 Port C
0 1 1 Control Register
1 X X No Selection
Operating mode of 8255
• Bit Set Reset (BSR) Mode
• I/O Mode
I/O
Mode
• The 8255 has the following 3 modes of operation
• Mode 0 – Simple Input/output
• Mode 1 – Input / Output with the Handshake or strobed
• Mode 2 – Bi-directional I/O
I/O
Mode
Mode 0 – Simple Input/output
• Port A and port B are used as two simple 8-bit I/O port
• Port C as two 4-bit port
• Features
• Outputs are latched
• Inputs are buffered not latched
• Ports do not have handshake or interrupt capability
I/O
• Mode 1 – Input / Output with the Handshake
Mode
• Input or output data transfer is controlled by handshaking signals.
• Handshaking signals are used to transfer data between devices whose data
transfer speeds are not same.
• Port A and Port B are designed to operate with the Port C.
• When Port A and Port B are programmed in Mode 1, 6 pins of port C is
used for
their control.
I/O
• D0-D7 data bus
Mode
– bi directional, tri state data bus line
– It is used to transfer data and control word from 8085 to 8255
• RD (Read)
– When this pin is low, the CPU can read data in the port or status word through
the data buffer
• WR (write)
– When this pin is low, the CPU can write data in the port or in the control register
through the data buffer
I/O
•
Mode
Mode 2 – Bi-directional I/O
• Port A can be programmed to operate as a bidirectional port.
• The mode 2 operation is only for port A
• When port A is programmed in Mode 2, the Port B can be used in either
Mode 1 or Mode 0.
• Mode 2 operation the port a is controlled by PC3 to PC7 of port C.
PIN
DIAGRAM
OF 8255
Traffic Light Control System Using 8085
One at a time
T=10 sec; Yellow will glow
PROGRAMMING and OPERATION of
8255
• Programming in MODE 0
• D7 –set to 1
• D6,D5,D2- all set to 0 –MODE 0
• D4,D3,D1 and D0- determine weather the corresponding ports are to
configured as input or output
A B GROUP A GROUP B
D4 D3 D1 D0 PORT A PORTC U PORT B PORT C L
• Introduction
• Basic structure
• Input and output processing
• Programming
• Mnemonics
• Timers, counters and internal relays
• Data handling
• Selection of PLC
PROGRAMMABLE LOGIC
CONTROLLER
• A Programmable Logic Controller(PLC) is a digital computer used for
automation of typically industrial electromechanical processes, such
as control of machinery on factory assembly lines, amusement rides
or light fixtures.
Application
s
• Automated manufacturing process equipment and machinery
• Packaging and filling equipment
• Chemical mixing
• Conveyor systems and distillation etc.,
Features and specification
• They are rugged and designed to withstand vibration, temperature,
humidity and noise
• The interfacing for inputs and outputs is inside the controller.
• They are easily programmed and have an easily understood
programming language.
• Programming is primarily concerned with logic and switching
operation.
Hardwired motor
circuit
Hardwired motor circuit with
PLC
Basic structure
• PLC is designed as a replacement for the hardwired relay and timer
logic, where PLC provides ease and flexibility of control based on
programming and executive logical instruction.
• The internal functions such as timers, counter and shift registers
making sophisticated control possible using even the smallest PLC.
• PLC capable of performing function such as
• counting,
• logistics,
• numerical application,
• comparing and processing of signals.
• A PLC is divided in to 4 parts. They are
• Input/output module (I/O)
• Central processing Unit (CPU)
• Memory
• Programming unit
i) Input/output module (I/O)
• It is used to transfer the data between external devices and CPU
• It is incorporated into PLC in two ways
I. Fixed I/O – it is a small unit that comes in one piece with processor i.e., the
I/O terminals cannot be changed in fixed I/O
II. Modular I/O – it is packed together i.e., there are several compartment of
I/O module are plugged together.
Central processing Unit (CPU)
• It is consisting of a microprocessor which interrupts the input signal and
carries out the control actions according to the program stored in the
memory, communicating the decision as an action signal to the output.
• It scan the total information package stored in the memory and input and
output devices continuously.
• During the scan the CPU executes instruction based on input data, sends
appropriate output responses to the output devices, updates data
acquisition systems and indicate condition changes
• Scan time for larger unit depends on the size of the memory and
configuration of the system
• Power supply unit is needed to convert the AC voltage to the low DC
voltage necessary for the processor and to supply power to other
circuit in the input and output interface module.
Memory
Unit
• The memory in PLC stores the digital control logic, the process
program and the necessary instruction to operate the system.
• The memory used in PLC are
• Non-volatile memory
• Volatile memory
• According to purpose of usage
• RAM –volatile memory
• ROM- permanent storage
Programming
unit
• It is used to enter the required program into the memory of the
processor
• There are normally 3 approaches followed by the program
• Use of hand held programmer
• Terminal with video display unit
• PC with appropriate software
Architecture
• Buses
• Data buses – it is used for communicating data b/n elements
• Address buses-it is used to read the address of locations for accessing stored
data
• Control buses- it is used for internal control action carried by the CPU
• System buses- it is used for communication b/n Input/output ports and
input/output units
• Memory
• RAM
• ROM
• PROM
• EPROM
• Electrically EPROM
Optoisolator
An AND System
An OR System
NOT System
NOR System
NAND System
XOR System
Cylinder
Sequencing A+,
B+, A- and B-
List of Mnemonics used for the Mitsubishi f
Series PLC
Mnemonics for Logic
system
Mnemonics for Logic
system
Time
r
Timer circuit programmed to cause an output to go
ON for 0.5s, then OFF for 0.5s, then OFF for 0.5s
and so on
ON-OFF
cycle timer
Internal relay
Counter
Master control relay
JUMP
Instruction
Data
handling
• Data movement
• Data comparison
• Arithmetic operation
• Code conversion
Data Movement
Controlling the speed of motor
Selection of
PLC definition
• System
• Choosing the I/O hardware
• I/O timing consideration
• Analog I/O module –resolution, voltage level
• Conversion speed
• Analog closed control
• Communication
• Counter, encoders and positioning
• Selecting suppliers
UNIT
ACTUATORS AND MECHATRONICS SYSTEMS DESIGN
5
CONTE
NT
Types of stepper and servo motors – construction, working principle
Design process - Stages in designing mechatronics system
Traditional and mechatronic design concept
Possible design solution
Case studies of mechatronics systems
Pick and place robot
Engine management system
Automatic car park barrier
Stages in designing mechatronics system
Need for design
Analysis of problem
Preparation of specification
Evaluation
Implementation of design
Traditional
design
A mechanical system
A
mechanical
system
Electronic
components,
computers & IT
systems
Comparison of traditional and mechatronics
design