19ECE313 – VLSI

DESIGN
Shruthi A S
ECE Department
Amrita School of Engineering Bangalore
Tutorial
Design a single bit magnitude comparator using TG and inverters if needed.
SHRUTHI, DEPT. OF ECE, ASE, BANGALORE
SHRUTHI, DEPT. OF ECE, ASE, BANGALORE
DEPT. OF ECE, ASE, BANGALORE
SHRUTHI, DEPT. OF ECE, ASE, BANGALORE
SHRUTHI, DEPT. OF ECE, ASE, BANGALORE
 Solved Problems
Example 1. Find the output capacitance in the NOT gate shown in Figure.

Solution :
 Solved Problems
Example 2. Consider an inverter circuit that has FET aspect ratio of (W/L) n = 6 and (W/L)p = 8 in a process where k’n = 150 µA/V2, VTn =
0.70V,
k’p = 62 µA/V2, VTp = - 0.85 V, VDD = 3.3 V. The total output capacitance is estimated to be C out = 150 fF. Compute rise time, fall
time and maximum signal frequency.
Solution :
 Assignment-1
1. An inverter uses FETs with βn = 2.1 mA/V2 and βp = 1.8 mA/V2. The threshold voltages are given as Vtn = 0.6 V and Vtp = - 0.7V and the
power supply has a value of VDD = 5 V. The parasitic FET capacitance at the output node is estimated as C FET = 74 fF.
(a) Find the midpoint voltage. (2.378 V)
(b) Find the values of Rn and Rp. (108.23 ohm, 129.2 ohm)
(a) Calculate the rise time and fall times at the output when C L = 0. (21.03ps, 17.62ps)
(b) Calculate the rise time and fall time when an external load of value C L = 115 fF is connected to the output. (53.72ps, 45ps)
(e) Plot rise time and fall time as functions of CL.

2. A CMOS inverter is designed with βp= 80 μA/V2, βn= 0.25 mA/V2, Vtn =|Vtp|= 0.5 V and VDD = 2.5 V. The total capacitance at the
output is 50fF.
(a) Using general expression for MOSFET resistance in saturation, what is the resistance for each transistor? (Rn= 2 Kohm, Rp= 6.25 Kohm)
(b) What is the rise time of this circuit? (685.5ps)
(c) What is the fall time of this circuit? (220ps)
(d) What is the high-to-low propagation delay for this inverter? (69.3ps)
(e) What is the low-to-high propagation delay for this inverter? (217ps)

3. Consider the NOT gate shown in figure of example 1 when an external load of CL = 80fF is connected to the output. The electrical channel
length is L = 0.8 μm.
(a) Find the input capacitance of the circuit. (32.4 fF) Hint :
(b) Find the values of Rn and Rp. (303.03 ohm, 387.6 ohm)
(c) Calculate rise and fall times for the inverter. (111.24ps, 87.04ps)
1. A CMOS NAND2 is designed using identical nFETs with a value of β n = 2βp; the pFETs are the same size. The power supply is chosen to be
VDD = 5 V and the device threshold voltages are given as V Tn = 0.6 V and VTp = -0.7 V.
(a) Find the midpoint voltage VM for the case of simultaneous switching. (2.77 V)
(b) What would be the midpoint voltage for an inverter made with the same β specifications? (2.13 V)
2. A CMOS NOR2 gate is designed using nFETs with a value of βn. The pFETs are both described by βp = 2.2 βn. Find the value of VM for the case

of simultaneous switching if VDD = 3.3 V, VTn = 0.65 V and VTp = - 0.80 V. (1.47 V)
 Assignment-2
1. A CMOS NAND2 is designed using identical nFETs with a value of β n = 2βp; the pFETs are the same size. The power supply is chosen to be
VDD = 5 V and the device threshold voltages are given as VTn = 0.6 V and VTp = -0.7 V.
(a) Find the midpoint voltage VM for the case of simultaneous switching. (2.77 V)
(b) What would be the midpoint voltage for an inverter made with the same β specifications? (2.13 V)

2. A CMOS NOR2 gate is designed using nFETs with a value of βn. The pFETs are both described by βp = 2.2 βn. Find the value of VM for the case
of simultaneous switching if VDD = 3.3 V, VTn = 0.65 V and VTp = - 0.80 V. (1.47 V)

3. A NAND3 gate uses identical nFETs with an aspect ratio of 4. The nFET process transconductance is 120 µA/V 2, and the threshold voltage
is 0.55 V. A power supply of 5 V is chosen for the circuit.
Find the value of the pFET βp needed to create a gate where the case of simultaneous switching gives a midpoint voltage of
VM = 2.4 V, Assume that VTp = -0.90 V and r = 2.4. (63.16 µA/V2)
 Assignment-3
1. A CMOS NAND2 is designed using identical nFETs with a value of β n = 2βp; the pFETs are the same size. The power supply is chosen to be
VDD = 5 V and the device threshold voltages are given as VTn = 0.6 V and VTp = -0.7 V.
(a) Find the midpoint voltage VM for the case of simultaneous switching. (2.77 V)
(b) What would be the midpoint voltage for an inverter made with the same β specifications? (2.13 V)

2. A CMOS NOR2 gate is designed using nFETs with a value of βn. The pFETs are both described by βp = 2.2 βn. Find the value of VM for the case
of simultaneous switching if VDD = 3.3 V, VTn = 0.65 V and VTp = - 0.80 V. (1.47 V)

3. A NAND3 gate uses identical nFETs with an aspect ratio of 4. The nFET process transconductance is 120 µA/V 2, and the threshold voltage
is 0.55 V. A power supply of 5 V is chosen for the circuit.
Find the value of the pFET βp needed to create a gate where the case of simultaneous switching gives a midpoint voltage of
VM = 2.4 V, Assume that VTp = -0.90 V and r = 2.4. (63.16 µA/V2)