University Institute of Engineering

DEPARTMENT OF COMPUTER SCIENCE

MULTIPROCESSORS DISCOVER . LEARN . EMPOWER

• Uniform and non-uniform memory access multi processors

• various interconnection networks.

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 COUPLING OF PROCESSORS
• Tightly Coupled System
• - Tasks and/or processors communicate in a highly synchronized fashion
• - Communicates through a common shared memory
• - Shared memory system
• Loosely Coupled System
• - Tasks or processors do not communicate in a
• synchronized fashion
• - Communicates by message passing packets
• - Overhead for data exchange is high
• - Distributed memory system

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 GRANULARITY OF PARALLELISM
Coarse-grain
• - A task is broken into a handful of pieces, each
• of which is executed by a powerful processor
• - Processors may be heterogeneous
• - Computation/communication ratio is very high
Medium-grain
• - Tens to few thousands of pieces
• - Processors typically run the same code
• - Computation/communication ratio is often hundreds or more
Fine-grain
• - Thousands to perhaps millions of small pieces, executed by very
• small, simple processors or through pipelines
• - Processors typically have instructions broadcasted to them
• - Compute/communicate ratio often near unity

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 SHARED MEMORY MULTIPROCESSORS
Characteristics
• All processors have equally direct access to one large memory address space

Example systems
• - Bus and cache-based systems: Sequent Balance, Encore Multimax
• - Multistage IN-based systems: Ultracomputer, Butterfly, RP3, HEP
• - Crossbar switch-based systems: C.mmp, Alliant FX/8

Limitations
• Memory access latency; Hot spot problem

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 MESSAGE-PASSING MULTIPROCESSORS
• Characteristics
• - Interconnected computers
• - Each processor has its own memory, and
• communicate via message-passing

• Example systems
• - Tree structure: Teradata, DADO
• - Mesh-connected: Rediflow, Series 2010, J-Machine
• - Hypercube: Cosmic Cube, iPSC, NCUBE, FPS T Series, Mark III

• Limitations
• - Communication overhead; Hard to programming

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 INTERCONNECTION STRUCTURES
• Time-Shared Common Bus

• Multiport Memory

• Crossbar Switch

• Multistage Switching Network

• Hypercube System

• Bus

• -All processors (and memory) are connected to a common bus or busses

• - Memory access is fairly uniform, but not very scalable

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 BUS
• A collection of signal lines that carry module-to-module communication
• Data highways connecting several digital system elements
• M3 wishes to communicate with S5

• [1] M3 sends signals (address) on the bus that causes

• Master Device: Device that initiates and controls the communication

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 MULTIPORT MEMORY
• Multiport Memory Module
• Each port serves a CPU
• Memory Module Control Logic
• Each memory module has control logic
• Resolve memory module conflicts Fixed priority
among CPUs
Advantages
• Multiple paths -> high transfer rate
Disadvantages
• Memory control logic
• Large number of cables and
connections

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CROSSBAR SWITCH

MM1 MM2 MM3 MM4

CPU1

CPU2

CPU3

CPU4

SOURCE: www.lecturenotes.in/coa/ranusingh.php 10
 MULTISTAGE INTERCONNECTION
NETWORK
• 8x8 Omega Switching Network

0 000
1 001
2 010
3 011
4 100
5 101
6 110
7 111
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 HYPERCUBE INTERCONNECTION
• p = 2n
• processors are conceptually on the corners of a
• n-dimensional hypercube, and each is directly
• connected to the n neighboring nodes
111
• Degree = n
010
0 01 11 110

101
001

1 00 10 100
000

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 APPLICATIONS

• Computer organization and architecture course deals with instruction set architecture, micro architecture and efficient

implementation of micro architecture.

• Understanding the computer architecture concepts is essential for students interested in hardware, processor design,

compilers, and operating systems. 

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 REFERENCES
Reference Books:
1. J.P. Hayes, “Computer Architecture and Organization”, Third Edition.
2. Mano, M., “Computer System Architecture”, Third Edition, Prentice Hall.
3. Stallings, W., “Computer Organization and Architecture”, Eighth Edition, Pearson Education.
Text Books:
4. Carpinelli J.D,” Computer systems organization &Architecture”, Fourth Edition, Addison Wesley.
5. Patterson and Hennessy, “Computer Architecture” , Fifth Edition Morgaon Kauffman.
Reference Website
6. https://www.geeksforgeeks.org/computer-organization-and-architecture-tutorials/

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THANK YOU