DATA-FLOW MODELING

Features
• The designer can instantiate and connect every gate
individually for small circuits, using gate-level modeling.
• The designers can design more effectively if they
concentrate on implementing the function at a level of
abstraction higher than gate level, in complex designs
• Dataflow modeling provides a powerful way to implement
a design.
• Verilog allows a circuit to be designed in terms of the data
flow between registers and how a design processes data
rather than instantiation of individual gates.
• Data flow modeling can also be referred as RTL modeling
 Assignments
• The assignment is the basic mechanism in Data flow Modeling.
• This assignment is used for getting values into nets and registers.
• There are two basic forms of the assignment:
 Continuous assignment, which assigns values to nets
 Procedural assignment, which assigns values to registers
• An assignment consists of two parts, a left-hand side and a right-hand
side, separated by the equal (=) character.
• The right-hand side can be any expression that evaluates to a value.
• The left-hand side indicates the variable that the right-hand side is to be
assigned to.
• The left-hand side can take one of the following forms, depending on
whether the assignment is a continuous assignment or a procedural
assignment.
Legal left-hand side forms in assignment
statements
 Continuous Assignments
• Continuous assignments drive values onto nets, both
vector and scalar.
• The significance of the word “continuous” is that the
assignment occurs whenever simulation causes the
value of the right-hand side to change.
• Continuous assignments provide a way to model
combinational logic without specifying an
interconnection of gates.
• The expression on the right-hand side of the continuous
assignment is not restricted in any way.
 Continuous Assignment Statements
• The assignment statement starts with the keyword
assign.
• The syntax of an assign statement is as follows.
• <continuous_assign> ::= assign <drive_strength>?
<delay>? <list_of_assignments> ;
• Drive strength is optional and can be specified in
terms of strength levels.
• The delay value is also optional and can be used
to specify delay on the assign statement.
 Continuous Assignments Characteristics

1. The left-hand side of an assignment must always be a scalar

or vector net or a concatenation of scalar and vector nets. It
cannot be a scalar or vector register.
2. Continuous assignments are always active. The assignment
expression is evaluated as soon as one of the right-hand-side
operands changes and the value is assigned to the left-hand-
side net.
3. The operands on the right-hand side can be registers or nets
or function calls. Registers or nets can be scalars or vectors.
4. Delay values can be specified for assignments in terms of time
units. Delay values are used to control the time when a net is
assigned the evaluated value.
Example of Continuous Assignment
 Implicit Continuous Assignment
• Instead of declaring a net and then writing a
continuous assignment on the net, Verilog provides a
shortcut by which a continuous assignment can be
placed on a net when it is declared.
• There can be only one implicit declaration
assignment per net because a net is declared only
once.
 Implicit Net Declaration
• If a signal name is used to the left of the continuous
assignment, an implicit net declaration will be inferred
for that signal name.
• If the net is connected to a module port, the width of
the inferred net is equal to the width of the module
port.
• Example:
• wire i1, i2;
• assign out = i1 & i2;
• Note that out was not declared as a wire but an implicit
wire declaration for out is done by the simulator
 Delays in Dataflow modeling
• A delay given to a continuous assignment
specifies the time duration between a right-
hand side operand value change and the
assignment made to the left-hand side.
• If the left-hand side references a scalar net,
then the delay is treated in the same way as for
gate delays.
 Types of Delays
• Delay values control the time between the
change in a right-hand-side operand and when
the new value is assigned to the left-hand side.
• Three ways of specifying delays in continuous
assignment statements are
 Regular assignment delay
 Implicit continuous assignment delay
 Net declaration delay.
 Regular Assignment Delay
• This method is to assign a delay value in a continuous
assignment statement.
• Any change in values of inputs will result in a delay of
specified time units before recomputation of the
expression and the result will be assigned to output.
• If inputs change value again before specified time units
and when the result propagates to output, the values of
inputs at the time of recomputation are considered.
• This property is called inertial delay.
• An input pulse that is shorter than the delay of the
assignment statement does not propagate to the output.
 Regular Assignment Delay

• Examples
wire out;
assign #10 out = in1 & in2;
 Implicit Continuous Assignment Delay

• An implicit continuous assignment method is to use to specify

both delay and declaration in assignment on the net.

• The declaration has the same effect as defining a wire out and
declaring a continuous assignment on out.
 Net Declaration Delay
• A delay can be specified on a net when it is declared
without putting a continuous assignment on the net.
• If a delay is specified on a net out, then any value change
applied to the net out is delayed accordingly.
• Net declaration delays can also be used in gate-level
modeling.
Expressions, Operators, and Operands

• Expressions, Operators, and Operands form

the basis of dataflow modelling.
• Expressions:
 Expressions are constructs that combine operators
and operands to produce a result.
• Operands:
• Operands can be of any data type.
• Operands can be
 Constants
 Integers
 Real
 Numbers
 Nets
 Registers
 Time
 Bit-select
 Part select
 Memories
 Function calls
Operands
 Operators
• Operators:
• Operators act on the operands to produce
desired result.
• Verilog provide various types of operators.
 Operator Types
• Verilog provide many different operators types.
• Operators may be:
 Arithmetic
 Logical
 Relational
 Equality
 Bitwise
 Reduction
 Shift
 Concatenation
 Conditional
Operator Types
 Arithmetic Operators
• Two types:
1. Binary
2. Unary
Binary Operators:
1. Multiplication *
2. Division /
3. Addition +
4. Subtraction -
5. Modulus %
• Unary Operators: + -
 Logical Operators
• Logical AND (&&)
Binary
• Logical OR (||)
• Logical NOT (!)  Unary
• Conditions:
• Evaluate to a 1-bit value 0(false),1(true)or X(ambiguous).
• Operand not equal to zero, equivalent to logic 1(true).
• Operand equal to zero, equivalent to logic 0(false).
• Logical operators take variables or expressions as
operands.
 Relational Operators
• Greater than (>)
• Lesser than (<)
• Greater than or equal to (>=)
• Lesser than or equal to (<=)
 EQUALITY OPERATORS
• Logical equality (==)
• Logical inequality (!==)
• case equality (===)
• case inequality (!==)
 Bitwise Operators
• Negation (~)
• AND (&)
• OR (|)
• XOR (^)
• XNOR (^~,~^)
 Reduction Operators
• AND (&)
• NAND (~&)
• OR (|)
• NOR (~|)
• XOR (^)
• XNOR (~^)
 Shift Operators
• Right shift (>>)
• Left shift (<<)
•
 Concatenation Operators
• Concatenation operator ( {,} )
Replication Operator
Conditional Operator
Operator Precedence
4X2 Encoder
 Gate level program for 4 to 2 encoder

Module encoder4to2(x,y,d0,d1,d2,d3);
input d0,d1,d2,d3;
output x,y;
Or (x,d1,d3);
Or (y,d2,d3);
Endmodule
 Data Flow program for 4 to 2 encoder

Module encoder4to2(x,y,d0,d1,d2,d3);
input d0,d1,d2,d3;
output x,y;
Assign x=di+d3;
Assign y=d2+d3;
endmodule
 Test Bench
module encoder_tb();
reg d0,d1,d2,d3;
wire x,y;
encoder n1(x,y,d0,d1,d2,d3);
initial
begin
d0 = 1;d1 = 0;d2 = 0;d3 = 0;
#5 d0 = 0;d1 = 1;d2 = 0;d3 = 0;
#5 d0 = 0;d1 = 0;d2 = 1;d3 = 0;
#5 d0 = 0;d1 = 0;d2 = 0;d3 = 1;
#5 d0 = 0;d1 = 0;d2 = 0;d3 = 0;
#5 d0 = 0;d1 = 0;d2 = 0;d3 = 0;
#5 d0 = 0;d1 = 0;d2 = 0;d3 = 0;
#5 d0 = 0;d1 = 0;d2 = 0;d3 = 0;
end
endmodule
Priority Encoder
Priority Encoder
 Priority Encoder in Gate Level
Module priority_encoder(A0,A1,Y0,Y1,Y2,Y3);
input Y3, Y2, Y1, Y0;
output A0, A1;
wire y2bar; //not of y2
wire and_out; // and of y2bar and y1
not(y2bar, y2);
and(and_out, y2bar, y1);
or(A1, Y3, Y2);
or(A0, and_out, Y3);
endmodule
 Priority Encoder in Data Flow
Module priority_encoder(A0,A1,Y0,Y1,Y2,Y3);
input Y0,Y1,Y2,Y3;
output A0,A1;
assign A1 = Y3 + Y2;
assign A0 = Y3 + ((~Y2)&Y1);
endmodule
 Priority Encoder in Behavioral
module priority_encoderbehave(A, Y);
input [3:0]Y;
output reg [1:0]A;
always@(Y)
begin
casex(Y)
4'b0001:A = 2'b00;
4'b001x:A = 2'b01;
4'b01xx:A = 2'b10;
4'b1xxx:A = 2'b11;
default:$display("Error!");
endcase
end
endmodule
 TESTBENCH
module PriorityEncoder_Test;
reg [3:0] y;
wire [1:0] a;
priority_encoderbehave uut (.Y(y), .A(a));
initial
Begin
Y = 0;
#100;
#10 Y = 4'b0000;
#10 Y = 4'b1000;
#10 Y = 4'b0100;
#10 Y = 4'b0010;
#10 Y = 4'b0001;
#10 Y = 4'b1010;
10 Y = 4'b1111;
end
initial
begin
$monitor("time=",$time,, "D=%b : Y=%b V=%b",D,Y,V);
end
endmodule
Decoder
 2 to 4 Decoder in Gate Level
Module decoder(a,b,c,d0,d1,d2,d3);
input a,b,e;
output d0,d1,d2,d3;
Wire ao,bo;
Not (a0,a);
Not (b0,b);
And(d0,ao,bo,e);
And(d1,ao,b,e);
And(d2,a,bo,e);
And(d3,a,b,e);
End module
 2 to 4 Decoder in Data Flow
Module decoder(a,b,c,d0,d1,d2,d3);
input a,b,e;
output d0,d1,d2,d3;
Wire ao,bo;
assign d0=(~a&~b&e),
d1=(~a&b&e),
d2=(a&~b&e),
d3=(a&b&e);
endmodule
 Testbench for 2 to 4 Decoder
module decoder_tb();
reg a,b,e;
wire d0,d1,d2,d3;
Decoder n1(a,b,c,d0,d1,d2,d3);
initial
Begin
E=0;
#5 e=1;
a = 0;b = 0;
#10 a = 0;b = 1;
#10 a = 1;b = 0;
#10 a = 1;b = 1;
end
endmodule