Pabna University of Science &

Technology

FET
BIASING
Field-effect transistors biasing

T. H. M. Sumon Rashid
Assistant Professor, Dept. of
 FET
Biasing

J F E T Vs B J E T Fixed-Bias C o n f i g .
01 Construction, operation and
Transfer characteristics
02 MOSFET types, D-MOSFET
construction and operation

Self-Bias C o n f i g . D - M O S F E T Biasing
03 Construction, operation and Trnasfer
Curve
04 Constructions, advantages and
applications etc.

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 FET vs BJT Overview Lecture 13

BJT FET

The current flow is due to the flow of majority as The current flow is due to the flow of majority
well as minority charge carriers. charge carriers.
Current flow is due to both electrons and holes, The current flow is due to either electrons or holes,
therefore name bipolar transistor. therefore, named unipolar transistor.
It is a current-controlled current device. It is a voltage-controlled current device.

There are 2 PN junction in BJT. There are no PN junctions.

The BJT has very simple biasing. The FET biasing is a little difficult.

The input impedance is comparatively low in the The input impedance is very high in the range of
range of 𝑘 Ω. 100 𝑀Ω .

 The general relationships that can be applied to the dc

analysis of all FET amplifiers are
=𝐼
𝐼𝐺 ≅ 0 𝐴 and 𝐼𝐷
𝑆

[Prepared and Conducted by: T. H. M. Sumon Rashid, Assistant Professor, Dept. of EEE, Pabna University of Science and Technology]
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 Fixed-Bias Configuration Lecture 13

The resistor 𝑅𝐺 is present to ensure that 𝑉𝑖 appears at the

input to the FET amplifier for the ac analysis.

𝐼𝐺 ≅ 0 𝐴

and 𝑉𝑅𝐺 = 𝐼𝐺𝑅𝐺 =0𝐴

𝑅𝐺 replaced by a short circuit equivalent, Fig.13-2.

Fig.13-1:Fixed-bias config.
Applying KVL, −𝑉𝐺𝐺 − 𝑉𝐺𝑆 = 0 ⟹ 𝑉𝐺𝑆= −𝑉𝐺𝐺

Since, 𝑽𝑮𝑮 is fixed dc supply, the voltage 𝑉𝐺𝑆 is fixed,

resulting in the designation “fixed-bias configuration”.
The resulting level of 𝐼𝐷 is controlled by Shockley’s
equation:
𝑉𝐺𝑆 2
𝐼𝐷 = 𝐼 1−
𝐷𝑆𝑆
𝑉𝑃
Fig.13-2:Fixed-bias
configuration.

[Prepared and Conducted by: T. H. M. Sumon Rashid, Assistant Professor, Dept. of EEE, Pabna University of Science and Technology]
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 Fixed-Bias Configuration Lecture 13

Applying KVL to the output

section:
+𝑉𝐷𝑆 + 𝐼𝐷𝑅𝐷 − 𝑉𝐷𝐷 = 0

⟹ 𝑉𝐷𝑆 = 𝑉𝐷𝐷 − 𝐼𝐷𝑅𝐷

𝑉𝑆= 0 𝑉

𝑉𝐷𝑆 = 𝑉𝐷 − 𝑉𝑆
Fig.13-4: Finding Q-point Solution
Fig.13-3:Plotting Shockley’s equation ⟹ 𝑉𝐷 = 𝑉𝐷𝑆

 In Fig.13-4, the fixed level 𝑉𝐺𝑆 has been 𝑉𝐺𝑆 = 𝑉𝐺 − 𝑉𝑆

superimposed as a vertical line.
 The point where the two curves ⟹ 𝑉𝐺 = 𝑉𝐺𝑆
intersect is the
common solution to the configuration.
 Referred to as the quiescent or
operating point.
[Prepared and Conducted by: T. H. M. Sumon Rashid, Assistant Professor, Dept. of EEE, Pabna University of Science and Technology]
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 Fixed-Bias Configuration Lecture 13

Example 1: Determine the following for the network of Fig. 13-

5 Boylestad a. 𝑉𝐺 𝑆 𝑄 b. 𝐼𝐷 𝑄 c. 𝑉𝐷 𝑆 d. 𝑉𝐷 e. 𝑉𝐺 f.
𝑉𝑆
Solution:
Mathematical Approach

a. 𝑉𝐺𝑆𝑄 = −𝑉𝐺𝐺 =
−2 𝑉 2
𝑉𝐺𝑆
b. 𝐼 = 𝐼 1− = 5.625 𝑚𝐴
𝐷𝑄 𝐷𝐷𝑆 𝑉𝑃

c. 𝑉𝐷𝑆 = 𝑉𝐷𝐷 − 𝐼𝐷𝑅𝐷 e. 𝑉𝐺 = 𝑉𝐺𝑆 = −2 𝑉

d. 𝑉𝐷 = 𝑉𝐷𝑆 = 4.75 𝑉 f. 𝑉𝑆 = 0 𝑉 Fig.13-5: Example 1

[Prepared and Conducted by: T. H. M. Sumon Rashid, Assistant Professor, Dept. of EEE, Pabna University of Science and Technology]
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 Fixed-Bias Configuration Lecture 13

Graphical Approach
The resulting Shockley curve and the vertical line at 𝑉𝐺𝑆 = −2 𝑉
shown in Fig.13-6.

a. 𝑉𝐺𝑆𝑄 = −𝑉𝐺𝐺 = −2 𝑉

b. 𝐼𝐷𝑄 = 5.6 𝑚 𝐴

c. 𝑉𝐷𝑆 = 𝑉𝐷𝐷 − 𝐼𝐷𝑅𝐷 = 4.8 𝑉

d. 𝑉𝐷 = 𝑉𝐷𝑆 = 4.8 𝑉

e. 𝑉𝐺 = 𝑉𝐺𝑆 = −2 𝑉

f. 𝑉𝑆 = 0 𝑉
Fig.13-6: Graphical Solution
Result of both solutions are quite close.

[Prepared and Conducted by: T. H. M. Sumon Rashid, Assistant Professor, Dept. of EEE, Pabna University of Science and Technology]
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 Self-Bias Configuration Lecture 13

 Self-bias configuration require only one dc supplies.

 𝑉𝐺𝑆 now determined by the voltage across 𝑅𝑆

Since, 𝐼𝐺 = 0 𝐴, the network for dc analysis

can be redrawn as Fig.13-8.

The current through 𝑅𝑆 is 𝐼𝑆, but 𝐼𝑆 = 𝐼𝐷 and

𝑉𝑅𝑆 = 𝐼𝐷𝑅𝑆

Applying KVL to the closed loop,

−𝑉𝐺𝑆 − 𝑉𝑅𝑆 = 0 Fig.13-7: JFET self-bias
configuration.
𝑉𝐺𝑆 = −𝑉𝑅𝑆 = −𝐼𝐷𝑅𝑆

𝑽𝑮𝑺 is function of 𝑰𝑫 , and not fixed.

Fig.13-8 DC analysis Self-bias

[Prepared and Conducted by: T. H. M. Sumon Rashid, Assistant Professor, Dept. of EEE, Pabna University of Science and Technology]
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 Self-Bias Configuration Lecture 13

Graphical method is easier to find the Q-point solution.

We
can plot the transfer curve using Shockley's equation.
𝑉𝐺𝑆 = −𝐼𝐷𝑅𝑆 [Straight line]

At 𝐼𝐷 = 0 𝐴, 𝑉𝐺𝑆 = 0 𝑉
𝐼𝐷𝑆𝑆 𝑅𝑆
At 𝐼𝐷 = 𝐼 𝐷𝑆𝑆 , 𝑉𝐺𝑆 = −
2 2

Applying KVL to output section:

𝑉𝑅𝑆 + 𝑉𝐷𝑆 + 𝑉𝑅𝐷 − 𝑉𝐷𝐷 = 0

𝑉𝐷𝑆 = 𝑉𝐷𝐷 − 𝑉𝑅𝑆 − 𝑉𝑅𝐷 = 𝑉𝐷𝐷 − 𝐼𝑆𝑅𝑆 − 𝐼𝐷𝑅𝐷

but, 𝐼𝐷 = 𝐼𝑆 𝑉𝑆 = 𝐼𝐷𝑅𝑆
Fig.13-9: Sketching self-bias line
𝑉𝐺 = 0 𝑉
So, 𝑉 = 𝑉𝐷𝐷 − 𝐼𝐷 (𝑅𝑆 + 𝑅𝐷 )
𝐷𝑆 𝑉𝐷 = 𝑉𝐷𝑆 + 𝑉𝑆 = 𝑉𝐷𝐷 − 𝑉𝑅𝐷

[Prepared and Conducted by: T. H. M. Sumon Rashid, Assistant Professor, Dept. of EEE, Pabna University of Science and Technology]
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 Self-Bias Example Lecture 14

Example 2: Determine the following for the network of Fig. 14-

1.Boylestad a. 𝑉𝐺 𝑆 𝑄 b. 𝐼𝐷 𝑄 c. 𝑉𝐷 𝑆 d. 𝑉𝑆 e. 𝑉𝐺 f. 𝑉𝐷
h. Find quiescent point for 𝑹𝑺 = 𝟏𝟎𝟎 𝜴 and 𝟏𝟎 𝒌𝜴.
Solution:
a. 𝑉𝐺𝑆 = −𝐼𝐷𝑅𝑆

Choose, 𝐼𝐷 = 4 𝑚𝐴, 𝑉𝐺𝑆 = −4 𝑉

𝑉𝐺𝑆𝑄 = −2.6 𝑉 [From graph]

b.
𝐼𝐷𝑄 = 2.6 𝑚𝐴 [From graph]
Fig.14-1: Example 2
c.
𝑉𝐷𝑆 = 𝑉𝐷𝐷 − 𝐼𝐷(𝑅𝑆 + 𝑅 𝐷 ) = 8.82 𝑉
d. 𝑉𝑆= 𝐼𝐷𝑅𝑆 = 2.6 𝑉

e. 𝑉𝐺 = 0 𝑉

f. 𝑉𝐷 = 𝑉𝐷𝐷 − 𝐼𝐷𝑅𝐷 = 11.42 𝑉 Fig.14-2: Example 2

[Prepared and Conducted by: T. H. M. Sumon Rashid, Assistant Professor, Dept. of EEE, Pabna University of Science and Technology]
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 Self-Bias Example Lecture 14

Both 𝑅𝑆 = 100 Ω and 𝑅𝑆 = 10 𝑘Ω are plotted

on Fig.14-3.

For, 𝑅𝑆 = 100 Ω:

𝐼𝐷𝑄 = 6.4 𝑚𝐴

𝑉𝐺𝑆𝑄 = −𝐼𝐷𝑅𝑆 ≅ −0.64 𝑉

For, 𝑅𝑆 = 10 𝑘Ω:

𝑉𝐺𝑆𝑄 = −4.6 𝑉
𝐼𝐷𝑄 = − 𝑉𝐺𝑆𝑄 ≅ 0.46 𝑚𝐴
𝑅𝑆

Fig.14-3: Example 2

[Prepared and Conducted by: T. H. M. Sumon Rashid, Assistant Professor, Dept. of EEE, Pabna University of Science and Technology]
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 Voltage-divider Biasing Lecture 14

Fig.14-4: Voltage-divider bias config. (a) (b)

Fig.14-5: Redrawn for dc analysis

𝑉𝐺 = 𝑅2𝑉𝐷𝐷
Since, 𝐼𝐺 = 0 𝐴, 𝑅1 + 𝑅 2
Applying KVL to the closed loop,
So, 𝐼𝑅1 = 𝐼𝑅2
𝑉𝐺 − 𝑉𝐺𝑆 − 𝑉𝑅𝑆 = 0
And the series ⟹ 𝑉𝐺𝑆 = 𝑉𝐺 − 𝐼𝐷𝑅𝑆
equivalent 𝑉𝐺 𝑆 = 𝑉𝐺 − 𝑉
circuit shown if 𝑅𝑆
[Prepared and Conducted by: T. H. M. Sumon Rashid, Assistant Professor, Dept. of EEE, Pabna University of Science and Technology]
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 Voltage-divider Biasing Lecture 14

𝑉𝐺𝑆 = 𝑉𝐺 − 𝐼𝐷𝑅𝑆

𝑽𝑮 and 𝑹𝑺 are fixed and the equation above is

still a straight line equation.

If 𝐼𝐷 = 0 𝑚𝐴, 𝑉𝐺𝑆 = 𝑉𝐺
𝑉𝐺
If 𝑉𝐺 𝑆 = 0 𝑉, 𝐼𝐷 =
𝑅𝑆

𝑉𝐷𝑆 = 𝑉𝐷𝐷 − 𝐼𝐷(𝑅𝐷 + 𝑅𝑆) Fig.14-6: Sketching the network equation

𝑉𝐷 = 𝑉𝐷𝐷 − 𝐼𝐷𝑅𝐷

𝑉𝑆= 𝐼𝐷𝑅𝑆

Fig.14-7:Effect of 𝑅𝑆 on the resulting Q-point

[Prepared and Conducted by: T. H. M. Sumon Rashid, Assistant Professor, Dept. of EEE, Pabna University of Science and Technology]
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 D-MOSFET Biasing Lecture 14

 JFET and D-MOSFET have similar Transfer curve.

 Therefore, the analysis also similar.
 The only difference is, D-MOSFET permit operating point with
positive values of 𝑉𝐺𝑆 and level of 𝐼𝐷 exceed 𝐼𝐷𝑆𝑆.

Example 6: For n-channel depletion type MOSFET of Fig. 14-8,

Boylestad determine:
a. 𝐼𝐷 𝑄 and 𝑉𝐺 𝑆 𝑄 b.
𝑉𝐷 𝑆

Solution:
a. At, 𝐼𝐷 Transfer curve: 𝑉 = 0.5 V = −1.5 V Fig.14-8: Example 6
= 𝐼 𝐷4 𝑆 𝑆 = 1.5 𝐺𝑆 P
𝑚𝐴, 2
For D-MOSFET, For positive value 𝑉𝐺 𝑆
𝐼𝐷 = 𝐼 1−
of 𝑉𝐺𝑆 , 𝐼 increases
𝐷 rapidly. 𝐷𝑆𝑆 𝑉𝑃
define
So, only for 𝑉𝐺𝑆 = +1 𝑉
= 10.67 𝑚𝐴

[Prepared and Conducted by: T. H. M. Sumon Rashid, Assistant Professor, Dept. of EEE, Pabna University of Science and Technology]
14
 D-MOSFET Biasing Lecture 14

Proceeding as JEFTs, we have

𝑅2 𝑉𝐷𝐷
𝑉𝐺 = = 1.5 𝑉
𝑅1 + 𝑅2

𝑉𝐺𝑆 = 𝑉𝐺 − 𝐼𝐷𝑅𝑆 = 1.5 𝑉 − 𝐼𝐷 (750Ω)

Setting, 𝐼𝐷 = 0 𝑚𝐴, 𝑉𝐺𝑆 =𝑉𝑉𝐺𝐺 = 1.5 𝑉

Setting, 𝑉𝐺𝑆 = 0 𝑉, 𝐷 = =2
𝑅
𝑚𝐴 𝑆
𝐼
Transfer curve and resulting bias line shown in Fig. 14-
9. The resulting operating point is given by

𝐼𝐷𝑄 = 3.1 𝑚𝐴

𝑉𝐺𝑆𝑄 = −0.8 𝑉

b. 𝑉𝐷𝑆 = 𝑉𝐷𝐷 − 𝐼𝐷(𝑅𝐷 + 𝑅𝑆) = 10.1 𝑉 Fig.14-9: Determining Q-point

[Prepared and Conducted by: T. H. M. Sumon Rashid, Assistant Professor, Dept. of EEE, Pabna University of Science and Technology]
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 THANKS
Do you have any questions?

CREDITS:
T. H. M. Sumon Rashid
Assistant Professor, Dept. of EEE
Pabna University of Science & Technology