Verilog HDL

18EC56

Dinesh M.A.
[email protected]
•
/dinesh.ajay
/prof.dineshma
 Verilog HDL(18EC56)

• Verilog HDL is the study of an hardware description

language that is used to describe electronic circuits, in
particular digital circuits, using different abstraction levels.
• The major focus is to expose students to the design process
of combinational and sequential logic design using Verilog
HDL.
• This course describes the basic concepts, modelling styles
in Verilog.

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 Why HDL?
Evolution of Logic Design

• Early days
• 10s of logic gates

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Verilog HDL
 Evolution of Logic Design (cont’d)

 A decade later
100s of logic gates
Schematic design

 Another decade later

1000s of logic gates
Structural Hardware Description Languages (HDL)

 State of the art

10,000s-1000,000s-10,000,000s logic gates
Behavioral and Register Transfer Level HDL
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 Evolution of Logic Design (cont’d)
HDL-based Design

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 Why HDLs?

• SSI (Small Scale Integration)

• MSI (Medium Scale Integration)
• LSI (Large Scale Integration)
• VLSI (Very Large Scale Integration)

• Important concepts
• Simulation = check if design works fine
• Synthesis = implement the design on real hardware
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 Popular Levels of Abstraction

Behavioral

Data flow

problem
Structural

Switch

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Popular Levels of Abstraction (cont’d)

Behavioral

Data flow

problem
Structural

Switch

Verilog HDL 03/06/2023 8

Popular Levels of Abstraction (cont’d)

Behavioral

Data flow

problem
Structural

Switch

Verilog HDL 03/06/2023 9

Popular Levels of Abstraction (cont’d)

Behavioral

Data flow

problem
Structural

Switch

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 HDL Examples

 AHDL
 Altera HDL
CDL: Computer Description Language
 1965
ISPS: Instruction Set Processor Specification
AHPL: A Hardware Programming Language
Abel
 Small designs such as state machines

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 VHDL
 VHSIC HDL: Very High Speed Integrated Circuit Hardware Description Language
 DARPA workshop on VHSIC in 1981
 DARPA released requirement in 1983
 A language for hardware documentation
 VHDL 7.2 in 1985
 IEEE standard in 1987
 ANSI standard in 1988
 For RTL design VITAL added,
 VITAL(VHDL Initiative Towards ASIC Library)
 IEEE revised VHDL & VITAL in 1993
 Final review of standard in 2001
 Very general, but verbose

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 Verilog HDL
 Verifying Logic
 Phil Moorby from Gateway Design Automation in 1984 to 1987 (absorbed
by Cadence)
 Verilog-XL Simulator from GDA in 1986
 Synopsys synthesis tool in 1988
 In 1990 became open language, OVI (Open Verilog International)
 IEEE standard 1995
 Similar to C
 Fairly efficient and easy to write

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 Hello World!
VHDL vs. Verilog
• VHDL • Verilog
------------------------------------------ //-----------------------------------------------------
-- Design Name : hello_world // This is my first Verilog Program
----------------------------------------- // Design Name : hello_world
entity hello_world is // File Name : hello_world.v
end;
// Function : This program will print 'hello world‘
architecture hello_world of hello_world is
// Coder : Deepak
begin
//-----------------------------------------------------
stimulus : process
module hello_world ;
begin
initial begin
assert false report "Hello World By Deepak“
$display ("Hello World by Deepak");
severity note;
#10 $finish;
wait;
end process stimulus; end

end hello_world; endmodule // End of Module hello_world

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 Course Learning Objectives#

This course will enable students to:

• Learn different Verilog HDL constructs.
• Familiarize the different levels of abstraction in Verilog.
• Understand Verilog Tasks, Functions and Directives.
• Understand timing and delay Simulation.
• Understand the concept of logic synthesis and its impact in verification

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 Module – 1 RBT
Level
Overview of Digital Design with Verilog HDL: Evolution of CAD, emergence of HDLs,
typical HDL-flow, why Verilog HDL?, trends in HDLs. L1, L2,
Hierarchical Modeling Concepts: Top-down and bottom-up design methodology, differences L3
between modules and module instances, parts of a simulation, design block, stimulus block.
Module – 2
Basic Concepts: Lexical conventions, data types, system tasks, compiler directives. L1, L2,
Modules and Ports: Module definition, port declaration, connecting ports, hierarchical name L3
referencing.
Module -3
Gate-Level Modeling: Modeling using basic Verilog gate primitives, description of and/or and
buf/not type gates, rise, fall and turn-off delays, min, max, and typical delays. L1, L2,
Dataflow Modeling: Continuous assignments, delay specification, expressions, operators, L3
operands, operator types.

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 RBT
Module -4 Level
Behavioral Modeling: Structured procedures, initial and always, blocking and non-blocking
statements, delay control, generate statement, event control, conditional statements,
Multiway branching, loops, sequential and parallel blocks. L1, L2,
Tasks and Functions: Differences between tasks and functions, declaration, invocation, L3
automatic
tasks and functions.
Module -5

Useful Modeling Techniques: Procedural continuous assignments, overriding parameters,

conditional compilation and execution, useful system tasks.
Logic Synthesis with Verilog: Logic Synthesis, Impact of logic synthesis, Verilog HDL L1, L2,
Synthesis, Synthesis design flow, Verification of Gate-Level Netlist. (Chapter 14 till 14.5 of L3
Text).

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 CO’s DESCRIPTION OF THE OUTCOMES

Present the comprehension of the IC Design flow, syntax, lexical

18EC56.1 conventions, data types, system tasks compiler directives and logic
synthesis in Verilog HDL.
Develop Verilog modules for digital circuits using gate level and
18EC56.2 data flow modeling, behavioral modeling using different control
structures and related statements and for system tasks as well.
Analyze the behavior of structural, dataflow and behavior modeling
18EC56.3
procedures written in Verilog.
Design digital functional blocks for a given set of specifications
18EC56.4
using hierarchical modeling concepts in Verilog.

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 Text & References

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