VLSI Design

Spring 2023
 Chap 05
Power

Instructor: Muneeb Abrar

[email protected]
Outline
• Sequencing
• Sequencing Element Design
• Max and Min-Delay
• Clock Skew
• Time Borrowing
• Two-Phase Clocking

Sequential Circuits 3
Sequencing
• Combinational logic
• output depends on current inputs
• Sequential logic
• output depends on current and previous inputs
• Requires separating previous, current, future
• Called state or tokens
• Ex: FSM, pipeline clk clk clk clk

in out
CL CL CL

Finite State Machine Pipeline

Sequential Circuits 4
Sequencing Cont.
• If tokens moved through pipeline at constant speed, no sequencing
elements would be necessary
• Ex: fiber-optic cable
• Light pulses (tokens) are sent down cable
• Next pulse sent before first reaches end of cable
• No need for hardware to separate pulses
• But dispersion sets min time between pulses
• This is called wave pipelining in circuits
• In most circuits, dispersion is high
• Delay fast tokens so they don’t catch slow ones.
Sequential Circuits 5
Sequencing Overhead
• Use flip-flops to delay fast tokens so they move through exactly one
stage each cycle.
• Inevitably adds some delay to the slow tokens
• Makes circuit slower than just the logic delay
• Called sequencing overhead
• Some people call this clocking overhead
• But it applies to asynchronous circuits too
• Inevitable side effect of maintaining sequence

Sequential Circuits 6
Sequencing Elements
• Latch: Level sensitive
• a.k.a. transparent latch, D latch
• Flip-flop: edge triggered
• A.k.a. master-slave flip-flop, D flip-flop, D register
• Timing Diagrams
• Transparent clk clk

• Opaque

Latch

Flop
D Q D Q

• Edge-trigger
clk

Q (latch)

Q (flop)

Sequential Circuits 7
Latch Design
• Pass Transistor Latch 
• Pros
+ Tiny D Q
+ Low clock load
Used in 1970’s
• Cons
• Vt drop
• nonrestoring
• backdriving
• output noise sensitivity
• dynamic
• diffusion input

Sequential Circuits 8
Latch Design
• Transmission gate 

+ No Vt drop D Q
- Requires inverted clock


Sequential Circuits 9
Latch Design

• Inverting buffer X
D Q
+ Restoring
+ No backdriving 

+ Fixes either
• Output noise sensitivity D Q
• Or diffusion input

• Inverted output

Sequential Circuits 10
Latch Design
• Tristate feedback 

+ Static D
X
Q
• Backdriving risk 


• Static latches are now essential 

because of leakage

Sequential Circuits 11
Latch Design
• Buffered input 
X
+ Fixes diffusion input D Q

+ Noninverting 


Sequential Circuits 12
Latch Design
 Q
• Buffered output X
D
+ No backdriving




• Widely used in standard cells
+ Very robust (most important)
- Rather large
- Rather slow (1.5 – 2 FO4 delays)
- High clock loading

Sequential Circuits 13
Latch Design
Q
• Datapath latch 
X
+ smaller D

+ faster 


- unbuffered input


Sequential Circuits 14
Flip-Flop Design
• Flip-flop is built as pair of back-to-back latches
 
X
D Q

 

  Q

X
D Q
 
 

 

Sequential Circuits 15
Timing Diagrams
Contamination and
Propagation Delays
A tpd
Combinational
A Y
tpd Logic Prop. Delay Logic
Y tcd

tcd Logic Cont. Delay

clk clk tsetup
thold
tpcq Latch/Flop Clk->Q Prop. Delay

Flop
D Q D
tccq Latch/Flop Clk->Q Cont. Delay tpcq
Q tccq
tpdq Latch D->Q Prop. Delay

tcdq Latch D->Q Cont. Delay clk

clk
tccq
tsetup
tpcq
thold

tsetup Latch/Flop Setup Time

Latch
D Q D tpdq
tcdq

thold Latch/Flop Hold Time Q

Sequential Circuits 16
Max-Delay: Flip-Flops
t pd  Tc  tsetup  t pcq 
clk clk

     Q1 D2
Combinational Logic

F1

F2
sequencing overhead

Tc

tsetup
clk
tpcq

Q1 tpd

D2

Sequential Circuits 17
Min-Delay: Flip-Flops
clk

tcd  thold  tccq Q1

CL

F1
clk

D2

F2
clk

Q1 tccq tcd

D2 thold

Sequential Circuits 18
Clock Skew
• We have assumed zero clock skew
• Clocks really have uncertainty in arrival time
• Decreases maximum propagation delay
• Increases minimum contamination delay
• Decreases time borrowing

Sequential Circuits 19
Skew: Flip-Flops
clk clk

t pd  Tc   t pcq  tsetup  tskew 

Q1 D2
Combinational Logic

F1

F2
       Tc

sequencing overhead
clk
tpcq
tcd  thold  tccq  tskew tsetup
tskew

Q1 tpdq

D2

clk

Q1
CL

F1
clk

D2

F2
tskew

clk
thold

Q1 tccq

D2 tcd

Sequential Circuits 20
Clock Distribution
• On a small chip, the clock distribution network is just a wire
• And possibly an inverter for clkb
• On practical chips, the RC delay of the wire resistance and gate load is
very long
• Variations in this delay cause clock to get to different elements at different
times
• This is called clock skew
• Most chips use repeaters to buffer the clock and equalize the delay
• Reduces but doesn’t eliminate skew

21: Package, Power, and Clock 21

Example
• Skew comes from differences in gate and wire delay
• With right buffer sizing, clk1 and clk2 could ideally arrive at the same time.
• But power supply noise changes buffer delays
• clk2 and clk3 will always see RC skew

gclk
3 mm 3.1 mm 0.5 mm
clk1 clk3
clk2
1.3 pF
0.4 pF 0.4 pF

21: Package, Power, and Clock 22

Review: Skew Impact
clk clk

Q1 D2

• Ideally full cycle is

Combinational Logic

F1

F2
Tc

available for work clk

tpcq
tskew

• Skew adds sequencing

Q1 tpdq tsetup

D2

overhead clk

Q1

• Increases thold
CL

F1
pd T time
  t too
c t t 
pcq setup skew
       D2
clk

sequencing overhead

F2
tcd  thold  tccq  tskew tskew

clk
thold

Q1 tccq

D2 tcd

21: Package, Power, and Clock 23

Solutions
• Reduce clock skew
• Careful clock distribution network design
• Plenty of metal wiring resources
• Analyze clock skew
• Only budget actual, not worst case skews
• Local vs. global skew budgets
• Tolerate clock skew
• Choose circuit structures insensitive to skew

21: Package, Power, and Clock 24