CADENCE GENUS

© 2020 Renesas Design Vietnam Co., Ltd. All rights reserved. RENESAS CONFIDENTIAL
AGENDA
 PRACTICE WITH LAB 1

 PRACTICE WITH LAB 3

 SEARCH FOR MAXIMUM OPERATING FREQUENCY OF DESIGN & SUBMISSION DATA

© 2020 Renesas Design Vietnam Co., Ltd. All rights reserved. RENESAS CONFIDENTIAL Page 2
 LAB STRUCTURE

© 2020 Renesas Design Vietnam Co., Ltd. All rights reserved. RENESAS CONFIDENTIAL Page 3
LAB DIRECTORY STRUCTURE (1/2)
 To run the lab, it requires 4 below data
 RTL DESIGN (*.v)
 SYNTHESIS LIBRARY (*.lib)
 SYNTHESIS CONSTRAINT
 SAMPLE ENVIRONMENT
 Please copy Sample Environment Kit from Cadence to your each synthesis working folder
[rvc@localhost ~]$
cd /home/{group}??/vlsi/${Student_ID}/work/synthesis_env

[rvc@localhost synthesis_env]$
cp -rf /home/share_file/cadence/installs/Genus_CUI_RAK/ ./Genus_BoundFlasher

© 2020 Renesas Design Vietnam Co., Ltd. All rights reserved. RENESAS CONFIDENTIAL Page 4
LAB DIRECTORY STRUCTURE (2/2)
[rvc@localhost synthesis_env]$
ls Genus_BoundFlasher

① ③
②
②
③
④

© 2020 Renesas Design Vietnam Co., Ltd. All rights reserved. RENESAS CONFIDENTIAL Page 5
 LAB 1: BASIC GENUS FLOW

© 2020 Renesas Design Vietnam Co., Ltd. All rights reserved. RENESAS CONFIDENTIAL Page 6
LAB1: BASIC GENUS FLOW
 Step 1: Prepare your RTL and put to below path ./Genus_BoundFlasher/RTL/
 Step 2: Prepare constraints as below at
[rvc@localhost synthesis_env]$
vi ./Genus_BoundFlasher/constraints/bound_flasher_gate.sdc

# Set the current design Design Module Name bound_flasher_gate.sdc

current_design bound_flasher
Clock Port Name
create_clock -name "clk" -add -period 5.0 -waveform {0.0 2.5} [get_ports clk]

set_input_delay -clock [get_clocks clk] -add_delay 2.5 [get_ports flick] Inputs / Outputs
set_input_delay -clock [get_clocks clk] -add_delay 2.5 [get_ports rst_n]
set_output_delay -clock [get_clocks clk] -add_delay 2.5 [get_ports lamp ]

set_max_fanout 15.000 [current_design]

set_max_transition 1.2 [current_design]

© 2020 Renesas Design Vietnam Co., Ltd. All rights reserved. RENESAS CONFIDENTIAL Page 7
LAB1: BASIC GENUS FLOW
 Step 3: Modify environment a bit to map current design
[rvc@localhost synthesis_env]$
vi ./Genus_BoundFlasher/LAB1/run.tcl
##############################################################################
## Preset global variables and attributes
##############################################################################
. . .
set DESIGN bound_flasher Design Module Name
####################################################################
## Load Design
####################################################################
read_hdl "bound_flasher.v"
elaborate $DESIGN RTL File Name
. . .
####################################################################
## Constraints Setup
####################################################################
read_sdc ../constraints/bound_flasher_gate.sdc
. . . Constraint File Name
#######################################################################################################
## Optimize Netlist
#######################################################################################################
. . .
write_hdl > ${_OUTPUTS_PATH}/${DESIGN}_m.v NETLIST File (Important)
#################################
### write_do_lec
#################################
quit Quit at end

© 2020 Renesas Design Vietnam Co., Ltd. All rights reserved. RENESAS CONFIDENTIAL Page 8
LAB1: BASIC GENUS FLOW
 Step 4: Source Genus & license files. Then, execute Synthesis
[rvc@localhost synthesis_env]$ cd /home/share_file/cadence
[rvc@localhost cadence]$ source add_path
[rvc@localhost cadence]$ source add_license
[rvc@localhost cadence]$ cd -
[rvc@localhost synthesis_env]$ cd ./LAB1/

[rvc@localhost LAB1]$ genus -f run.tcl | tee -i sync.log

 The following message will show in the Genus session when synthesis is done:

© 2020 Renesas Design Vietnam Co., Ltd. All rights reserved. RENESAS CONFIDENTIAL Page 9
LAB1: BASIC GENUS FLOW
 Step 5: Check synthesis Log file to confirm no “Error” occur
[rvc@localhost LAB1]$ vi sync.log

OK NG

 If it occurs “Error”, you need to resolved all Error before go to next step.

© 2020 Renesas Design Vietnam Co., Ltd. All rights reserved. RENESAS CONFIDENTIAL Page 10
LAB1: BASIC GENUS FLOW
 Step 6: Check Synthesis Report
[rvc@localhost synthesis_env]$ cd ./LAB1/
[rvc@localhost LAB1]$ vi reports??/final_area.rpt //Check Design Area

[rvc@localhost LAB1]$ vi reports??/final_qor.rpt //Check QoR Information

[rvc@localhost LAB1]$ vi reports??/final_time.rpt //Check Detail Timing Path

Critical Path Slack (CPS)(unit:ps) >= 0 proves QUALIFIED NETLIST

OK NG

© 2020 Renesas Design Vietnam Co., Ltd. All rights reserved. RENESAS CONFIDENTIAL Page 11
LAB1: BASIC GENUS FLOW
 Step 7: Prepare script to load NETLIST
[rvc@localhost LAB1]$ vi gui.tcl //Create new file

Design Module Name

set DESIGN bound_flasher gui.tcl
###############################################################
## Library setup
###############################################################
read_libs "../LIB/slow.lib ../LIB/pll.lib ../LIB/CDK_S128x16.lib ../LIB/CDK_S256x16.lib ../LIB/CDK_R512x16.lib "

read_physical -lef " ../LEF/gsclib045_tech.lef ../LEF/gsclib045_macro.lef ../LEF/pll.lef ../LEF/CDK_S128x16.lef

../LEF/CDK_S256x16.lef ../LEF/CDK_R512x16.lef "

####################################################################
## Load Design
####################################################################
read_hdl "./outputs/bound_flasher_m.v"

elaborate $DESIGN

Suppose that NETLIST is stored at

LAB1/outputs/bound_flasher_m.v

© 2020 Renesas Design Vietnam Co., Ltd. All rights reserved. RENESAS CONFIDENTIAL Page 12
LAB1: BASIC GENUS FLOW
 Step 8: Invoke NETLIST Schematic Window
[rvc@localhost LAB1]$ genus -f gui.tcl -gui //Open Genus GUI and load NETLIST

Righ Click

© 2020 Renesas Design Vietnam Co., Ltd. All rights reserved. RENESAS CONFIDENTIAL Page 13
 LAB 3: LOW-POWER SYNTHESIS

© 2020 Renesas Design Vietnam Co., Ltd. All rights reserved. RENESAS CONFIDENTIAL Page 14
LAB3: RUNNING LOW-POWER SYNTHESIS
Clock Port Name

 Step 1: Prepare your RTL and put to below path ./Genus_BoundFlasher/RTL/ Design Module Name
Inputs / Outputs
 Step 2: Prepare constraints as below at
[rvc@localhost synthesis_env]$
vi ./Genus_BoundFlasher/constraints/bound_flasher_gate.sdc bound_flasher_gate.sdc
# Set the current design
current_design bound_flasher

create_clock -name "clk" -add -period 5.0 -waveform {0.0 2.5} [get_ports clk]

set_input_delay -clock [get_clocks clk] -add_delay 2.5 [get_ports flick]

set_input_delay -clock [get_clocks clk] -add_delay 2.5 [get_ports rst_n]
set_output_delay -clock [get_clocks clk] -add_delay 2.5 [get_ports lamp ]

set_max_fanout 15.000 [current_design]

set_max_transition 1.2 [current_design]

© 2020 Renesas Design Vietnam Co., Ltd. All rights reserved. RENESAS CONFIDENTIAL Page 15
LAB3: RUNNING LOW-POWER SYNTHESIS
 Step 3: Modify environment a bit to map current design
[rvc@localhost synthesis_env]$
vi ./Genus_BoundFlasher/LAB3/run.tcl
##############################################################################
## Preset global variables and attributes
##############################################################################
. . .
set DESIGN bound_flasher Design Module Name
####################################################################
## Load Design
####################################################################
read_hdl "bound_flasher.v"
elaborate $DESIGN RTL File Name
. . .
####################################################################
## Constraints Setup
####################################################################
read_sdc ../constraints/bound_flasher_gate.sdc
. . . Constraint File Name
#######################################################################################################
## Optimize Netlist
#######################################################################################################
. . .
write_hdl > ${_OUTPUTS_PATH}/${DESIGN}_m.v NETLIST File (Important)
#################################
### write_do_lec
#################################
quit Quit at end

© 2020 Renesas Design Vietnam Co., Ltd. All rights reserved. RENESAS CONFIDENTIAL Page 16
LAB3: RUNNING LOW-POWER SYNTHESIS
 Step 4: Setting Power Optimization Attributes
Low-power synthesis is included as part of the synthesis process.
###############################################################
## Library setup
###############################################################
set_db / .lp_insert_clock_gating true
Enable Clock-Gating features. It must be enable before ELABORATE command

set_db / .leakage_power_effort medium

Set the leakage power optimization effort

#######################################################################################
## Leakage/Dynamic power/Clock Gating setup.
#######################################################################################
#set_db "design:$DESIGN" .lp_clock_gating_cell [vfind /lib* -lib_cell <cg_libcell_name>]
set_db "design:$DESIGN" .max_leakage_power 0.0
set_db "design:$DESIGN" .lp_power_optimization_weight 0.5 ;#<value from 0 to 1>
set_db "design:$DESIGN" .max_dynamic_power 100 Specify the optimization weight for dynamic power versus leakage power.

Set the maximum dynamic power attribute

© 2020 Renesas Design Vietnam Co., Ltd. All rights reserved. RENESAS CONFIDENTIAL Page 17
LAB3: RUNNING LOW-POWER SYNTHESIS
 Step 5: Source Genus & license files. Then, execute Synthesis
[rvc@localhost synthesis_env]$ cd /home/share_file/cadence
[rvc@localhost cadence]$ source add_path
[rvc@localhost cadence]$ source add_license
[rvc@localhost cadence]$ cd -
[rvc@localhost synthesis_env]$ cd ./LAB3/

[rvc@localhost LAB3]$ genus -f run.tcl | tee -i sync.log

 The following message will show in the Genus session when synthesis is done:

© 2020 Renesas Design Vietnam Co., Ltd. All rights reserved. RENESAS CONFIDENTIAL Page 18
LAB3: RUNNING LOW-POWER SYNTHESIS
 Step 6: Check synthesis Log file to confirm no “Error” occur
[rvc@localhost LAB3]$ vi sync.log

OK NG

 If it occurs “Error”, you need to resolved all Error before go to next step.

© 2020 Renesas Design Vietnam Co., Ltd. All rights reserved. RENESAS CONFIDENTIAL Page 19
LAB3: RUNNING LOW-POWER SYNTHESIS
 Step 7: Check Synthesis Report (AS LAB 1)
[rvc@localhost synthesis_env]$ cd ./LAB3/
[rvc@localhost LAB3]$ vi reports??/final_area.rpt //Check Design Area

[rvc@localhost LAB3]$ vi reports??/final_qor.rpt //Check QoR Information

[rvc@localhost LAB3]$ vi reports??/final_time.rpt //Check Detail Timing Path

Critical Path Slack (CPS)(unit:ps) >= 0 proves QUALIFIED NETLIST

OK NG

© 2020 Renesas Design Vietnam Co., Ltd. All rights reserved. RENESAS CONFIDENTIAL Page 20
LAB3: RUNNING LOW-POWER SYNTHESIS
 Step 8: Prepare script to load NETLIST
[rvc@localhost LAB3]$ vi gui.tcl //Create new file

Design Module Name

set DESIGN bound_flasher gui.tcl
###############################################################
## Library setup
###############################################################
read_libs "../LIB/slow.lib ../LIB/pll.lib ../LIB/CDK_S128x16.lib ../LIB/CDK_S256x16.lib ../LIB/CDK_R512x16.lib "

read_physical -lef " ../LEF/gsclib045_tech.lef ../LEF/gsclib045_macro.lef ../LEF/pll.lef ../LEF/CDK_S128x16.lef

../LEF/CDK_S256x16.lef ../LEF/CDK_R512x16.lef "

####################################################################
## Load Design
####################################################################
read_hdl "./outputs/bound_flasher_m.v"

elaborate $DESIGN

Suppose that NETLIST is stored at

LAB3/outputs/bound_flasher_m.v

© 2020 Renesas Design Vietnam Co., Ltd. All rights reserved. RENESAS CONFIDENTIAL Page 21
LAB3: RUNNING LOW-POWER SYNTHESIS
 Step 9: Invoke NETLIST Schematic Window
[rvc@localhost LAB3]$ genus -f gui.tcl -gui //Open Genus GUI and load NETLIST

Righ Click

© 2020 Renesas Design Vietnam Co., Ltd. All rights reserved. RENESAS CONFIDENTIAL Page 22
 SEARCH MAXIMUM DESIGN FREQUENCY &
SUBMISSION DATA

© 2020 Renesas Design Vietnam Co., Ltd. All rights reserved. RENESAS CONFIDENTIAL Page 23
SEARCH MAXIMUM DESIGN FREQUENCY
 Please re-use LAB1 and change Design Frequency until MAX while Critical Path Slave >= 0
 Change Design Constraints and re-run Synthesis as LAB1
[rvc@localhost synthesis_env]$
vi ./Genus_BoundFlasher/constraints/bound_flasher_gate.sdc

Change Design Change so that

# Set the current design Clock Period Duty Cycle = bound_flasher_gate.sdc
current_design bound_flasher (ns) 50%

create_clock -name "clk" -add -period 5.0 -waveform {0.0 2.5} [get_ports clk]

set_input_delay -clock [get_clocks clk] -add_delay 2.5 [get_ports flick] Inputs / Outputs
set_input_delay -clock [get_clocks clk] -add_delay 2.5 [get_ports rst_n]
set_output_delay -clock [get_clocks clk] -add_delay 2.5 [get_ports lamp ]

set_max_fanout 15.000 [current_design] Change so that

it is 50% of
set_max_transition 1.2 [current_design] Design Clock
Period (ns)

© 2020 Renesas Design Vietnam Co., Ltd. All rights reserved. RENESAS CONFIDENTIAL Page 24
 Click icon to add picture

© 2020 Renesas Design Vietnam Co., Ltd. All rights reserved. RENESAS CONFIDENTIAL
SUBMISSION DATA
 After re-synthesize with Maximum frequency, please submit below data:
(Note that LAB1 & LAB3 just for practice, no need to submit any data related to them)
 Netlist: outputs??/${DESIGN}_m.v (Ex: bound_flasher_m.v)
 Area report: reports??/final_area.rpt
 QoR report: reports??/final_qor.rpt
 Timing report: reports??/final_time.rpt

© 2020 Renesas Design Vietnam Co., Ltd. All rights reserved. RENESAS CONFIDENTIAL Page 26
 Renesas.com

© 2020 Renesas Design Vietnam Co., Ltd. All rights reserved. RENESAS CONFIDENTIAL