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DMC Abstract

This document presents a major project on using decimal matrix code (DMC) to enhance memory reliability against multiple cell upsets. DMC utilizes decimal algorithms to obtain maximum error detection capabilities with lower delay overhead compared to existing error correction codes. The methodology involves encoding data using the DMC, storing the encoded data in memory, and decoding during read operations to ensure reliable data retrieval. The objective is to improve fault tolerance against multiple bit errors through efficient detection and correction of errors caused by particle strikes that affect multiple memory cells simultaneously.

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Keerthi
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34 views11 pages

DMC Abstract

This document presents a major project on using decimal matrix code (DMC) to enhance memory reliability against multiple cell upsets. DMC utilizes decimal algorithms to obtain maximum error detection capabilities with lower delay overhead compared to existing error correction codes. The methodology involves encoding data using the DMC, storing the encoded data in memory, and decoding during read operations to ensure reliable data retrieval. The objective is to improve fault tolerance against multiple bit errors through efficient detection and correction of errors caused by particle strikes that affect multiple memory cells simultaneously.

Uploaded by

Keerthi
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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A

MAJOR PROJECT PRESENTATION ON


ENHANCED MEMORY RELIABILITY AGAINST MULTIPLE CELL
UPSETS USING DMC

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

Under the guidance of : Presented by:


Mrs. K.GOUTHAMI P.KEERTHI (19N01A0470)
Assistant Professor. M.VAISHNAVI (20N05A0412)
J.PRIYANKA (19N01A04B0)
U.VIVEKANANDA PATEL (19N01A0494)
CONTENTS:

• Abstract

• Introduction

• Literature review

• Existing system

• Objective

• Methodology

• References

Sree chaitanya college of engineering


1
ABSTRACT

• Transient multiple cell upsets (MCUs) are becoming major issues in the reliability of memories
exposed to radiation environment. To prevent MCUs from causing data corruption, more complex
error correction codes (ECCs) are widely used to protect memory, but the main problem is that
they would require higher delay overhead.

• Fault tolerant memory is designed with DMC.

• Decimal matrix code (DMC) based on divide-symbol is proposed to enhance memory reliability
with lower delay overhead. The proposed DMC utilizes decimal algorithm to obtain the maximum
error detection capability.

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INTRODUCTION

• Enhanced memory reliability against multiple cell upsets using decimal matrix code is a technique
used to improve the reliability of memory systems by mitigating the effects of multiple cell upsets.

• Multiple cell upsets refer to a phenomenon that can occur in memory systems where multiple
memory cells are affected by a single event, such as a cosmic ray or other high-energy particle.
These particles can cause a disturbance in the charge of memory cells, leading to errors in
the stored data.

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LITERATURE REVIEW

• "Fault-Tolerant Techniques for Digital Circuits" by Bhagat et al. (2016), discusses various fault-
tolerant techniques, including redundancy-based approaches and error-detection and correction
codes.

• "A Comprehensive Study of Error-Correcting Codes for NAND Flash Memory" by Liang et al.
(2017), which investigates the performance of different error-correcting codes (ECCs) for NAND
flash memory.

• "A Survey on Memory Errors, Their Mechanisms, and Error Correction Techniques" by Kang et
al. (2019), surveys various memory error mechanisms and error-correction techniques.

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EXISTING SYSTEM

1.Hamming distance

2. Punctured difference set (PDS)

3. Built-in current sensors (BICS)

4.Cyclic redundancy check(CRC)

5.Even parity / Odd parity

• Above codes require more area, power, and delay overheads since the encoding and decoding
circuits are more complex in these complicated codes.

• Error correction rate less than 50%.

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OBJECTIVE

• The objective of using decimal matrix code for enhanced memory reliability against multiple cell
upsets is to improve the fault tolerance of memory systems by detecting and correcting errors
caused by multiple bit flips, which are also known as multiple cell upsets (MCUs).

• Decimal matrix codes are a type of error-correcting code that can detect and correct multiple bit
errors in a memory system. They are based on the representation of data in a decimal format,
rather than binary, which allows for more efficient error correction

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METHODOLOGY

• The methodology for enhanced memory reliability against multiple cell upsets using decimal
matrix code involves encoding the data using a matrix code.

• The code that can detect and correct errors, storing the encoded data in the memory chip, and
decoding the data using the same matrix code during the read operation to ensure
reliable data retrieval.

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BLOCK DIAGRAM

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REFERENCES

• [1] D. Radaelli, H. Puchner, S. Wong, and S. Daniel, “Investigation of multi-bit upsets in a 150 nm
technology SRAM device,” IEEE Trans. Nucl. Sci., vol. 52, no. 6, pp. 2433–2437, Dec. 2005.

• [2] E. Ibe, H. Taniguchi, Y. Yahagi, K. Shimbo, and T. Toba, “Impact of scaling on neutron
induced soft error in SRAMs from an 250 nm to a 22 nm design rule,” IEEE Trans. Electron
Devices, vol. 57, no. 7, pp. 1527–1538, Jul. 2010.

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THANK YOU

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