Logic Equivalence

Check
Significance of LEC
Steps for LEC
 Loading guidance:
Guidance helps the formality to understand and process design changes made by various tools that are part of the design flow. Formality then
uses this list of information to assist in compare point matching and correctly setting up verification without user interference. Much information
is passed from the synthesis tool to the formality in the form of guidance like:
• Handles undriven signals like synthesis
• RTL interpretation like synthesis
• Auto-enable clock-gating and auto-disable scan
• Multibit flops information
 Loading the reference and implementation design:
User is required to load the reference design and the implementation design. Design can be loaded in (.v) or (.ddc) format, technological libs can
be loaded in the form of (libs), (db), and (ndm) formats.
 Performing setup:
It is the most important step in the LEC flow, most information needs to pass through the LEC tool before performing matching and verification.
Some of them are passed in the form of guidance. But the remaining information about the black box, scan connectivity, UPF related constraints,
and timing loop cut points is provided in the setup step.
 Matching compare points:
A compare point is defined as the design object that is used as a combinational logic endpoint while doing verification. Before design verification,
formality tries to match each primary output, black box input pin, sequential element, and qualified net in the implementation design with a
design object in the reference design from which it can compare.
 Verification:
During verification, formality allocates one of the five types of statuses for every compare point it figures through verification: Passing, Failing,
Aborted, Unverified, and Not Verified. Multiple reports are generated after the LEC completion like non-equivalence.rpt, failing_points.rpt,
black_box.rpt, SVF guidance rpts, unmatched_points.rpt, undriven_nets.rpt, multidriven_nets.rpt, and implementation_loops.rpt.
 Issues to be checked :

• Complete inputs information: The verification person must have all the input information used at the time of
the Synthesis.
• Setup files: The file needed to inform the tool about the design transformation or modification during
optimizations such as Removal of the unused Flip-Flops, ]Merging of the FFs, Register optimization, Datapath
optimization, FSM re-encoding
• Clock Gating: It used to reduced the dynamic power when circuit do not required to change their states
unnecessary. This is done by adding extra circuitry in the clock path, this added logic lead to a mismatch during
verification.
• Scan Flip-Flops: Scan flip-flops are inserted for the DFT process after replacing the flip-flops. These are used
by a design for manufacturing test. The extra logic in the path of data pin leads to logic cone match fail
• ECO Changes: ECO is done by manually modifying netlist with swaping cell, sizing cell or inserting buffers.
These modifications in the netlist which were done to improve timing may lead to alter the logic. Suppose you
have up-sized a cell to fix the setup time violation or inserted a buffer to fix hold time violation. LEC is done to
ensure these modifications has not effected your functionality.
Reports after LEC
• Non-equivalence report
• Unmapped report
• Blockbox report
• Abort.rpt
• Unreachable.rpt
• Floating.rpt
• Mapped.rpt