Multiprocessor System

Microcomputer Systems; The 8086/8088 family

Liu and Gibson
Chapter 11
 Why Multiprocessor System?
 Direct Memory Access (DMA) controller could improve the system
throughput by concurrently performing I/O as the CPU continued its
processing.
 This is possible because CPU does not utilize all of the bus cycles (8086
use only 50-80% of the available bus time).
 Capability of DMA controller is limited.
 Possible Solution:
 Complex components
 Multicore or multichip processor
 Multiprocessor
Why Multiprocessor System?
 Complex components:
 Limited data width
 Lacking of floating point arithmetic instruction
 Require many instruction to perform single floating point operation
 Multicore processor:
 Centralized
 Single point failure

Here comes Multiprocessor System

Multiprocessor System
Multiprocessor system is a type of parallel system in which two
or more processors work together to process more than one
program simultaneously. 
Advantages
 Reduced Cost: Multiple processors share the same
resources. Separate power supply or mother board for
each chip is not required. This reduces the cost.

 Increased Reliability: The reliability of system is also

increased. The failure of one processor does not affect the
other processors though it will slow down the machine.
Advantages (Contd…)
 Increased Throughput: An increase in the number of processes
completes the work in less time.
 Easy to add more processor as need arises.
 Task are divided among modules, so if any failure occurs, so it is
easier and cheaper to find and replace.
Multiprocessor Issues
 As more than one processor shares the system memory and I/O
devices through a common system bus, extra logic must be
included.
 Why……?
 To ensure that only one processor has access to the system bus
at a time.
Two problems in multiprocessor
• Bus contention

• Inter processor Communication

8086 & 8088
 Maximum mode of the 8086 and 8088 is specially designed to
implement multiprocessor systems.
 Multiprocessing features are provided in maximum mode to
accommodate three basic configurations.
Basic Configurations
Three basic configurations -
 Coprocessor Configuration
 Closely Coupled Configuration
 Loosely Coupled Configuration
Coprocessor Configuration

Introduction
Characteristics
Interaction between CPU & Coprocessor
Coprocessor configuration
• The configuration in which coprocessor is connected with the main
processor is called coprocessor configuration.
• Main processor and coprocessor work parallely in the system.
• For example, 8087 is a coprocessor for the 8086 processor
• 8087 coprocessor mainly used for numeric calculation.
• After calculation it supplies its result to the main processor .
• Then main processor work with the result supplied by the
coprocessor.
Coprocessor configuration
• 8086 and 8088 are powerful single-chip microprocessors.
• But, their instruction is not sufficient for some complex applications.
• For example, the 8086/8088 has no instructions for performing floating
point arithmetic.
• Coprocessor 8087 can help as a numeric data processor here.
• Hence, 8086/8088 are used as the dominant processors in
multiprocessing systems.
Characteristics
• Both the dominant processor and coprocessor uses same clock
generator.
• Main processor and the coprocessor shares the bus control logic.
• Dominant processor and coprocessor communicates with some specific
instructions.
Interaction between CPU & Coprocessor
• The host CPU fetch instructions, but coprocessor also receives all
instructions and monitor them.
• An instruction to be executed by the coprocessor is indicated when an
escape (ESC) instruction appears.
• This ESC instruction contains an external operation code.
• Both processor and coprocessor decodes it but coprocessor executes
the instruction.
Interaction between CPU & Coprocessor (Contd.)
• At this point, the host may simply go on the next instruction or it may
fetch the first word of a memory operand for the coprocessor and then
go on next instruction.
• While coprocessor executes an instruction, it sends a busy (high) signal
to host’s TEST pin.
• As the host continues processing instruction stream, the coprocessor
will perform operation indicated by the code in ESC instruction.
• If the host needs result of coprocessor it executes WAIT instruction and
stop parallel operation.
Interaction between CPU & Coprocessor (Contd.)
• The host has to wait until TEST pin of host is activated by coprocessor .
• The WAIT instruction repeatedly checks the test pin to check activation
status of host.
• When coprocessor completes its operation, it activates the TEST pin.
• When the TEST pin is activated. The host executes the next instruction
in sequence.
Synchronization between 8086 and its coprocessor
8086 Coprocessor
Wake up t
he coproc
ESC essor
Monitor
the 8086
or 8088
Execute the
8086
instructions Deactivate the
host’s TEST pin
& execute the
specified
WAIT operation.
Wake up
the 8086
or 8088
Activate
the TEST
pin
Closely Coupled Configuration
 Introduction
 Characteristics
 Interaction

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 Closely Coupled Configuration
1. The second configuration is Closely Coupled Configuration.
2. In this configuration, the 8086/8088 supports independent
processor, which unlike a coprocessor, executes its own
instruction stream.
3. Closely coupled multiprocessor system share the same
clock and bus control logic.
4. The independent processor access bus through the CPU’s
RQ/GT lines.
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Interaction
• Communication between the host and independent
processor is accomplished through shared memory
space
• Host sets up a message in memory
• Accesses shared memory to get the assigned task
• Executes the task in parallel with the host

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 Independent
8086/8088 Processor

Wait for
Set up messages request

Wake up independent
Fetch message
processor with an OUT
instruction

Perform assigned
Execute the 8086’s task
program sequence

Notify CPU of
Wait for ready or
completion
interrupt request

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Figure 11.6: Interprocessor Communication through shared memory
Interaction
• After the task is completed, the external processor
notifies its host using either a status bit or an interrupt
request.
• A message specify
- which operation is to be performed
- the input parameters
- the address of the location to store result.
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Loosely Coupled Configurations
Introduction, advantages &
bus allocations schemes

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Introduction
 In a loosely coupled multi processor system each CPU has
its own bus control logic and bus arbitration is resolved by
extending this logic and adding external logic that is common
to all master modules.

 Therefore several CPUs can form a very large system and

each CPU may have independent processors and/or a
coprocessor attached to it.

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Advantages
 High system throughput can be achieved by having more than
one CPU.
 A failure in one module normally does not cause a breakdown of
the entire system and the faulty module can be easily detected
and replaced.
 Each bus master may have a local bus to access dedicated
memory or I/O devices so that a greater degree of parallel
processing can be achieved.
 The system can be expanded in a modular from a bus master
module can be added or removed without affecting the other
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Bus arbitration problem
 Definition
 When more than one bus master module may have access to the
shared bus. This problem is called bus arbitration problem.

 Solution of bus arbitration problem

 By providing extra bus logic, this problem can be resolved. This
extra bus logic is called bus access logic.
 The responsibility of this logic is to ensure that only one bus
master at a time control the bus.

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Bus arbitration resolver schemes

Simultaneously, bus requests are resolved on a priority

basis. There are three schemes for establishing priority.

 Daisy Chaining
 Polling
 Independent requesting

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Daisy Chaining
 It is characterized by its simplicity & low cost.
 In daisy chain all masters use the same line for making
bus requests.
 To respond to a bus request signal the controller sends out
a bus grant signal if the bus busy signal is inactive.
 The grant signal serially propagates until it encounters the
first one that is requesting access to the bus.
 This module blocks the propagation of the bus grant signal,
activates the busy line , and gains control of the bus.
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Daisy chaining (contd...)

 Any other requesting module will not receive the grant

signal and the one located closest to the controller has the
highest priority.
 Comparing to other methods it requires less control line and
this number is independent of number of modules.
 But bus arbitration is slower due to propagation delay of
grant signal. This delay is proportional to the no of modules.
 The priority is fixed by its physical location so failure of one
module cause the whole system to fail.
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 master1 master2 master N

Bus Bus Bus

access access access
logic logic logic

Bus grant

Controller Bus request

Bus busy

Daisy chain method

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Advantages - Daisy Chaining
 It is simple.
 It is a low cost scheme.
 Require least number of control line.
 The number of control line is independent of the number of
module.

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Disadvantages - Daisy Chaining

 Arbitration time is slow due to the delay of bus grant line.

 This delay is proportional to the number of modules.
 Priority is fixed by its physical location as a result the failure
of a module causes the whole system fail.

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Polling Method
 The polling scheme uses a set of lines sufficient to address each
module .
 In response to bus request, the controller generates a sequence of
module addresses.
 When a requesting module recognizes its address , it activates the
busy line.
 The major advantages of polling is that the priority can be
changed dynamically by alternating the polling sequence stored in
the controller. 35
 master1 master2 master N

Bus Bus Bus

Module address access access access
logic logic logic

Controller Bus request

Bus busy

Polling method
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Advantages - Polling Method
 The priority can be dynamically change by altering the polling
sequence stored in the controller.
 If one module is failed the whole system will not fail.

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Independent Request Scheme
 The independent requests scheme resolves priority in a parallel
fashion .
 Each module has a separate pair of bus request and bus grant lines
and each pair has a priority assigned to it .
 The controller includes a priority decoder , which selects the request
with the highest priority and returns the corresponding bus grant
signal.
 Compared to the other methods the independent requests design is
fastest. It requires more bus request and grant lines.

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 master1 master2 master N

Bus Bus Bus

access access access
logic logic logic
Bus grant 1

Bus request 1
Controller
Bus grant 2

Bus request 2

Bus grant N

Bus request N

Bus busy

Independent Request Scheme 39

Independent Request Scheme
 Advantages
Design fastest

 Disadvantages
More bus requests and grants line

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Module

Module contains:
1. Host (8086 or 8088)
2. Bus arbiter (8289)
3. Bus controller (8288)
4. Latches (8283 ) X 3
5. Transceivers (8287) X 2
Host (8086 or 8088)
• Lacks the capability of requesting bus access and recognizing bus
grants.
• So it is necessary for each module containing a bus master to have
extra logic for sending and receiving bus access logic.
• Here comes bus arbiter (Intel 8289).
Bus arbiter (Intel 8289)

• Specially designed to provide necessary bus access handshaking.

Thank You