Peripherals Devices in

Computer Organization
Unit-VI
• A Peripheral Device is defined as the device which
provides input/output functions for a computer and serves as an
auxiliary computer device without computing-intensive functionality.
• Generally peripheral devices, however, are not essential for the
computer to perform its basic tasks, they can be thought of as an
enhancement to the user’s experience. A peripheral device is a device
that is connected to a computer system but is not part of the core
computer system architecture. Generally, more people use the term
peripheral more loosely to refer to a device external to the computer
case.
• Classification of Peripheral devices:
It is generally classified into 3 basic categories which are given below:
1.Input Devices:
The input devices is defined as it converts incoming data and instructions
into a pattern of electrical signals in binary code that are comprehensible to a
digital computer.
Example:
Keyboard, Mouse, Scanner, Microphone etc.
Output Devices:
An output device is generally reverse of the input process and generally
translating the digitized signals into a form intelligible to the user. The output
device is also performed for sending data from one computer system to
another. For some time punched-card and paper-tape readers were extensively
used for input, but these have now been supplanted by more efficient devices.
Example:
Monitors, headphones, printers etc
• Input/Output peripherals:
Input/output peripherals are the means by which the user and the
computer communicate with each other. A computer is very little
use unless it has at least one input peripheral and one output
peripheral. The input device is needed so that the user can tell the
machine what he wants it to do, and to enter data. The output device
reports the results to the user.
• Advantage of Peripherals Devices:
Peripherals devices provides more feature due to this operation of the
system is easy. These are given below:
• It is helpful for taking input very easily.
• It is also provided a specific output.
• It has a storage device for storing information or data
• It also improves the efficiency of the system.
I/O mapped I/O and Memory Mapped I/O
• Basically this are two different techniques to interface devices,
interfacing devices means connecting devices with processor now this
devices can be either I/O devices or can be memory devices. Depending
upon technique you can use I/O mapped I/O and Memory Mapped I/O.
• 1. Memory-Mapped I/O Interfacing :
In this kind of interfacing, we assign a memory address that can be used
in the same manner as we use a normal memory location.
• 2. I/O Mapped I/O Interfacing :
A kind of interfacing in which we assign an 8-bit address value to the
input/output devices which can be accessed using IN and OUT
instruction is called I/O Mapped I/O Interfacing.
Features Memory Mapped IO IO Mapped IO

IO devices are accessed like any other memory They cannot be accessed like any other
Addressing
location. memory location.

Address Size They are assigned with 16-bit address values. They are assigned with 8-bit address values.

Instructions Used The instruction used are LDA and STA, etc. The instruction used are IN and OUT.

Cycles involved during operation are Memory Cycles involved during operation are IO read
Cycles
Read, Memory Write. and IO writes in the case of IO Mapped IO.

Registers Communicating Any register can communicate with the IO Only Accumulator can communicate with IO
device in case of Memory Mapped IO. devices in case of IO Mapped IO.

216 IO ports are possible to be used for Only 256 I/O ports are available for interfacing
Space Involved interfacing in case of Memory Mapped IO. in case of IO Mapped IO.

IO/M` signal During writing or read cycles (IO/M` = 0 ) in During writing or read cycles (IO/M` = 1) in
case of Memory Mapped IO. case of IO Mapped IO.

No separate control signal required since we

Control Signal have unified memory space in the case of Special control signals are used in the case of
IO Mapped IO.
Memory Mapped IO.

Arithmetic and logical operations are Arithmetic and logical operations cannot be
Arithmetic and Logical operations performed directly on the data in the case of performed directly on the data in the case of
Memory Mapped IO. IO Mapped IO.
Memory-Mapped I/O

• When I/O devices and the memory share the same address space, the
arrangement is called memory-mapped I/O.

• Any machine instruction that can access memory can be used to transfer
data to or from an I/O device.

Move DATAIN, R0

Move R0, DATAOUT

Some processors have special In and Out instructions to perform I/O

transfer.
I/O Mapped I/O:
• We give an Input-Output address to an Input-Output device
• Only IN and OUT instructions are accessed by such devices
• The ALU operations are not directly applicable to such Input-Output data.
• I/O is any general-purpose port used by processor/controller to handle
peripherals connected to it.
• I/O mapped I/Os have a separate address space from the memory. So, total
addressed capacity is the number of I/Os connected and a memory
connected. Separate I/O-related instructions are used to access I/Os. A
separate signal is used for addressing an I/O device.
• Memory-mapped I/Os share the memory space with external memory. So,
total addressed capacity is memory connected only. This is under utilisation
of resources if your processor supports I/O-mapped I/O. In this case,
instructions used to access I/Os are the same as that used for memory.
Program-Controlled I/O

I/O devices operate at speeds that are very much different from that of
the processor.

Keyboard, for example, is very slow.

It needs to make sure that only after a character is available in the input
buffer of the keyboard interface; also, this character must be read only
once.
• Three Major Mechanisms

• Program-controlled I/O – processor polls the device.

• Interrupt

• Direct Memory Access (DMA)

DMA
• It is an approach used to transfer blocks of data directly between the main memory  and I/O devices,
such as disks 
• Operation of a disk drive is controlled by a disk controller circuit, which also  provides an interface
between the disk drive and the rest of the computer system • A special control unit called DMA
controller is provided to manage the transfer,  without continuous intervention by the processor. 
• DMA controller may be part of the disk controller (I/O device interface), or it may  be a separate unit
shared by a number of I/O devices.  
• The DMA controller performs the functions that would normally be carried out by  the processor when
accessing the main memory.  
• For each word transferred, it provides the memory address and generates all the  control signals
needed.  
• It increments the memory address for successive words and keeps track of the  number of
transfers.
DMA Procedure

Processor sends the starting address, the number of data, and the direction of transfer to
DMA controller.

Processor suspends the application program requesting DMA, starts DMA transfer, and
starts
another program.

After the DMA transfer is done, DMA controller sends an interrupt signal to the processor.

The processor puts the suspended program in the Runnable state.

Typical registers in a DMA controller
• The OS initiates the transfers by issuing Read / Write requests, which entail loading the controller’s
registers with the necessary addressing and control information. 
• Typically, this information includes: 
• Main memory address -The address of the  first main memory location of the block 
• Word count—The number of words in the block to be transferred. 
• Disk address— starting location on the disk(track and sector number) where read/write operation is to
take place 
Data Transfer Modes in DMA
• Cycle Stealing: The DMA Controller(DMAC )steals the system bus  (Memory cycles) from
the CPU, during its non-memory machine  cycles like Decode or execute, to transfer a
byte/word to/from  memory. 
• Burst Mode: 
• Once the DMAC takes the bus, it completes the data transfer with the necessary number
of cycles.
• Holds the system bus until the Byte Count reaches zero, after which it releases  the bus.  
• The CPU is halted during the data transfer.  
• Since the intended block is transferred in one bus access, Burst mode is also  called Block
Transfer Mode.
• Programmed I/O
Programmable I/O is one of the I/O technique other than the interrupt-driven I/O and direct memory access (DMA).
The programmed I/O was the most simple type of I/O technique for the exchanges of data or any types of
communication between the processor and the external devices. With programmed I/O, data are exchanged between
the processor and the I/O module. The processor executes a program that gives it direct control of the I/O operation,
including sensing device status, sending a read or write command, and transferring the data. When the processor
issues a command to the I/O module, it must wait until the I/O operation is complete. If the processor is faster than
the I/O module, this is wasteful of processor time. The overall operation of the programmed I/O can be summaries
as follow:

1. The processor is executing a program and encounters an instruction relating to I/O operation.
2. The processor then executes that instruction by issuing a command to the appropriate I/O module.
3. The I/O module will perform the requested action based on the I/O command issued by the processor
(READ/WRITE) and set the appropriate bits in the I/O status register.
4. The processor will periodically check the status of the I/O module until it find that the operation is complete
INTERRUPTS
• An interrupt in computer architecture is a signal that requests the processor to suspend its current execution
and service the occurred interrupt
• To service the interrupt the processor executes the corresponding interrupt service routine (ISR). After the
execution of the interrupt service routine, the processor resumes the execution of the suspended program.
• When a program enters a wait loop, it will repeatedly check the device status. During this period, the
processor will not perform any function.
• The Interrupt request line will send a hardware signal called the interrupt signal to the processor.
• On receiving this signal, the processor will perform the useful function during the waiting period.
• The routine executed in response to an interrupt request is called Interrupt Service Routine.
• The interrupt resembles the subroutine calls.

Fig:Transfer of control through the use of interrupts

• The processor first completes the execution of instruction i Then it loads the PC(Program Counter) with the
address of the first instruction of the ISR. After
• the execution of ISR, the processor has to come back to instruction i + 1
• Therefore, when an interrupt occurs, the current contents of PC which point to i +1 is put in temporary
storage in a known location.
• A return from interrupt instruction at the end of ISR reloads the PC from that temporary storage location,
causing the execution to resume at instruction i+1.
• When the processor is handling the interrupts, it must inform the device that its request has been recognized
so that it remove its interrupt requests signal
• This may be accomplished by a special control signal called the interrupt acknowledge signal.
• The task of saving and restoring the information can be done automatically by the processor.
• The processor saves only the contents of program counter & status register (ie) it saves only the minimal
amount of information to maintain the integrity of the program execution.
Interrupt Vector Table
(IVT)
Types of Interrupts in Computer Architecture
• The interrupts can be various type but they are basically classified into hardware interrupts
and software interrupts.
1. Hardware Interrupts
• If a processor receives the interrupt request from an external I/O device it is termed as a
hardware interrupt. Hardware interrupts are further divided into maskable and non-maskable
interrupt.
• Maskable Interrupt: The hardware interrupt that can be ignored or delayed for some time if
the processor is executing a program with higher priority are termed as maskable interrupts.
• Non-Maskable Interrupt: The hardware interrupts that can neither be ignored nor delayed and
must immediately be serviced by the processor are termed as non-maskeable interrupts.
2. Software Interrupts
• The software interrupts are the interrupts that occur when a condition is met or a system call
occurs.
 Pipelinin
g
• Pipelining is a particularly effective way of organizing concurrent activities in a computer system.
• Pipelining overlaps the execution of successive instructions to achieve high performance.
• For example, while one instruction is being executed, the computer is decoding the next instruction.
• The execution of an instruction involves multiple stages of operation: Fetch, Decode, Execute, Write
• Pipelining enables a processor to work simultaneously on multiple instructions by performing a
Instruction
different stage for each of the multiple instructions at the same time
• Conceptcycle
of pipelining is also useful for performing arithmetic operations (like adding and subtraction
ofwith
floating-point numbers)
Interrupt
• This is the same principle as seen in an assembly line.
No pipeline Vs Two Stage
Pipeline
Four Stage Pipeline
Example- A four stage pipeline
What should be length of the clock period
• Each stage in a pipeline is expected to complete its operation in one
clock cycle.
• Hence, the clock period should be sufficiently long to complete the
task being performed in any stage.
• If different units require different amounts of time, the clock period
must allow the longest task to be completed.
• A unit that completes its task early is idle for the remainder of the
clock period.
• Hence, pipelining is most effective in improving performance, if the
tasks
• being performed in different stages require about the same amount
of time.
Pipeline Hazards
Pipeline hazards: hazards are circumstances that prevent the next
instruction in the instruction stream from executing during the
designated clock cycle.
• Any condition that causes the pipeline to stall is called a hazard.
• Types of hazards:
• Data Hazards:
• control hazards or instruction hazards.
• Structural Hazards
Data Hazards
• A data hazard is any condition in which either the source or the
destination operands of an instruction are not available at the time
expected in the pipeline.
• Data hazards in pipelining emerge when the execution of one
instruction is dependent on the results of another instruction that is still
being processed in the pipeline
Instruction hazard/control hazard
• The pipeline may also be stalled because of a delay in the availability
of an instruction.
• This is caused by branch instructions in which prefetched instruction
becomes useless after the jump instruction taking control to another
instruction
Structural Hazard
• Haídwaíe íesouíce conflicts among the instíuctions in the
pipeline cause stíuctuíal hazaíds.
• Memoíy, a geneíal-puípose Registeí, oí an ALU might all be
used as íesouíces heíe.
• When moíe than one instíuction in the pipeline íequiíes access
to the veíy same íesouíce in the same clock cycle, a íesouíce
conflict is said to aíise.
• In an oveílapping pipelined execution, this is a ciícumstance
wheíe the haídwaíe cannot handle all potential combinations.
 Example: Instruction hazard due to cache
miss
• Instruction I1 is fetched from the cache in
cycle 1, and its execution proceeds
normally.
• However, the fetch operation for
instruction I2, which is started in cycle 2,
results in a cache miss.
• The instruction fetch unit must now
suspend any further fetch requests and
wait for I2 to arrive.
• We assume that instruction I2 is received
and loaded into buffer B1 at the end of
cycle 5.
• The pipeline resumes its normal
operation at that point.