Module 2

Layout Compaction
Introduction
 One of the goals in VLSI design is to minimize the area
of the final circuit.
 Design decisions at all levels of abstraction have a
consequence for the area of the final circuit.
 At the lowest level, the level of the mask patterns for
the fabrication of the circuit, a final optimization can
be applied to remove redundant space. This
optimization is called layout compaction.
Design Rules
The mask patterns that are used for the fabrication of
an integrated circuit have to obey certain restrictions
on their shapes and sizes. These restrictions are called
the design rules.
Sticking to the design rules decreases the probability
that the fabricated circuit will not work due to short
circuits, disconnections in wires, parasitics, etc.
The shape of the patterns is often restricted to
rectilinear polygons, i.e' polygons that are made of
horizontal and vertical segments only.
There are design rules for layout elements located in
the same fabrication layer and rules for elements in
different layers.
If patterns in two specific layers are constrained by one
or more design rules, the layers are said to interact.
Design rules can be quite complex. However, most of
them can be expressed as minimum-distance rules.
As the minimum feature size that can be realized on a
chip is subject to continual change (from several microns
a few years ago to a few tenths of microns nowadays)
distances are often expressed in integer multiples (or
small fractions) of a relative length unit, the , λ", rather
than absolute length units.
In this way, designers can deal with simple expressions
independent of actual length values. This means that all
mask patterns are drawn along the lines of a so-called
lambda grid.
Lambda Grid

Minimum-distance design rules on a lambda grid: minimum width (a), minimum

separation (b, c and d) and minimum overlap (e).
The most common types of minimum-distance rules are:

 Minimum width: a pattern in a certain layer cannot be narrower than

a certain distance (see Figure 6.2(a)).

 Minimum separation: two patterns belonging to the same (see Figure

6.2(b)) layer or to different but interacting layers (see Figure 6.2(c))
cannot be positioned closer to each other than a certain distance; this
is also true when the rectangles are diagonally separated (see Figure
6.2(d)).

 Minimum overlap: a pattern in one layer located on top of a pattern in

another interacting layeq should have a minimal overlap (see Figure
6.2(e)).
Symbolic Layout
The existence of design rules makes the design of
layout very cumbersome;
There are many design rules and a human designer
can overlook one of them very easily when fixing the
position of a certain rectangle.
Although special tools, so-called design rule checkers,
exist for detecting this type of mistakes, the mistake
might not be easy to correct, requiring one to
reposition many other rectangles in the neighborhood
of the wrong one.
In this context, geometry means that the coordinates
of the rectangles are absolute and topology means that
only relations between layout elements, such as "to the
left of" or "below", are known.
The symbolic layout of a simple CMOS inverter is
given in Figure

The symbolic layout of a CMOS inverter (a), its geometric layout (b) and
a
Symbolic layout can normally be created interactively
on a graphics computer screen, by means of a symbolic
layout editor or it can be specified in textual form, by
means of a formal layout language.
The advantages of symbolic layout can only be
exploited if tools exist for automatically converting
symbolic layout into geometric layout.
Problem Formulation
 Applications of Compaction
 Converting symbolic layout to geometric layout.
 Removing redundant area from geometric layout
 Adapting geometric layout to a new technology
 Correcting small design rule errors
Adapting geometric layout to a new technology

A new technology means that the design rules have

changed; as long as the new and old technologies are
compatible (e.g. both are CMOS technologies with the
same mask layers), this adaptation can be done
automatically, e.g. by means of so-called mask-to-
symbolic extraction.
Correcting small design rule errors
If there are methods to put layout elements
closer to each other to remove redundant space, it is
plausible to assume that pulling layout elements apart
when they are too close to each other can be done
similarly.
 This is true as long as the layout with design-rule
errors is topologically correct: the relative ordering of
the rectangle edges in interacting layers should be the
same as in the correct design.
Informal Problem Formulation
Basically, the rectangles can be classified into two
groups
 Rigid rectangles corespond to transistors and
contact cuts whose length and width are fixed. when
they are moved during a compaction process, their
lengths and widths do not change.
Stretchable rectangles correspond to wires .
Layout is essentially two-dimensional and layout
elements can in principle be moved both horizontally
and vertically for the purpose of compaction.
when one dimensional compaction tools are used, the
layout elements are only moved along one direction
(either vertically or horizontally).
Two dimensional compaction tools move layout
elements in both directions simultaneously.
Graph-theoretical Formulation
In one-dimensional, say horizontal, compaction a
rigid rectangle can be represented by one x-coordinate
(of its center, for example) and a stretchable one by
two (one for each of the endpoints)
For the purpose of the algorithms to be explained, it is
assumed that there are n distinct x-coordinates. They
will be indicated as xr, x2, . . . , xn.
A minimum-distance design rule between two
rectangle edges can now be expressed as an inequality:

Assuming that the minimum width for the layer

concerned is a and the minimum separation is b, the
following (and many other) inequalities are valid:
It is now possible to represent all these
inequalities in a so-called constraint graph
G(V, E), constructed in the following way:
The vertex set V is composed by
associating a vertex Vi, with each variable
xi; that occurs in an inequality.
The edge set E is composedof edges (Vi,Vj)
with weight w((vi,vj)) =dij for each
inequality xj - xj > dij.
There is a source vertex v0, located at x
=0.So, there ate n +1 vertices in total:
 v0, v1, . . . , vn.All layout elements are
assumed to have a positive x-coordinate'
This is incorporated in the graph by edges
from the source vertex to those vertices
that do not have any other vertices
constraining them at the left.
A constraint graph derived from only minimum-distance
constraints has no cycles . It is called a directed acyclic
graph, often denoted by the abbreviation DAG.
The following observation can be made:
 the length of the longest path from the source vertex V0
to a specific vertex Vi; in a the constraint graph G(V, E)
gives the minimal x-coordinate Xi associated to that vertex.
 By taking the longest path to Vi, one makes sure that all
inequalities in which xi, participates are satisfied. So,
computing the lengths of the longest paths to all vertices
in the constraint graph results in a solution for the one-
dimensional compaction problem.
Maximum-distance Constraints
Some situations necessitate the limitation of the
maximum distance between the coordinates of layout
elements. An example of such a situation is a
connectivity constraint: moving an element too far
away with respect to another can break an electrical
connection.
The situation in the figure gives rise to two
constraints:

Maximum-distance constraints can in general be written

as:
where cij ≥ 0. This can also be written as:
The last inequality has the same form as Inequality
and can be represented in the constraint graph by an
edge (Vj,Vi) with weight dij = -Cij.
 The addition of this type of edges can create cycles in
the constraint graph.
In the presence of cycles, the solution of the
compaction problem still amounts to computing the
lengths of the longest paths. However, the problem is
more difficult than finding the longest path in a DAG.
Algorithms for Constraint-graph Compaction
A longest-path Algorithm for DAGs
A variable pi is associated with each vertex vi to keep
count of the edges incident to vi that have already
been processed.
 Because the graph is acyclic, once all incoming edges
have been processed, the longest path to vi is known.
Then vi is included in a set Q.
 It will be taken out later on to traverse the edges
incident from it in order to propagate the longest-path
values to the vertices at their endpoints.
The longest-path algorithm
presented has a time
complexity o(E). This is easy
to see: all edges in the graph
are visited exactly once during
the execution of the inner for-
each loop
The value given for the set Q
is the value at the beginning
of the iteration. The first
element is removed. The
remaining elements in the
same row are the updated
values after processing this
first element.
The Longest Path in Graphs with Cycles
Two cases can be distinguished:
1. The graph only contains negative cycles , i.e. the sum of the
edge weights along any cycle is negative.
2. The graph contains positive cycles.
 The problem for graphs with positive cycles is NP-hard.
However, a constraint graph with positive cycles corresponds to
a layout with conflicting constraints (in which e.g. the
minimum distance for two coordinates exceeds the maximum
one). Such a layout is called overconstrained and is impossible
to realize.
 So, the best to be done in such a case is to detect the existence
of positive cycles. They can be detected in polynomial time.
The LiaoWong Algorithm
Liao and Wong have proposed an algorithm that
partitions the edge set E of the constraint graph G(V,
E) into two sets Ef and Eb.The edges in Ef have been
obtained from the minimum-distance inequalities and
ate called forward edges. The edges in Eb correspond
to maximum-distance inequalities and are called
backward edges (they create cycles by going
backward).
The main idea is to start with Gf(V, Ef ) which is acyclic and to which the
DAG longest-path algorithm can be applied.
 Then the backward edges are considered and modifications to the minimal
x-coordinates are made, followed by a call to the DAG longest path algorithm
to propagate the effects of the modifications through the forward edges.
This process (modifications due to backward edges followed by propagation)
is repeated until the values of the minimal x-coordinates stabilize or a
maximum number of iterations equal to [Eb] have been performed. In the
last case, a positive cycle exists.
In order to understand that the algorithm is correct, one should realize that
at the kth iteration of the do loop, the values of the xi represent the longest-
paths going through all forward edges and possibly k backward edges. As a
longest-path contains each edge at most once, the algorithm should
terminate after at most lEb | iterations in the absence of positive cycles.
The Bellman-Ford Algorithm
 An alternative to the Liao-Wong algorithm is the
Bellman-Ford algorithm. The algorithm does not
discriminate between forward and backward edges. It
is comparable to the longest path algorithm for DAGs
with the difference that several iterations through the
graph are necessary before the lengths of the longest
paths have been computed.
One way of looking at the algorithm is to see it as repeated wave
front propagation: ,Sl contains the current wave front and S2 is
the one for the next iteration.
As in the Liao-Wong algorithm' if there are more than n
iterations, where n is the number of vertices in the graph G(V,
E),it can be concluded that the graph has positive cycles.
 Informally, this can be seen as follows: after k iterations, the
algorithm has computed the longest-path values for paths going
through k - 1 intermediate vertices.
If there are no cycles, the algorithm should terminate after at
most n iterations, as the longest path to a vertex can go through
at most n – 1 vertices.
Other Issues
 Noncritical layout elements: . In general, all layout
elements not on the critical path have some mobiliry
or freedom.
 Automatic Jog Insertion: Considering a wire as a
rectangle that is merely stretchable in one dimension,
does not exploit all the possible freedom that one has
with wires. One such possibility is the insertion of
jogs. This is the splitting of a wire in segments such
that these segments can be moved with respect to each
other.
 Constraint Generation: An efficient algorithm is necessary [o
convert a layout into a constraint graph. In a straightforward
algorithm, assuming horizontal compaction, one could
inspect all pairs of layout elements and generate a weighted
edge between them, if they overlap when projected on the
vertical axis.
 Hierarchy: It is important to note that compaction will seldom
be applied to the layout of a complete integrated circuit. The
physical domain can be described hierarchically, such that
small groups of transistors form a cell, groups of cells form
modules, etc. If special attention is paid to cell boundaries, it
is normally sufficient to apply compaction to cells only.