Analog and Digital Electronics

21CS33
Venugopala Rao A S
Dept. of Computer Science and Design
AIET, Moodbidri
 Module 3
• Combinational circuit design and simulation using gates:
Review of Combinational circuit design, design of circuits
with limited Gate Fan-in, Gate delays and Timing diagrams,
Hazards in combinational Logic, simulation and testing of
logic circuits

• Multiplexers, Decoders and Programmable Logic Devices:

Multiplexers, three state buffers, decoders and encoders,
Programmable Logic devices.

• Textbook 1: Part B: Chapter 8, Chapter 9 (Sections 9.1 to 9.6)

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 Review of Combinational circuit design
• Review of Combinational Circuit Design
• When logic gates connected together to produce a specified
output specified combinations of input variables, with no
storage involved, the resulting circuit is called combinational
logic circuit
• In combinational logic circuit, the output variables are at all
times dependent on the combination of input variables.

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• Design Procedure
• The design of combinational circuits starts from the outline
of the problem statement and
• Ends in a logic circuit diagram or a set of Boolean functions
from which the logic diagram can be easily obtained.
• The design procedure involves following steps

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• 1. The problem definition.
• 2. The determination of number of available input variables
and required output variables.
• 3. Assigning letter symbols to input and output variables.
• 4. The derivation of truth table indicating the relationships
between input and output variables.
• 5. Obtain simplified Boolean expression for each output.
• 6. Obtain the logic diagram.

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• A Combinational Function Generator
• Here, the combinational circuit is represented by the
relationship between its input and an output variable or
variables.
• We will see a few examples to understand the procedure to
design such combinational circuits.
• E.g. 1:
• Design a combination logic circuit with three input variables
that will produce a logic 1 output when more than one input
variables are logic 1.

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• Solution:
• Step 1 Derive the truth table for given statement
• Given that there are three input variables and one output
variable.
• Let us name them as A, B and C and let Y letter be the
symbol to one output variable.
• The relationship between input variables and output variable
needs to be tabulated in the form of truth table

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• Step 2: Obtain simplified Boolean expression.

• Now we obtain the simplified Boolean expression for output

variable Y using K-map simplification.
• Y = AC + BC + AB
• Step 3: Draw logic diagram.

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• Example 2: Design circuit to detect invalid BCD number and
implement using NAND gate only
• Solution:
• Truth table

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• Design of Circuits with Limited Gate Fan-in
• In practical circuit design problems, the maximum number
of inputs on each gate is limited, (Fan-in is limited).
• Depending on the type of gates used, this limit may be 2, 3, 4
or 8.
• If a two level realization of a circuit requires more gate
inputs than allowed, factoring of the logic expression in done
to obtain a multilevel realization.

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• E.g.: Minimize the following functions and realize them
using only 2 input NAND gates and inverters
• f1=Ʃ m(0, 2, 3, 4, 5) f2=Ʃ m(0, 2, 3, 4, 7)
• f3=Ʃ m(1, 2, 6, 7)
• Step 1: minimize each function separately

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• Step 2: To implement each expression we need, three 3-input
OR gate.
• Since the requirement is to use 2-input OR gate we need to
factorize them.

• or

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• Check for the common terms in these three function.
• Let us choose second expression for f2 as it has the term (a`b)
common with f1.
• The term (a`b`c) of f3 can be represented as
• a`b`c = a`(b` c) = a`((b+c`))`
• The term (b+c`) in the above expression can be shared with
the same term in the function f2.
• The term (a+c`) is common in functions f1 and f3.
• Let us first realize these function using basic gates.

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• NAND Gate implementation:
• A NAND and NOR gates (universal gates) can be used to
implement any Boolean function
• Let us see how to implement a circuit that is equivalent to
the given circuit and consists of only NAND gates.
• E.g.

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• Same Boolean Function with NAND gate is as shown below:

• Before we get to how to convert any circuit to a NAND-only

circuit, let us see how to implement Complement, AND &
OR operation using NAND gates.

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• COMPLEMENT Using NAND

• AND Using NAND

• OR Using NAND

• NAND using OR & Inverter

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• Procedure for Conversion
• Consider the following circuit.

• We have to re-implement this using only NAND gates.

• Let us insert two inverters between each AND gate and OR
gate as shown below

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• This circuit is equivalent to the original one
• The output of each AND gate is being complemented twice
before the signal reaches the OR gate.
• These inverters will play a key role in the process of
conversion.
• Now take a look at the highlighted areas.

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• The gates in each highlighted area can be combined into one
NAND gate. Thus we get

• Now look at the blue highlighted area.

• Recall the implementation of a NAND operation using OR &
inverter gates we have covered above, the gates in the blue area
implement a NAND operation.
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• Therefore we can just replace all the gates in the blue area
with a single NAND gate!

• Our Final Result:

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• To realize using 2-input NAND gate and inverter note the
following rule, Bubbled NAND= OR
• E.g.:

• Also AND-OR logic can be represented by NAND-NAND

Logic

• Using these we can redraw the previous circuit using NAND

gates only

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• Gate Delays and Timing Diagrams
• When the input to a logic gate is changed, the output will not
change instantaneously.
• The transistors or other switching elements within the gate
take a finite time to react to a change in input, so that the
change in the gate output is delayed with respect to the input
change
• Following figure shows possible input and output waveforms
for an inverter.

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• If the change in output is delayed by time, ε, with respect to

the input, we say that this gate has a propagation delay of ε.
• In practice, the propagation delay for a 0 to 1 output change
may be different than the delay for a 1 to 0 change
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• Propagation delays for integrated circuit gates may be as
short as a few nanoseconds (l nanosecond =10-9 second), and
in many cases these delays can be neglected.
• But, in the analysis of some types of sequential circuits, even
short delays may be important.
• Timing diagrams are used in the analysis of sequential
circuits.
• These diagrams show various signals in the circuit as a
function of time.

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• Several variables are usually plotted with the same time scale
so that the times at which these variables change can be
visualized easily
• Consider the following timing diagram for a circuit with two
gates

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• This timing diagram is drawn for the following conditions

• Gate inputs B and C are held at constant values 1 and 0,
respectively, and input A is changed to 1 at t=40 ns and then
changed back to 0 at t=100 ns.
• The output of gate G1 changes 20 ns after A changes, and the
output of gate G2 changes 20 ns after G1 changes.
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• Hazards in Combinational Logic:
• When the input to a combinational circuit changes, unwanted
switching transients may appear in the output.
• These transients occur when different paths from input to
output have different propagation delays.
• If, in response to any single input change and for some
combination of propagation delays, a circuit output may
momentarily go to 0 when it should remain a constant 1, we
say that the circuit has a static 1-hazard.
• Similarly, if the output may momentarily go to 1 when it
should remain a 0, we say that the circuit has a static 0-hazard
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• If, when the output is supposed to change from 0 to 1 (or 1 to
0), the output may change three or more times, we say that
the circuit has a dynamic hazard.
• Figure below shows possible outputs from a circuit with
hazards.

• In each case the steady-state output of the circuit is correct,

but a switching transient appears at the circuit output when
the input is changed.
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• Hazards are properties of the circuit and are independent of
the delays existing in the circuit
• Consider the following circuit

• If A = C = 1, then F = B + B’ = 1, so the F output should

remain a constant 1 when B changes from 1 to 0.

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• Timing Diagram:

• If each gate has a propagation delay of 10 ns, E will go to 0

before D goes to 1, resulting in a momentary 0 (a glitch
caused by the 1-hazard) appearing at the output F.

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• Note that, after B changes to 0, both the inverter input (B)
and output (B’) are 0 until the propagation delay has elapsed.
• During this period, both terms in the equation for F are 0, so
F momentarily goes to 0.
• Detection of Static 1 Hazard:
• Hazards can be detected using a Karnaugh map

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• As seen on the map, no loop
covers both minterms ABC and
ABC`.

• So if A = C = 1 and B changes,
both terms can momentarily go
to 0, resulting in a glitch in F.

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• We can detect hazards in a two-level AND-OR circuit, using
the following procedure:
• 1. Write down the sum-of-products expression for the circuit.
• 2. Plot each term on the map and loop it.
• 3. If any two adjacent 1’s are not covered by the same loop, a
1-hazard exists for the transition between the two 1’s.
• For an n-variable map, this transition occurs when one
variable changes and the other n –1 variables are held
constant.

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• To Eliminate Static 1 Hazard:
• If we add a loop to the map of above Figure and, then, add
the corresponding gate to the circuit, hazard gets eliminated

• The term AC remains 1 while B is changing, so no glitch can

appear in the output.
• Note that F is no longer a minimum sum of products.
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• Detection of Static 0 Hazard:
• The following Figure shows a circuit with several 0-hazards.

• The POS representation for the circuit output is

• 𝐹= (𝐴+𝐶) (𝐴′+𝐷′) (𝐵′+𝐶′+𝐷)
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• The Karnaugh map for this function:

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• From the K-map we can see that, four pairs of adjacent 0’s
are not covered by a common loop as indicated by the
arrows.
• Each of these pairs corresponds to a 0-hazard.
• Assume that gate delays of 3 ns for each inverter, and of 5 ns
for each AND gate and each OR gate
• when A = 0, B = 1, D = 0, and C changes from 0 to 1, a spike
may appear at the Z output for some combination of gate
delays.
• The timing diagram illustrates this.

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• A = 0, B = 1, D = 0,
• C = 01

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• To Eliminate Static 0 Hazard:
• We can eliminate the 0-hazards by looping additional prime
implicants that cover the adjacent 0’s that are not already
covered by a common loop.
• This requires three additional loops as shown in the
following Figure.

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•.

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• The resulting circuit requires seven gates in addition to the
inverters, as given by below expression
• 𝐹= (𝐴+𝐶) (𝐴′+𝐷′) (𝐵′+𝐶′+𝐷) (𝐶+𝐷′) (𝐴+𝐵′+𝐷) (𝐴′+𝐵′+𝐶′)

• The SOP or POS expression is derived in the normal manner

except that the complementation laws are not used,
• i.e., xx’ = 0 and x + x’ = 1 are not used.
• The resulting SOP (POS) expression may contain products
(sums) of the form xx’α or (x + x’ + β).
• α is a product of literals or it may be null and β is a sum of
literals or it may be empty.
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• SIMULATION AND TESTING OF LOGIC CIRCUITS:
• An important part of the logic design process is verifying
that the final design is correct and debugging the design if
necessary.
• Logic circuits may be tested either by actually building them
or by simulating them on a computer.
• Simulation is generally easier, faster, and more economical.
• As logic circuits become more and more complex, it is very
important to simulate a design before actually building it.

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• This is true when the design is built in IC form, because
fabricating an IC may take a long time and correcting errors
may be very expensive.
• Simulation is done for following reasons:
• Verification that the design is logically correct
• Verification that the timing of the logic signals is correct, and
• Simulation of faulty components in the circuit as an aid to
finding tests for the circuit.

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• A simple simulator for combinational logic works as follows:
1. The circuit inputs are applied to the first set of gates in the
circuit, and the outputs of those gates are calculated.
2. The outputs of the gates which changed in the previous step
are fed into the next level of gate inputs. If the input to any
gate has changed, then the output of that gate is calculated.
3. Step 2 is repeated until no more changes in gate inputs occur.
The circuit is then in a steady-state condition, and the
outputs may be read.
4. Steps 1 through 3 are repeated every time a circuit input
change.
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• MULTIPLEXERS:
• A multiplexer (or data selector, abbreviated as MUX) has a
group of data inputs and a group of control inputs.
• The control inputs are used to select one of the data inputs
and connect it to the output terminal.
• The following Figure shows a 2-to-1 multiplexer.

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• When the control input A is 0, the switch is in the upper
position and the MUX output is Z = I0
• When A is 1, the switch is in the lower position and the
MUX output is Z = I1.
• Thus, a MUX acts like a switch that selects one of the data
inputs (I0 or I1) and transmits it to the output.
• The logic equation for the 2-to-1 MUX is
therefore: 𝑍 = 𝐴′ 𝐼0 + 𝐴𝐼1

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• 4-to-1 multiplexer

• The 4-to-1 MUX acts like a four-position switch that

transmits one of the four inputs to the output.

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• Two control inputs (A and B) are needed to select one of the
four inputs. If the control inputs are AB = 00, the output is I0;
similarly, the control inputs 01, 10, and 11 give outputs of I1,
I2, and I3, respectively.
• The 4- to-1 multiplexer is described by the
equation: 𝑍 = 𝐴′ 𝐵′𝐼0 + 𝐴′ 𝐵𝐼1 + 𝐴𝐵′𝐼2 + 𝐴𝐵𝐼3

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• 8-to-1 MUX:

• The 8-to-1 MUX selects one of eight data inputs using three
control inputs.
• It is described by the equation:
• 𝑍 = 𝐴′𝐵′𝐶′𝐼0 + 𝐴′𝐵′𝐶𝐼1 + 𝐴′𝐵𝐶′𝐼2 + 𝐴′𝐵𝐶𝐼3+𝐴𝐵′𝐶′𝐼4+𝐴𝐵′𝐶𝐼5+𝐴𝐵𝐶′𝐼6
+ 𝐴𝐵𝐶𝐼7.
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• Internal schematic of 8:1 MUX

• If the OR gate in the above Figure is replaced by a NOR

gate, then the 8-to-1 MUX inverts the selected input.
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• To distinguish between these two types of multiplexers, we
will say that the multiplexers without the inversion have
active high outputs, and the multiplexers with the inversion
have active low outputs.
• In general, a multiplexer with n control inputs can be used to
select any one of 2n data inputs.
• The general equation for the output of a MUX with n control
inputs and 2n data inputs is:

• mk is a minterm of the n control variables and Ik is the

corresponding data input.
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• 2n-to 1 MUX:

• Multiplexers can also have an additional input called an enable

input.
• Multiplexers are frequently used in digital system design to
select the data which is to be processed or stored.
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• Multiplexer Logic:
• A digital design begins with a formation of truth table.
• Solution to the problem is to come up with a logic circuit
that has the same truth table.
• two standard methods for implementing a truth table are
• the SOP and the POS solution.
• The third method is the multiplexer solution.
• E.g. 1:
• Implement Y (A, B, C, D) = Σm (0, 2, 3, 4, 5, 8, 9, 10, 11,
12, 13, 15) using 16-to-1 multiplexer (IC 74150) & 8-to-1
multiplexer.
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 A B
MUX,
C D Y
DECODERS, AND PLD
• Truth
0 0
table
0 0 1
0 0 0 1 0
0 0 1 0 1
0 0 1 1 1
0 1 0 0 1
0 1 0 1 1
0 1 1 0 0
0 1 1 1 0
1 0 0 0 1
1 0 0 1 1
1 0 1 0 1
1 0 1 1 1
1 1 0 0 1
1 1 0 1 1
1 1 1 0 0
1 1 1 1 1
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• We follow a procedure that is
similar to the one that we
adopted in Entered Variable
Map method to implement Y
using 8-to-1 MUX.

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• Expanding Multiplexers
• Several digital multiplexer ICs are available such as 74150 (16
to 1), 74151 (8 to 1), 74157 (Dual 2 input) and 74153 (Dual 4
to 1) multiplexer.
• It is possible to expand the range of inputs for multiplexer
beyond the available range in the integrated circuits.
• This can be accomplished by interconnecting several
multiplexers.
• E.g.: Two 74XX151, 8 to 1 multiplexers can be used together to
form a 16-to-1 multiplexer, two 74XX150, 16 to 1 multiplexers
can be used together to form a 32 to 1 multiplexer and so on.
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• Various Multiplexer ICs
• 74153 4 to 1 MUX

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• 74151 8 to 1 MUX

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• 74152 8 to 1 MUX - It has eight inputs and one output. The
output is in inverted form.

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• 74150 – 16 to 1 MUX

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• E.g.: Design 32 to 1 multiplexer using two 74LSI50
• to design 32-to-1 MUX
• 16-to-1 mux needed - 2
• Select inputs needed - 5
• Let A, B, C, D and E be select inputs
• E input is to be applied to the enable input of the MUX 1 and
E` is to be applied to MUX 2

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• E.g. 2: Design 32:1 multiplexer using two 16:1 multiplexers
and one 2:1 multiplexer.
• Solution:
• To design 32:1 MUX we need to 16:1 MUX.
• The output of these two MUX should be fed as input to 2:1
MUX
• Select lines S0, S1, S2 and S3 are connected in parallel to both
16:1 multiplexers.
• S4 is connected to 2:1 MUX to select one of the output of
two 16:1 MUX

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• E.g.: Construct 8:1 multiplexer using 2:1 multiplexer

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• Examples to Practice:
• Construct 16:1 multiplexer using 4:1and 2:1 multiplexer
• Design a 16 to 1 multiplexer using two 8 to 1 multiplexer
and one 2 to multiplexer

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• Demultiplexers:
• In digital systems, many times it is necessary to route data
from single data line to one of the available output lines and
there should be facility to select the output line on which the
data is to be routed.
• The digital circuit which does this task is a demultiplexer.
• A demultiplexer is a circuit that receives information on a
single line and transmits this information on one of 2n
possible output lines.
• The selection of specific output line is controlled by the
values of n selection lines
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• The following figure shows the block diagram of a
demultiplexer.

• It has one input data line, 2 output lines, n select lines and
one enable input.
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• Differentiate between Multiplexer and Demultiplexer
• List out – based on inputs, outputs, functionality

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• Three-State Buffers
• A gate output can only be connected to a limited number of
other device inputs without degrading the performance of a
digital system.
• A simple buffer may be used to increase the driving
capability of a gate output.
• Figure below shows a buffer connected between a gate
output and several gate inputs

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• As there is no bubble is present at the buffer output, this is a non-
inverting buffer, and the logic values of the buffer input and
output are the same, that is, F = C.
• Normally, a logic circuit will not operate correctly if the outputs
of two or more gates or other logic devices are directly
connected to each other.
• For example, if one gate has a 0 output and another has a 1
output, when the gate outputs are connected together the
resulting output voltage may be some intermediate value that
does not clearly represent either a 0 or a 1.
• In some cases, damage to the gates may result if the outputs are
connected together.
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• Use of three-state logic permits the outputs of two or more
gates or other logic devices to be connected together.
• Following figure shows a three-state buffer and its logical
equivalent

• Here B acts as enable input

• When the enable input is 1, the output C equals A; when B is 0,
the output C acts like an open circuit.
• In other words, when B is 0, the output C is effectively
disconnected from the buffer output so that no current can flow.
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• This is referred to as a Hi-Z (high-impedance) state of the
output because the circuit offers a very high resistance or
impedance to the flow of current.
• Three-state buffers are also called tri-state buffers.
•
• There are four types of tri-state buffers as shown below
•

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• In first two, the enable input B is not inverted, so the buffer
output is enabled when B = 1 and disabled when B = 0.
• That is, the buffer operates normally when B=1, and the
buffer output is effectively an open circuit when B = 0.
• We use the symbol Z to represent this high-impedance state.
• Also note that, in second figure, the buffer output is inverted
so that C =A` when the buffer is enabled.
• The buffers in 3rd and 4th figures operate the same as in 1st
and 2nd except that the enable input is inverted, so the buffer
is enabled when B = 0.

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• The operation of these buffers can be summarized in truth
table as shown below

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• Consider the following figure:

• Here the outputs of two three-state buffers are tied together.

• When B=0, the top buffer is enabled, so that D = A and when
B = 1, the lower buffer is enabled, so that D=C.
• Therefore, D =B'A + BC. This is logically equivalent to
using a 2-to-1 multiplexer to select the A input when B= 0
and the C input when B = 1.
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• Let us connect two three-state buffer outputs together, as
shown below

• If one of the buffers is disabled (output = Z), the combined

output F is the same as the other buffer output.
• If both buffers are disabled, the output is Z.
• If both buffers are enabled, a conflict can occur.
• If A = 0 and C = 1, we do not know what the hardware will
do, so the F output is unknown (X).
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• If one of the buffer inputs is unknown, the F output will also
be unknown.
• The table below summarizes the operation of the circuit.

• S1 and S2 represent the outputs the two buffers would have

if they were not connected together.
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• A multiplexer may be used to select one of several sources to
drive a device input.
• E.g.: if an adder input must come from four different
sources; a 4-to-1 MUX may be used to select one of the four
sources. An alternative is to set up a three-state bus, using
three-state buffers to select one of the sources (see the
following Figure). In this circuit, each buffer symbol actually
represents four three-state buffers that have a common
enable signal.

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• Decoder
• The decoder is another commonly used type of integrated
circuit
• Decoder is identical to a demultiplexer without any data
input.
• Its outputs can be either active-low or active-high.
• For active-high outputs, the output selected by select lines
(usually called address lines) goes high, other outputs remain
low.

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• Fig. shows 2 to 4 decoder.
• Here, 2 inputs are decoded
into four outputs, each
output representing one the
minterms of the 2 input
variables.
• The two inverters provide
the complement of the
inputs, and each one of
four AND gates generates
one of the minterms.
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• The truth table for a 2 to 4 decoder can be written as shown
below.

• As shown in the truth table, if enable input is 1 (EN = 1),

one, and only one, of the outputs Y0 to Y3, is active for a
given input.
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• The output Y0 will be active, ie. Y0 = 1 when inputs A = B =
0, the output Y1 is active when inputs A = 0 and B = 1.
• If EN = 0, then all the outputs are 0.
• 3:8 decoder:
• This decoder generates all of the minterms of the three input
variables.
• One of the output lines will be 1 for each combination of the
values of the input variables.
• 3-to-8 line decoder can be pictorially represented as shown.

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• Truth table:

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• Decoder ICs
• 3 to 8 Decoder (IC 74138)
• The 74X138 is a commercially available 3-to-8 decoder.
• It accepts three binary inputs (A, B, C) and provides eight
enabled, individual active low outputs (Y0 - Y7).
• The device has three enable inputs: two active low (G2A,G2B)
and one active high (G1).
• Logic symbol and function table are shown in the following
figures

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• Implementation of Combinational Logic using Decoder
• When decoder output is active high, it generates minterms
(product terms) for input variables; i.e. it makes selected
output logic 1.
• In such case to implement SOP function we have to take sum
of selected product terms generated by decoder implemented
by ORing the selected decoder outputs.

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• E.g.: f = Ʃ M(1,2,3, 7) using 3:8 decoder with active high
outputs.

• E.g. 2: Implement the following function using 3:8 decoder

and external gates F(A,B,C)= Ʃm(2,4,5,7)
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• Solution:
• The decoder produces minterms.
• The outputs Y2, Y4, Y5 and Y7 are ORed to produce the
required output.
• The following Fig. shows the implementation of given
Boolean function.

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• Realize the following Boolean expressions using the 3:8
decoder
• F1(A, B, C)=Ʃ m(1, 2, 3, 4), F2(A, B, C) = Ʃm(3, 5, 7)

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• Seven-Segment Decoders:
• The following Fig shows a seven-segment indicator, i.e.
seven LEDs labeled a through g
• By forward biasing the LEDs, we can display the digits 0
through 9.

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• E.g.: to display the digit 0, we need to light-up the segments
a, b, c, d, e, and f.
• The 7446 & The 7448:
• A seven-segment decoder-driver is an IC decoder that can be
used to drive a seven-segment indicator.
• There are two types of decoder-drivers,
• common-anode (IC 7446) and
• common cathode (IC 7448) indicators.
• Each decoder driver has 4 input pins (the BCD input) and 7
output pins (a through h segments), as shown in the
following Fig.
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• The logic circuits inside 7446 / 7448 convert the BCD input
to the required output.
• If the BCD input is 0111, the internal logic of the 7446 /
7448 will force segments a, b, and c to conduct.
• As a result, digit 7 will appear on the seven-segment
indicator.

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• Encoder: is a digital circuit that performs the inverse
operation of a decoder.
• Figure below shows an 8-to-3 priority encoder with inputs y0
through y7.

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• If input yi is 1 and the other inputs are 0, then the a b c
outputs represent a binary number equal to i.
• E.g.: If y3 =1, then abc = 011.
• If more than one input can be 1 at the same time, the output
can be defined using a priority scheme.
• The truth table for this can be constructed uses the following
scheme:
• If more than one input is 1, the highest numbered input
determines the output
• E.g.: if inputs y1, y4, and y5 are 1, the output is abc = 101
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• Truth table:

• The X’s in the table are don’t-cares;

• E.g.: if y5 is 1, we do not care what inputs y0 through y4 are.
• Output d is 1 if any input is 1, otherwise, d is 0.
• This signal is needed to distinguish the case of all 0 inputs from
the case where only y0 is 1
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• A programmable logic device (or PLD) is a general name for a
digital integrated circuit capable of being programmed to
provide a variety of different logic functions.
• Simple combinational PLDs are capable of realizing from 2 to
10 functions of 4 to 16 variables with a single integrated circuit
• Thus, a single PLD can replace a large number of integrated
circuits, and this leads to lower cost designs.
• When a digital system is designed using a PLD, changes in the
design can easily be made by changing the programming of the
PLD without having to change the wiring in the system.

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• Classification of PLDs

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• Programmable Logic Arrays(PLA) is a design solution to
implement SOP equations.
• It consists of programmable AND array followed by
programmable OR array.
• A PLA with n inputs and m outputs can realize m functions
of n variables as shown in the figure

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• Let us realize the following functions using PLA
• F0 =Ʃ m(0, 1, 4, 6) = A`B` + AC` F1 = Ʃ m(2, 3, 4, 6, 7) = B+ AC`
• F2 = Ʃ m(0, 1, 2, 6) = A`B`+ BC` F3 = Ʃ m(2, 3, 5, 6, 7) = AC + B

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• E.g.: to form A`B`, switching elements are used to connect
the first word line with the A and B lines.
• Switching elements are connected in the OR array to select
the product terms needed for the output functions.
• Because F0 = A`B` + AC`, switching elements are used to
connect the A`B` and AC` lines to the F0 line.
• AND-OR equivalent of the above PLA can be drawn as
shown in the figure

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• The contents of a PLA can be specified by a PLA table as
shown below

• Table specifies the PLA in previous Figure.

• The input side of the table specifies the product terms.
• The symbols 0, l, and – indicate whether a variable is
complemented, not complemented, or not present in the
corresponding product term.
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• Realize the following functions
using PLA:
• 𝑓1=𝑎′𝑏𝑑+𝑎𝑏𝑑+𝑎𝑏′𝑐′+𝑏′𝑐
• 𝑓2=𝑐+𝑎′𝑏𝑑
• 𝑓3=𝑏𝑐+𝑎𝑏′𝑐′ 𝑎𝑏𝑑

• Solution:
• Based on the given expressions, let
us construct a PLA table with one
row for each distinct product term.
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• the PLA structure can be drawn as shown below,

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• This has four inputs, six product terms, and three outputs.
• A dot at the intersection of a word line and an input or output
line indicates the presence of a switching element in the
array.

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• Programmable Array Logic (PAL):
• A PAL is a special case of the PLA in which the AND array
is programmable and the OR array is fixed.
• The following Figure represents a segment of an un-
programmed PAL.

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• Consider the PAL segment used to realize the function
I1I2`+ I`1I2.

• The X’s in the following Figure (b) indicate that 𝐼1 𝑎𝑛𝑑 𝐼2′
lines are connected to the first AND gate, and the 𝐼1`𝑎𝑛𝑑 𝐼2
lines are connected to the other gate. 119
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• Example: Implement Full Adder using PAL. Solution: The
logic equations for the full adder are:
• 𝑆𝑢𝑚=𝑋′𝑌′𝐶𝑖𝑛+𝑋′𝑌𝐶′𝑖𝑛+𝑋𝑌′𝐶′𝑖𝑛+𝑋𝑌𝐶𝑖𝑛
• 𝐶𝑜𝑢𝑡=𝑋𝑌+𝑌𝐶𝑖𝑛+𝑋𝐶𝑖𝑛
• Solution:
• The following Figure shows PAL where each OR gate is
driven by four AND gates. The X’s on the diagram show the
connections that are programmed into the PAL to implement
the full adder equations.

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