CMOS VLSI Design

Lecture 16:
SRAM
Learning Objectives
At the end of this lecture, you should be able to
• Explain the operations of 6T, 12T SRAM using transistor level or gate level diagrams.
• Design random access memories including: Bit cells, Row circuitry, Column circuitry
Multiple ports
• Design serial access memories that can perform operations such as Serial in Parallel out
and Parallel in Serial out.

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Memory Arrays

Memory Arrays

Random Access Memory Serial Access Memory Content Addressable Memory

(CAM)

Read/Write Memory Read Only Memory

Shift Registers Queues
(RAM) (ROM)
(Volatile) (Nonvolatile)

Serial In Parallel In First In Last In

Static RAM Dynamic RAM Parallel Out Serial Out First Out First Out
(SRAM) (DRAM) (SIPO) (PISO) (FIFO) (LIFO)

Mask ROM Programmable Erasable Electrically Flash ROM

ROM Programmable Erasable
(PROM) ROM Programmable
(EPROM) ROM
(EEPROM)

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Array Architecture
• 2n words of 2m bits each
• If n >> m, fold by 2k into fewer rows of more columns

• Good regularity – easy to design

• Very high density if good cells are used

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12T SRAM Cell
• Basic building block: SRAM Cell
• Holds one bit of information, like a latch
• Must be read and written
• 12-transistor (12T) SRAM cell
• Use a simple latch connected to bitline
• 46 x 75 λ unit cell

bit
write

write_b

read

read_b

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6T SRAM Cell
• Cell size accounts for most of array size
• Reduce cell size at expense of complexity
• 6T SRAM Cell
• Used in most commercial chips
• Data stored in cross-coupled inverters
• Read:
• Precharge bit, bit_b
• Raise wordline
• Write:
• Drive data onto bit, bit_b
• Raise wordline

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SRAM Read
• Precharge both bitlines high
• Then turn on wordline
• One of the two bitlines will be pulled down by the cell
• Ex: A = 0, A_b = 1
• bit discharges, bit_b stays high
• But A bumps up slightly
• Read stability
• A must not flip
• N1 >> N2

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SRAM Write
• Drive one bitline high, the other low
• Then turn on wordline
• Bitlines overpower cell with new value
• Ex: A = 0, A_b = 1, bit = 1, bit_b = 0
bit bit_b
• Force A_b low, then A rises high word
P1 P2

• Writability N2
A A_b
N4

• Must overpower feedback inverter N1 N3

• N2 >> P1 A_b

1.5 A

bit_b
1.0

0.5
word

0.0
0 100 200 300 400 500 600 700
time (ps)

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SRAM Sizing
• High bitlines must not overpower inverters during reads
• But low bitlines must write new value into cell

bit bit_b
word
weak
med med
A A_b
strong

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SRAM Column Example
Read Write

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SRAM Layout

• Cell size is critical: 26 x 45 λ (even smaller in industry)

• Tile cells sharing VDD, GND, bitline contacts

GND BIT BIT_B GND

VDD

WORD

Cell boundary

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Thin Cell
• In nanometer CMOS
• Avoid bends in polysilicon and diffusion
• Orient all transistors in one direction
• Lithographically friendly or thin cell layout fixes this
• Also reduces length and capacitance of bitlines

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Commercial SRAMs
• Five generations of Intel SRAM cell micrographs
• Transition to thin cell at 65 nm
• Steady scaling of cell area

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Decoders
• n:2n decoder consists of 2n n-input AND gates
• One needed for each row of memory
• Build AND from NAND or NOR gates

Static CMOS Pseudo-nMOS

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Decoder Layout
• Decoders must be pitch-matched to SRAM cell
• Requires very skinny gates

A3 A3 A2 A2 A1 A1 A0 A0

VDD

word

GND

NAND gate buffer inverter

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Large Decoders
• For n > 4, NAND gates become slow
• Break large gates into multiple smaller gates

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Predecoding
• Many of these gates are redundant
• Factor out common
gates into predecoder
• Saves area
• Same path effort

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Column Circuitry
• Some circuitry is required for each column
• Bitline conditioning
• Sense amplifiers
• Column multiplexing

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Bitline Conditioning
• Precharge bitlines high before reads

• Equalize bitlines to minimize voltage difference when using sense amplifiers

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Sense Amplifiers
• Bitlines have many cells attached
• Ex: 32-kbit SRAM has 128 rows x 256 cols
• 128 cells on each bitline
• tpd ~ (C/I) ∆V
• Even with shared diffusion contacts, 64C of diffusion capacitance (big C)
• Discharged slowly through small transistors (small I)
• Sense amplifiers are triggered on small voltage swing (reduce ∆V)

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Differential Pair Amp
• Differential pair requires no clock
• But always dissipates static power

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Clocked Sense Amp
• Clocked sense amp saves power
• Requires sense_clk after enough bitline swing
• Isolation transistors cut off large bitline capacitance

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Twisted Bitlines
• Sense amplifiers also amplify noise
• Coupling noise is severe in modern processes
• Try to couple equally onto bit and bit_b
• Done by twisting bitlines

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Column Multiplexing
• Recall that array may be folded for good aspect ratio
• Ex: 2 kword x 16 folded into 256 rows x 128 columns
• Must select 16 output bits from the 128 columns
• Requires 16 8:1 column multiplexers

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Tree Decoder Mux
• Column mux can use pass transistors
• Use nMOS only, precharge outputs
• One design is to use k series transistors for 2k:1 mux
• No external decoder logic needed

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Single Pass-Gate Mux
• Or eliminate series transistors with separate decoder

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Ex: 2-way Muxed SRAM

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Multiple Ports
• We have considered single-ported SRAM
• One read or one write on each cycle
• Multiported SRAM are needed for register files
• Examples:
• Multicycle MIPS must read two sources or write a result on some cycles
• Pipelined MIPS must read two sources and write a third result each cycle
• Superscalar MIPS must read and write many sources and results each cycle

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Dual-Ported SRAM
• Simple dual-ported SRAM
• Two independent single-ended reads
• Or one differential write

• Do two reads and one write by time multiplexing

• Read during ph1, write during ph2

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Multi-Ported SRAM
• Adding more access transistors hurts read stability
• Multiported SRAM isolates reads from state node
• Single-ended bitlines save area

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Large SRAMs
• Large SRAMs are split into subarrays for speed
• Ex: UltraSparc 512KB cache
• 4 128 KB subarrays
• Each have 16 8KB banks
• 256 rows x 256 cols / bank
• 60% subarray area efficiency
• Also space for tags & control

[Shin05]

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Serial Access Memories
• Serial access memories do not use an address
• Shift Registers
• Tapped Delay Lines
• Serial In Parallel Out (SIPO)
• Parallel In Serial Out (PISO)
• Queues (FIFO, LIFO)

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Shift Register
• Shift registers store and delay data
• Simple design: cascade of registers
• Watch your hold times!

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Denser Shift Registers
• Flip-flops aren’t very area-efficient
• For large shift registers, keep data in SRAM instead
• Move read/write pointers to RAM rather than data
• Initialize read address to first entry, write to last
• Increment address on each cycle

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Tapped Delay Line
• A tapped delay line is a shift register with a programmable number of stages
• Set number of stages with delay controls to mux
• Ex: 0 – 63 stages of delay

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Serial In Parallel Out
• 1-bit shift register reads in serial data
• After N steps, presents N-bit parallel output

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Parallel In Serial Out
• Load all N bits in parallel when shift = 0
• Then shift one bit out per cycle

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Queues
• Queues allow data to be read and written at different rates.
• Read and write each use their own clock, data
• Queue indicates whether it is full or empty
• Build with SRAM and read/write counters (pointers)

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FIFO, LIFO Queues
• First In First Out (FIFO)
• Initialize read and write pointers to first element
• Queue is EMPTY
• On write, increment write pointer
• If write almost catches read, Queue is FULL
• On read, increment read pointer
• Last In First Out (LIFO)
• Also called a stack
• Use a single stack pointer for read and write

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