Case Study: Intel Processors
By: Dr. M. A. Rouf
Professor, Dept. of CSE, DUET, Gazipur
CMOS VLSI Design
Outline
• Evolution of Intel Microprocessors
– Scaling from 4004 to Pentium 4
– Courtesy of Intel Museum
CMOS VLSI Design
Slide 2
4004
• First microprocessor (1971)
– For Busicom calculator of Nippon
Calculator
• Characteristics
– 10 μm process
– 2300 transistors
– 400 – 800 kHz
– 4-bit word size
– 16-pin DIP package
• Intel 4004 was a part of MCS-4 chipset,
which included the following chips:
– 4001 - 256-bit mask ROM and 4-bit I/O
device,
– 4002 - 320-bit RAM and 4-bit I/O device,
– 4003 - 10-bit shift register,
– 4008 and 4009 - standard memory and
I/O interface set.
CMOS VLSI Design
Slide 3
8008
• 8-bit follow-on (1972)
– Dumb terminals
• Characteristics
– 10 μm process
– 3500 transistors
– 500 – 800 kHz
– 8-bit word size
– 18-pin DIP package
– 16 KB Physical memory
CMOS VLSI Design
Slide 4
8080
• 16-bit address bus (1974)
– Used in Altair computer
• (early hobbyist PC)
• Characteristics
– 6 μm process
– 4500 transistors
– 2 MHz
– 8-bit word size
– 40-pin DIP package
CMOS VLSI Design
Slide 5
8086 / 8088
• 16-bit processor (1978-9)
– IBM PC and PC XT
– Revolutionary products
– Introduced x86 ISA
• Characteristics
– 3 μm process
– 29k transistors
– 5-10 MHz
– 16-bit word size
– 40-pin DIP package
• Microcode ROM
CMOS VLSI Design
Slide 6
80286
• Virtual memory (1982)
– IBM PC AT
• Characteristics
– 1.5 μm process
– 134k transistors
– 6-12 MHz
– 16-bit word size
– 68-pin PGA
• Regular datapaths and
ROMs
Bitslices clearly visible
CMOS VLSI Design
Slide 7
80386
• 32-bit processor (1985)
– Modern x86 ISA
• Characteristics
– 1.5-1 μm process
– 275k transistors
– 16-33 MHz
– 32-bit word size
– 100-pin PGA
• 32-bit datapath,
microcode ROM,
synthesized control
CMOS VLSI Design
Slide 8
80486
• Pipelining (1989)
– Floating point unit
– 8 KB cache
• Characteristics
– 1-0.6 μm process
– 1.2M transistors
– 25-100 MHz
– 32-bit word size
– 168-pin PGA (Pin Grid Array)
• Cache, Integer datapath,
FPU, microcode,
synthesized control
CMOS VLSI Design
Slide 9
Pentium
• Superscalar (1993)
– 2 instructions per cycle
– Separate 8KB I$ & D$
• Characteristics
– 0.8-0.35 μm process
– 3.2M transistors
– 60-300 MHz
– 32-bit word size
– 296-pin PGA
• Caches, datapath,
FPU, control
CMOS VLSI Design
Slide 10
Pentium Pro / II / III
• Dynamic execution (1995-9)
– 3 micro-ops / cycle
– Out of order execution
– 16-32 KB I$ & D$
– Multimedia instructions
– PIII adds 256+ KB L2$
• Characteristics
– 0.6-0.18 μm process
– 5.5M-28M transistors
– 166-1000 MHz
– 32-bit word size
– MCM / SECC
CMOS VLSI Design
Slide 11
Pentium 4
• Deep pipeline (2001)
– Very fast clock
– 256-1024 KB L2$
• Characteristics
– 180 – 90 nm process
– 42-125M transistors
– 1.4-3.4 GHz
– 32-bit word size
– 478-pin PGA
• Units start to become
invisible on this scale
CMOS VLSI Design
Slide 12
Summary
• 104 increase in transistor count, clock
frequency over 30 years!
CMOS VLSI Design
Slide 13