Introduction to

CMOS VLSI
Design

Lecture 21:
Scaling and Economics

Amit Kumar Singh

Assistant Professor
ECE Dept., BCE Bhagalpur
Scaling and Economics Slide 1
 Outline
 Scaling
– Transistors
– Interconnect
– Future Challenges
 VLSI Economics

Scaling and Economics CMOS VLSI Design Slide 2

 Moore’s Law
 In 1965, Gordon Moore predicted the exponential
growth of the number of transistors on an IC
 Transistor count doubled
every year since invention
 Predicted > 65,000
transistors by 1975!
 Growth limited by power

[Moore65]

Scaling and Economics CMOS VLSI Design Slide 3

 More Moore
 Transistor counts have doubled every 26 months for
the past three decades.
1,000,000,000

100,000,000
Pentium 4
Pentium III
10,000,000 Pentium II
Pentium Pro
Transistors

Pentium
Intel486
1,000,000
Intel386
80286
100,000
8086
10,000 8080
8008
4004
1,000

1970 1975 1980 1985 1990 1995 2000

Year

Scaling and Economics CMOS VLSI Design Slide 4

 Speed Improvement
 Clock frequencies have also increased exponentially
– A corollary of Moore’s Law
10,000

1,000 4004

8008

8080
Clock Speed (MHz)

100 8086

80286

Intel386

10 Intel486

Pentium

Pentium Pro/II/III

1 Pentium 4

1970 1975 1980 1985 1990 1995 2000 2005

Year

Scaling and Economics CMOS VLSI Design Slide 5

 Why?
 Why more transistors per IC?

 Why faster computers?

Scaling and Economics CMOS VLSI Design Slide 6

 Why?
 Why more transistors per IC?
– Smaller transistors
– Larger dice
 Why faster computers?

Scaling and Economics CMOS VLSI Design Slide 7

 Why?
 Why more transistors per IC?
– Smaller transistors
– Larger dice
 Why faster computers?
– Smaller, faster transistors
– Better microarchitecture (more IPC)
– Fewer gate delays per cycle

Scaling and Economics CMOS VLSI Design Slide 8

 Scaling
 The only constant in VLSI is constant change
 Feature size shrinks by 30% every 2-3 years
– Transistors become cheaper
– Transistors become faster
– Wires do not improve 10
10

(and may get worse)

6

Feature Size (m)

3

1.5
 Scale factor S 1
1
0.8
0.6

– Typically S  2
0.35
0.25
0.18
0.13
0.09

– Technology nodes 0.1

1965 1970 1975 1980 1985 1990 1995 2000 2005

Year

Scaling and Economics CMOS VLSI Design Slide 9

 Scaling Assumptions
 What changes between technology nodes?
 Constant Field Scaling
– All dimensions (x, y, z => W, L, tox)
– Voltage (VDD)
– Doping levels
 Lateral Scaling
– Only gate length L
– Often done as a quick gate shrink (S = 1.05)

Scaling and Economics CMOS VLSI Design Slide 10

 Device Scaling

Scaling and Economics CMOS VLSI Design Slide 11

 Device Scaling

Scaling and Economics CMOS VLSI Design Slide 12

 Device Scaling

Scaling and Economics CMOS VLSI Design Slide 13

 Device Scaling

Scaling and Economics CMOS VLSI Design Slide 14

 Device Scaling

Scaling and Economics CMOS VLSI Design Slide 15

 Device Scaling

Scaling and Economics CMOS VLSI Design Slide 16

 Device Scaling

Scaling and Economics CMOS VLSI Design Slide 17

 Device Scaling

Scaling and Economics CMOS VLSI Design Slide 18

 Device Scaling

Scaling and Economics CMOS VLSI Design Slide 19

 Device Scaling

Scaling and Economics CMOS VLSI Design Slide 20

 Device Scaling

Scaling and Economics CMOS VLSI Design Slide 21

 Device Scaling

Scaling and Economics CMOS VLSI Design Slide 22

 Observations
 Gate capacitance per micron is nearly independent
of process
 But ON resistance * micron improves with process

 Gates get faster with scaling (good)

 Dynamic power goes down with scaling (good)
 Current density goes up with scaling (bad)

 Velocity saturation makes lateral scaling

unsustainable

Scaling and Economics CMOS VLSI Design Slide 23

 Example
 Gate capacitance is typically about 2 fF/m
 The FO4 inverter delay in the TT corner for a
process of feature size f (in nm) is about 0.5f ps
 Estimate the ON resistance of a unit (4/2 )
transistor.

Scaling and Economics CMOS VLSI Design Slide 24

 Solution
 Gate capacitance is typically about 2 fF/m
 The FO4 inverter delay in the TT corner for a
process of feature size f (in nm) is about 0.5f ps
 Estimate the ON resistance of a unit (4/2 )
transistor.

 FO4 = 5  = 15 RC
 RC = (0.5f) / 15 = (f/30) ps/nm
 If W = 2f, R = 8.33 k
– Unit resistance is roughly independent of f

Scaling and Economics CMOS VLSI Design Slide 25

 Scaling Assumptions
 Wire thickness
– Hold constant vs. reduce in thickness
 Wire length
– Local / scaled interconnect
– Global interconnect
• Die size scaled by Dc  1.1

Scaling and Economics CMOS VLSI Design Slide 26

 Interconnect Scaling

Scaling and Economics CMOS VLSI Design Slide 27

 Interconnect Scaling

Scaling and Economics CMOS VLSI Design Slide 28

 Interconnect Scaling

Scaling and Economics CMOS VLSI Design Slide 29

 Interconnect Scaling

Scaling and Economics CMOS VLSI Design Slide 30

 Interconnect Scaling

Scaling and Economics CMOS VLSI Design Slide 31

 Interconnect Scaling

Scaling and Economics CMOS VLSI Design Slide 32

 Interconnect Scaling

Scaling and Economics CMOS VLSI Design Slide 33

 Interconnect Scaling

Scaling and Economics CMOS VLSI Design Slide 34

 Interconnect Scaling

Scaling and Economics CMOS VLSI Design Slide 35

 Interconnect Delay

Scaling and Economics CMOS VLSI Design Slide 36

 Interconnect Delay

Scaling and Economics CMOS VLSI Design Slide 37

 Interconnect Delay

Scaling and Economics CMOS VLSI Design Slide 38

 Interconnect Delay

Scaling and Economics CMOS VLSI Design Slide 39

 Interconnect Delay

Scaling and Economics CMOS VLSI Design Slide 40

 Interconnect Delay

Scaling and Economics CMOS VLSI Design Slide 41

 Interconnect Delay

Scaling and Economics CMOS VLSI Design Slide 42

 Observations
 Capacitance per micron is remaining constant
– About 0.2 fF/m
– Roughly 1/10 of gate capacitance
 Local wires are getting faster
– Not quite tracking transistor improvement
– But not a major problem
 Global wires are getting slower
– No longer possible to cross chip in one cycle

Scaling and Economics CMOS VLSI Design Slide 43

 ITRS
 Semiconductor Industry Association forecast
– Intl. Technology Roadmap for Semiconductors

Scaling and Economics CMOS VLSI Design Slide 44

 Scaling Implications
 Improved Performance
 Improved Cost
 Interconnect Woes
 Power Woes
 Productivity Challenges
 Physical Limits

Scaling and Economics CMOS VLSI Design Slide 45

 Cost Improvement
 In 2003, $0.01 bought you 100,000 transistors
– Moore’s Law is still going strong

[Moore03]

Scaling and Economics CMOS VLSI Design Slide 46

 Interconnect Woes
 SIA made a gloomy forecast in 1997
– Delay would reach minimum at 250 – 180 nm,
then get worse because of wires
 But…

[SIA97]

Scaling and Economics CMOS VLSI Design Slide 47

 Interconnect Woes
 SIA made a gloomy forecast in 1997
– Delay would reach minimum at 250 – 180 nm,
then get worse because of wires
 But…
– Misleading scale
– Global wires
 100 kgate blocks ok

Scaling and Economics CMOS VLSI Design Slide 48

 Reachable Radius
 We can’t send a signal across a large fast chip in
one cycle anymore
 But the microarchitect can plan around this
– Just as off-chip memory latencies were tolerated

Chip size

Scaling of
reachable radius

Scaling and Economics CMOS VLSI Design Slide 49

 Dynamic Power
 Intel VP Patrick Gelsinger (ISSCC 2001)
– If scaling continues at present pace, by 2005,
high speed processors would have power density
of nuclear reactor, by 2010, a rocket nozzle, and
by 2015, surface of sun.
– “Business as usual will not work in the future.”
 Intel stock dropped 8%
on the next day
 But attention to power is
increasing
[Moore03]

Scaling and Economics CMOS VLSI Design Slide 50

 Static Power
 VDD decreases
– Save dynamic power
– Protect thin gate oxides and short channels
– No point in high value because of velocity sat.
 Vt must decrease to
maintain device performance Dynamic

 But this causes exponential

increase in OFF leakage Static

 Major future challenge

[Moore03]

Scaling and Economics CMOS VLSI Design Slide 51

 Productivity
 Transistor count is increasing faster than designer
productivity (gates / week)
– Bigger design teams
• Up to 500 for a high-end microprocessor
– More expensive design cost
– Pressure to raise productivity
• Rely on synthesis, IP blocks
– Need for good engineering managers

Scaling and Economics CMOS VLSI Design Slide 52

 Physical Limits
 Will Moore’s Law run out of steam?
– Can’t build transistors smaller than an atom…
 Many reasons have been predicted for end of scaling
– Dynamic power
– Subthreshold leakage, tunneling
– Short channel effects
– Fabrication costs
– Electromigration
– Interconnect delay
 Rumors of demise have been exaggerated

Scaling and Economics CMOS VLSI Design Slide 53

 VLSI Economics
 Selling price Stotal
– Stotal = Ctotal / (1-m)
 m = profit margin
 Ctotal = total cost
– Nonrecurring engineering cost (NRE)
– Recurring cost
– Fixed cost

Scaling and Economics CMOS VLSI Design Slide 54

 NRE
 Engineering cost
– Depends on size of design team
– Include benefits, training, computers
– CAD tools:
• Digital front end: $10K
• Analog front end: $100K
• Digital back end: $1M
 Prototype manufacturing
– Mask costs: $500k – 1M in 130 nm process
– Test fixture and package tooling

Scaling and Economics CMOS VLSI Design Slide 55

 Recurring Costs
 Fabrication
– Wafer cost / (Dice per wafer * Yield)
– Wafer cost: $500 - $3000
2
– Dice per wafer: N     2r 
 r
A 2A 

– Yield: Y = e-AD
• For small A, Y  1, cost proportional to area
• For large A, Y  0, cost increases exponentially
 Packaging
 Test

Scaling and Economics CMOS VLSI Design Slide 56

 Fixed Costs
 Data sheets and application notes
 Marketing and advertising
 Yield analysis

Scaling and Economics CMOS VLSI Design Slide 57

 Example
 You want to start a company to build a wireless
communications chip. How much venture capital
must you raise?

 Because you are smarter than everyone else, you

can get away with a small team in just two years:
– Seven digital designers
– Three analog designers
– Five support personnel

Scaling and Economics CMOS VLSI Design Slide 58

 Solution
 Digital designers:  Support staff
– salary – salary
– overhead – overhead
– computer – computer
– CAD tools – Total:
– Total:  Fabrication
 Analog designers – Back-end tools:
– salary – Masks:
– overhead – Total:
– computer  Summary
– CAD tools
– Total:

Scaling and Economics CMOS VLSI Design Slide 59

 Solution
 Digital designers:  Support staff
– $70k salary – $45k salary
– $30k overhead – $20k overhead
– $10k computer – $5k computer
– $10k CAD tools – Total: $70k * 5 = $350k
– Total: $120k * 7 = $840k  Fabrication
 Analog designers – Back-end tools: $1M
– $100k salary – Masks: $1M
– $30k overhead – Total: $2M / year
– $10k computer  Summary
– $100k CAD tools – 2 years @ $3.91M / year
– Total: $240k * 3 = $720k – $8M design & prototype

Scaling and Economics CMOS VLSI Design Slide 60

 Cost Breakdown
 New chip design is fairly capital-intensive
 Maybe you can do it for less?
fab salary
25% 26%

25%
11%
4%
9% overhead

backendtools
computer

entry tools

Scaling and Economics CMOS VLSI Design Slide 61