EEE 3571 Electronic Engineering I

Lecture 4: DC Biasing of BJTs

Mr. G. Ziba
Email: [email protected]

University of Zambia
School of Engineering,
Department of Electrical & Electronic Engineering
 4.1 Introduction
 The analysis or design of a transistor amplifier requires knowledge of both the
dc and ac response of the system.
 In transistor networks, any increase in ac voltage, current, or power is the result
of a transfer of energy from the applied dc supplies.
 The superposition theorem is used to determine dc and ac responses separately,
so that their summation yields the total response.
 In design or synthesis, once the desired dc current and voltage levels have been
defined, a network must be constructed that will establish the desired operating
point.
 The analysis will chiefly exploit the following basic relationships:
V B E  0.7 V [4.1]

I E    1 I B  I C [4.2]

IC   I B [4.3]

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 4.2 Operating Point
 For transistor amplifiers
the applied biasing dc
voltages establish a fixed
level of current and
voltage on the
characteristics for small-
signal amplification.
 The fixed point
established is called the
quiescent point (Q-point).
 The BJT device biased to
operate outside the
maximum limits
culminates in shortened
Figure 4.1: Various operating points within lifetime or destruction of
the limits of operation of a transistor. the device.

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 4.3 Fixed-Bias Configuration
 Shown is the simplest npn transistor dc bias configuration.

Figure 4.2: (a) Fixed-bias circuit; (b) Dc equivalent of Fig. 4.2.

 For dc analysis the network is isolated from ac levels by replacing the
capacitors with open circuits.
 It follows from capacitive reactance, given f  0 H z , yields
X C  1 2 fC  1 2 0  C   
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 4.3 Fixed-Bias Configuration Cont’d
Forward Bias of Base-Emitter
 Consider first the base-emitter circuit loop of Fig. 4.3. Applying KVL yields
 V CC  I B R B  V BE  0
 Solving the equation for I B yields
V CC  V B E
IB  [4.4]
RB

Collector-Emitter Loop
 Recall that,
Figure 4.3:
Base-emitter IC   I B [4.5]
loop.
 Note that changing R C to
Figure 4.4:
any level will not affect the
Collector-emitter level of I B or I C so long
loop. this is within the active region.

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 4.3 Fixed-Bias Configuration Cont’d
 Applying KVL to Fig. 4.4 yields
V CE  I C R C  V CC  0 ;  V CE  V CC  I C R C [4.6]

 Vividly, V CE in fixed bias configuration is the supply voltage less the drop
across R C .
 Recall that, V CE  V C  V E [4.7]

 Since V E  0 V , we have V CE  V C [4.8]

 Furthermore, V BE  V B  V E [4.9]

 Since V E  0 V , we have V BE  V B [4.10]

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 Example 4.1 Fixed-Bias Configuration
 Determine the following for the fixed-bias configuration of Fig. 4.5.
a) I B and I C .
[Solution]
Q Q

b) V CE . Q V CC  V BE 12 V  0.7 V
c) V B and V C . a) Eq. [4.4]: I BQ   ;
RB 240 k 
d) V B C .
I B Q  47.08  A

Eq. [4.5]: I CQ   I BQ  50 47.08  A  ;

I CQ  2.35 m A

b) Eq. [4.6]: V CE Q  V CC  I C R C ;
V CE Q  12 V  2.35 m A 2.2 k   ;
V CE Q  6.83 V
Figure 4.5: DC fixed-bias circuit for Ex. 4.1.

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 Example 4.1 Fixed-Bias Configuration
Cont’d
b) Eqs. [4.10] and [4.8]: V B  V B E  0.7 V
V C  V CE  6.83 V

c) Using double-subscript notation yields

V B C  V B  V C  0.7 V  6.83 V ; V B C  6.13 V

d) The negative sign reveals that the junction is reverse-biased, as it should be

for linear amplification.

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 4.3 Fixed-Bias Configuration Cont’d
Transistor Saturation
 The term saturation is applied to any system where levels have reached their
maximum values.
 For a transistor operating in the saturation region, the current is a maximum
value for the particular design.  Fig. 4.6a depicts an
operating point in the
saturation region.
 Note that in this region
the characteristic curves
join and V CE  V CE . sa t

 Let Fig. 4.6a be

approximated by Fig.
4.6b. Clearly, the current
is relatively high and
Figure 4.6: Saturation regions: (a) actual; (b) assume V CE  0 V .
approximate.
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 4.3 Fixed-Bias Configuration Cont’d
 Exploiting Ohm’s law, we determine the resistance between collector and
emitter terminals as follows:
V 0V
R CE  CE  0 
IC I Csa t
 For the future, to know the approximate
maximum collector current (saturation level) for
a particular design, simply insert a short-circuit
equivalent between collector and emitter of the
BJT and calculate I C . sa t
Figure 4.7: Determining I C  For the fixed-bias configuration of Fig. 4.7,
sa t
for the fixed-bias configuration.
having applied the short-circuit, it follows that
V CC
I C ,sa t  [4.11]
RC

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 4.3 Fixed-Bias Configuration Cont’d
Load-Line Analysis
 The characteristics of the BJT are superimposed on a plot of the network
equation defined by the same axis parameters called dc load-line.
 From Fig. 4.8a an
output equation that
relates I C and V CE
is given by
V CE  V CC  I C R C
[4.12]
 Notice that the load
resistor R C
determines the slope
of the load-line.
Figure 4.8: Load-line analysis: (a) the network; (b) the device
characteristics..
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 4.3 Fixed-Bias Configuration Cont’d
 Co-plotting the load-line and output characteristic is aided by the fact that each
case relates I C and V CE .
 Let I C  0 m A , it follows that
V CE  V CC  0  R C ;
V CE  V CC I C 0 m A
[4.13]

 Furthermore, let V CE  0 V so that,

0  V CC  I C R C ;
V CC
IC  [4.14]
RC V CE  0 V

 The point of intersection is

Figure 4.9: Fixed-bias load line.
Quiescent point (Q-point).

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 4.3 Fixed-Bias Configuration Cont’d
 The level of I B is changed by varying the value of R B the effect of which is
depicted in Fig. 4.10.

Figure 4.10: Movement of Q-point with Figure 4.11: Effect of an increasing level
increasing level of I B . of R C on the load line and the Q-point.
 Holding V CC constant, if R C is increased, the load line will shift (less steep
slope) as shown in Fig. 4.11.
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 4.3 Fixed-Bias Configuration Cont’d
 Holding R C constant, if V CC is decreased, the load line will shift (same
slope) as shown in Fig. 4.12.

Figure 4.12: Effect of lower values of V CC

on the load line and the Q-point.

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 Example 4.2 Fixed-Bias Configuration
 Given the load line of Fig. 4.13 and the defined Q-point, determine the required
values of V CC , R C , and R B for a fixed-bias configuration.
[Solution]
 From Fig. 4.13,
V CE  V CC  20 V ; at I C  0 m A
V CC
IC  ; at V CE  0 V
RC
 Thus, we have
V 20 V
R C  CC   2 kΩ
I C 10 m A
V CC  V B E
Figure 4.13: Example 4.2. IB  ;
RB
 It follows that, V  V B E 20 V  0.7 V
R B  CC   772 k Ω
IB 25  A
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 4.4 Emitter-Bias Configuration
 The emitter resistor in Fig. 4.14 helps to improve the stability level over that of
fixed-bias configuration.  The more stable a configuration, the less
its response will change due to
undesirable changes in temperature and
parameter variations.
 The DC equivalent circuit for Fig. 4.14
is shown in Fig. 4.15.

Figure 4.14: BJT bias circuit with

emitter resistor.

Figure 4.15: DC
equivalent of Fig. 4.14.
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 4.4 Emitter-Bias Configuration Cont’d
Base-Emitter Loop
 The circuit of Fig. 4.15 is redrawn in Fig. 4.16.
Exploiting KVL yields
 V CC  I B R B  V B E  I E R E  0 [4.15]

 Recall that, I E    1  I B [4.16]

 Substituting for I E in Eq. [4.15] yields,

 V CC  I B R B  V B E     1  I B R E  0
Figure 4.16: Base-emitter  It follows that,
loop.
 I B  R B     1  R E   V CC  V BE  0 ;
 I B  R B     1  R E   V CC  V BE ;
V CC  V B E
IB  [4.17]
R B    1  R E
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 4.4 Emitter-Bias Configuration Cont’d
 Notice the difference between Eq. [4.17] and that obtained for the fixed-bias
configuration is the term   1  R E .
 Eq. [4.17] is used to sketch a series network of Fig.
4.17.
 The resistor R E is reflected back to the input base
circuit by a factor   1  .
 In general, therefore, for the configuration of Fig. 4.18,

Figure 4.17:
R i    1  R E [4.18]
Network derived
from Eq. [4.17].

Figure 4.18:
Reflected
impedance
level of R E .
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 4.4 Emitter-Bias Configuration Cont’d
Collector-Emitter loop
 Applying KVL to the loop of Fig. 4.19 yields
 I E R E  V CE  I C R C  V CC  0
 Substituting I E  I C and grouping terms gives
V CE  V CC  I C  R C  R E   0

 Thus, V CE  V CC  I C  R C  R E  [4.19]

 The single-subscript voltage V E is the voltage from

emitter to ground and is determined by
Figure 4.19: VE  I E RE
Collector-emitter
[4.20]
loop.  The voltage from collector to ground is found using
V  V V ; V C  V CE  V E [4.21]
CE C E

 Thus, V C  V CC  I C R C [4.22]
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 4.4 Emitter-Bias Configuration Cont’d
 The voltage at the base with respect to ground is obtained using Fig. 4.15 as
V B  V CC  I B R B [4.23]
 It follows that, V B  V BE  V E [4.24]

Example 4.3 Emitter-Bias Configuration

 For the emitter-bias network of
Fig. 4.20, determine:
a) I B . g) V B C
b) I C .
c) V CE .
d) V C . Figure 4.20: Emitter-
stabilized circuit for
e) V E .
Example 4.4
f) V B .

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 Example 4.3 Emitter-Bias Configuration
Cont’d
[Solution]
V CC  V B E 20 V  0.7 V 19.3 V
a) Eq. [4.17]: IB    ;
R B     1  R E 430 k   51 1 k   481 k 
I B  40.1 μ A
b) I C   I B  50 40.1  A  ; I C  2.01 m A
c) Eq. [4.19]: V CE  V CC  I C  R C  R E   20 V  2.01 m A 2 k   1 k   ;
V CE  20 V  6.03 V  13.97 V
d) V C  V CC  I C R C  20 V  2.01 m A 2 k    20 V  4.02 V ;
V C  15.98 V
e) V E  V C  V CE  15.98 V  13.97 V  2.01 V
Alternatively, V E  I E R E  I C R E  2.01 m A 1 k    2.01 V
f) V B  V B E  V E  0.7 V  2.01 V  2.71 V
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 Example 4.3 Emitter-Bias Configuration
Cont’d
f) V B C  V B  V C  2.71 V  15.98 V  13.27 V (reverse-biased as
required)
Improved Bias Stability
 The emitter resistor added to the dc bias
of the BJT provides improved stability
in that, the dc bias currents and voltages
remain closer to where they were set by
circuit when outside conditions, such as Figure 4.21:
temperature and transistor beta, change. Determining I Csa t
for the emitter-
Saturation Level stabilized bias
 The collector saturation level or circuit.
maximum collector current for an
emitter-bias design is determined by V CC
I Csa t  [4.25]
applying a short-circuit in Fig. 4.21. It RC  R E
follows that,
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 4.4 Emitter-Bias Configuration Cont’d
Load-Line Analysis
 The load-line analysis of the emitter-
bias network is only slightly different
from that of fixed-bias design.
 Thus, the collector-emitter loop
equation that defines the load line is
V CE  V CC  I C  R C  R E 
 Let I C  0 m A , it follows that
V CE  V CC  0  R C  R E  ;
Figure 4.22: Load line for the
emitter-bias configuration. V CE  V CC I C 0 m A [4.26]
 Furthermore, let V CE  0 V so that,
V CC
0  V CC  I C  R C  R E  ; IC  [4.27]
RC  R E V CE 0 V

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 4.5 Voltage-Divider Bias Configuration
 Thus far, in the bias designs we have discussed the bias current I C and Q

voltage V CE were a function of the current gain  of the transistor.

Q

 However, beta is temperature sensitive, especially for silicon transistors, thus

its actual value is usually not well defined.
 To mitigate this beta dependence problem the voltage-divider bias design of
Fig. 4.23 can be used.

Figure 4.23: Voltage-divider bias Figure 4.24: Defining the Q-point for the
configuration. voltage-divider bias configuration.
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 4.5 Voltage-Divider Bias Configuration
Cont’d
Exact Analysis
 For dc analysis Fig. 4.23 is redrawn as shown in Fig.
4.25. The input side is further redrawn in Fig. 4.26.
 The Thevenin equivalent circuit to the left of the base
terminal is found as follows:
 To find R Th , short circuit the voltage source so that,

R Th  R1 R 2 [4.28]

Figure 4.25:
DC components of
the voltage-divider
bias design.

Figure 4.26: Redrawing the input

side of the network of Fig. 4.25. Figure 4.27: Determining R Th .

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 4.5 Voltage-Divider Bias Configuration
Cont’d
 The open-circuit Thevenin voltage E Th is
determined with voltage source V CC returned to
the network, see Fig. 4.28. Applying voltage
divider rule yields
R 2V CC
E Th  V R 2  [4.29]
R1  R 2
Figure 4.28:
Determining E Th .  Thus, the Thevenin network is redrawn in Fig.
4.34, and I B can be determined by applying
Q

KVL, that is
E Th  I B R T h  V B E  I E R E  0 ;
 Substituting I E    1  I B yields,
E Th  V BE
I B  V R2  [4.30]
Figure 4.29: Inserting the R Th     1  R E
Thevenin equivalent circuit.
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 4.5 Voltage-Divider Bias Configuration
Cont’d
 Once I B is known, the remaining quantities of the network can be found in the
same manner as for the emitter-bias configuration. That is,
V CE  V CC  I C  R C  R E  [4.31]

Example 4.4 Voltage-Divider Bias

Configuration
 Determine the dc bias voltage V CE and
the current I C for the voltage divider
configuration of Fig. 4.30.
[Solution] Eq. [4.28]:
R R R 
 39 k  3.9 k  
 3.55 k 
Th 1 2
39 k   3.9 k 
Figure 4.30: Beta-stabilized
circuit for Example 4.4.
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 Example 4.4 Voltage-Divider Bias
Configuration
R 2V CC 3.9 k  22 V 
Eq. [4.29]: E  Th   2V
R1  R 2 39 k   3.9 k 
E Th  V B E 2 V  0.7 V
Eq. [4.30]: IB    8.38  A
R Th     1  R E 3.55 k   101 1.5 k  
I C   I B  100 8.38  A   0.84 m A

Eq. [4.31]: V CE V CC  I C  R C  R E  22 V  0.84 m A 10 k   1.5 k   ;

V CE  12.34 V

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 4.5 Voltage-Divider Bias Configuration
Cont’d
Approximate Analysis
 The input section of the voltage-divider configuration can be represented by the
circuit of Fig. 4.31.
 Recall that R i    1  R E is the reflected resistance between base and
emitter. Ri ? R2 I B I 2 I 2  I1
 Furthermore, such that , thus .
 With the approximation above the base
voltage V B is thus,
R 2V CC
VB  [4.32]
R1  R 2
 Since R i     1  R E   R E the
condition to be met for the approximate
analysis to hold is
Figure 4.31: Partial-bias circuit for
 R E  10 R 2 [4.33]
calculating the approximate base
voltage V B .
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 4.5 Voltage-Divider Bias Configuration
Cont’d
 Simply put, if the condition in Eq. [4.33] is met the approximate approach can
be applied with a high degree of accuracy.
 Once V B is determined, the level of V E can be calculated from
V E  V B  V BE [4.34]
 The emitter current can be determined from
VE
IE  [4.35]
RE
 It follows also that
I CQ  I E [4.36]
 The collector-emitter voltage is determined by
V CE V CC  I C R C  I E R E ;

 But I E  I C , thus V CE Q  V CC  I C  R C  R E  [4.37]

 Note: the determination of I C and V CE is independent of  .
30
Q Q

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 Example 4.5 Voltage-Divider Bias
Configuration
 Determine the levels of I C and V CE
Q Q

for the voltage-divider configuration

of Fig. 4.32 using the exact and
approximate techniques and compare
solutions.
 In this case, the conditions of Eq.
[4.33] will not be satisfied and the
results will reveal the difference in
solution if the criterion of Eq. [4.33] is
ignored.
Figure 4.32: Voltage-divider
configuration for Example 4.5. [Solution]
 Exact analysis: Eq. [4.33]:  R E  10 R 2
 50 1.2 k    10 22 k   ; 60 k  Not greater or equal to 220 k 
R Th  R1 R 2  82 k  22 k  17.35 k 
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 Example 4.5 Voltage-Divider Bias
Configuration Cont’d
RV 22 k  18 V 
E Th  2 CC   3.81 V
R1  R 2 82 k   22 k 
E Th  V B E 3.81 V  0.7 V 3.11 V
IB     39.6  A
R Th     1  R E 17.35 k   51 1.2 k   78.55 k 
I CQ   I B  50 39.6  A  ; I CQ  1.98 m A
V CE Q  V CC  I C  R C  R E   18 V  1.98 m A 5.6 k   1.2 k   ;

V CE Q  4.54 V

 Approximate analysis: V B  E Th  3.81 V

V E  V B  V B E  3.81 V  0.7 V  3.11 V
V E 3.11 V I CQ  2.59 m A
I CQ  I E   ;
R E 1.2 k 

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 Example 4.5 Voltage-Divider Bias
Configuration Cont’d
V CE Q  V CC  I C  R C  R E   18 V  2.59 m A 5.6 k   1.2 k   ;
V CE Q  3.88 V

Transistor Saturation
 The output collector-emitter circuit for the voltage-divider configuration has the
same appearance as the emitter-biased circuit. Thus, the resulting equation for
saturation current given that V CE  0 V is
V CC
I Csa t  I C ,m a x  [4.38]
RC  R E

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 4.5 Voltage-Divider Bias Configuration
Cont’d
Load-Line Analysis
 Similarities with the output circuit of the emitter-biased configuration result in
the same intersections for the load line of the voltage-divider configuration, i.e.,
V CE  V CC I C 0 m A [4.39]

V CC
IC  [4.40]
and RC  R E V CE 0 V

 Notice that the level of I B is determined by a different equation for the voltage-
divider bias and the emitter-bias configurations.

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 4.6 Collector Feedback Configuration
 An improved level of stability is also obtained by introducing a feedback path
from collector to base as shown in Fig. 4.33.
 The analysis is
conducted as has
been done
previously.
 Perform base-
emitter loop and
apply the results
to the collecter-
emitter loop.
Figure 4.33: DC bias circuit Figure 4.34: Base-emitter
with voltage feedback. loop for the network of
Base-Emitter Loop Fig. 4.33.
 KVL yields: V CC  I C R C  I B R F  V B E  I E R E  0
 But, I C  I C  I B ; thus substituting I C  I C   I B and I E  I C gives

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 4.6 Collector Feedback Configuration
Cont’d
V CC   I B R C  I B R F  V BE   I B R E  0
 V CC  V B E   I B  R C  R E   I B R F  0 ;
 Solving for I B yields V CC  V B E
IB  [4.41]
R F   RC  R E 

Collector-Emitter Loop
 KVL applied to Fig. 4.35 yields:
I E R E  V CE  I C R C  V CC  0

 Since I C  I C and I E  I C , we have

V CE  V CC  I C  R C  R E  [4.42]

Figure 4.35: Collector-  Exactly as was obtained for the emitter-bias and
emitter loop for the network voltage-divider bias configurations.
of Fig. 4.33.
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 4.6 Collector Feedback Configuration
Cont’d
Saturation Conditions
 By the approximation I C  I C , we find that the equation for saturation
current is the same as that of voltage-divider and emitter-bias configurations.
V CC
I Csat  I C ,m a x  [4.43]
RC  R E

Load-Line Analysis
 Continuing to let I C  I C yields the same load line as was obtained for the last
two configurations.

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 4.7 Emitter-Follower Configuration
 Here the output is taken off the
emitter terminal.

Figure 4.36: Common-collector (emitter- Figure 4.37:

follower) configuration. dc equivalent
of Fig. 4.36.
 Applying Kirchhoff’s voltage law to
the input circuit yields
 I B R B  V BE  I E R E  V E E  0 ; but I E    1  I B ;
V EE  V BE
 I B R B    1  I B R E  VEE  VBE ; IB  [4.44]
R B    1  R E
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 4.7 Emitter-Follower Configuration Cont’d
 For the output network, exploiting Kirchhoff’s voltage law yields
V CE  I E R E  V E E  0 ;  V CE  V E E  I E R E [4.45]

Example 4.6 Emitter-Follower Configuration

 Determine V CE and I E for the
Q Q

network of Fig. 4.38.

[Solution]
V EE  V BE
 Eq. 4.44: I B  ;
R B    1 R E
20 V  0.7 V
IB  ;
240 k   90  1  240 k 
Figure 4.38: Example 4.6.
19.3 V
IB   45.73  A
422 k 
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Example 4.6 Emitter-Follower Configuration
Cont’d
and Eq. 4.45: V CE Q  V E E  I E R E  V E E    1  I B R E ;
V CE Q  20 V  90  1 45.73  A 2 k    20 V  8.32 V ;

V CE Q  11.68 V

 It follows that,
I E Q     1  I B  90  1 45.73  A  ; I E Q  4.16 m A

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 4.8 Common-Base Configuration
 Is unique in that the applied signal is connected to the emitter terminal and the
base is at, or just above, ground potential.
 In the ac domain it has a very low input impedance, high output impedance,
and good gain.

Figure 4.40:
Input dc
equivalent of
Figure 4.39: Common-base configuration.
Fig. 4.39.
 Applying Kirchhoff’s voltage law to the input circuit yields
V EE  V BE
V EE  I E R E  V BE  0 ;  IE  [4.46]
RE

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 4.8 Common-Base Configuration Cont’d
 Applying Kirchhoff’s voltage law to the entire
outside perimeter of the circuit of Fig. 4.41
yields
V EE  I E R E  V CE  I C R C  VCC  0 ;
 V CE  V E E  V CC  I E R E  I C R C  0 ;
 Let I E  I C so that,
Figure 4.41: Determining V CE
and V CB . V CE  V B E  V CC  I E  R C  R E  [4.47]

 Applying KVL to the output loop of Fig. 4.41 gives

V CB  I C R C  V CC  0 ;  V CB  V CC  I C R C ;
 Let I E  I C so that,
V CB  V CC  I E R C [4.48]

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 4.9 Multiple BJT Networks
 Thus far, the BJT circuits discussed have only been single-stage configurations.
 Let us briefly look at some of the most common multiple transistor networks.
RC Coupling

Figure 4.42: RC coupled BJT amplifiers.

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 4.9 Multiple BJT Networks Cont’d
 The network of Fig. 4.42 yields two dc bias circuits of Fig. 4.43 which can be
analyzed as done before.
Darlington Configuration

Figure 4.43: DC equivalent of

Fig. 4.42.

Figure 4.44: Darlington

amplifier.

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 4.9 Multiple BJT Networks Cont’d
 The Darlington amplifier of Fig. 4.44 feeds the
output of one stage directly into the input of the
succeeding stage.
 The input impedance is very high, making it
attractive for use in amplifiers driven by sources of
relatively high internal resistance.
 Assuming a beta 1 for the first BJT and 2 for the
second BJT, it follows that
I B 2  I E1   1  1  I B1

Figure 4.45: DC
 Furthermore,
equivalent of Fig. 4.44. I E 2   2  1  I B 2   2  1  1  1  I B1
 Let  ? 1 for each BJT, so that net beta for the configuration is
 D  1  2 [4.49]
 This compares directly with a single-stage amplifier having a gain of  D .

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 4.9 Multiple BJT Networks Cont’d
 Applying an analysis similar to that of section 4.4 yields
V CC  V BE1  V BE 2
I B1 
R B  D  1  R E
 Defining
V B E D  V B E1  V B E 2 [4.50]
 We have.
V CC  V BE D
I B1  [4.51]
R B  D  1  R E
 The currents
I C 2  I E 2   D I B1 [4.52]
 The dc voltage at the emitter terminal is
V E2  I E2 R E [4.53]
 Vividly, V C2  V CC [4.54]

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 4.9 Multiple BJT Networks Cont’d
 Thus, the voltage across the output of transistor is
V CE 2  V C2  V E 2 ; V B E D  V B E1  V B E 2 [4.55]

 There are many other Cascode Configuration

multiple transistor networks
which will not be discussed
in lecture 4. Nevertheless,
you ought to take keen
interest, in your spare time,
to look at and understand.
 These include:

Figure 4.46:
Cascode
Amplifier.

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 4.9 Multiple BJT Networks Cont’d
Feedback Pair Amplifier

Direct Coupled Amplifier

Figure 4.47: Feedback Amplifier.

Current Mirror

Figure 4.48: Direct-coupled Amplifier.

Figure 4.49: Current

mirror using back-to-
back BJTs.
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 4.10 pnp BJTs
 Thus far, the analysis has been based on npn
transistors.
 It is worth noting that the analysis of pnp transistors
follows the same pattern, except that the resulting
equations have change of signs associate with
particular quantities.
 For instance, notice the change of signs in Fig. 4.50.

Figure 4.50: pnp BJT in an

emitter stabilized configuration

4.11 Transistor Switching Networks

 Transistor applications are not limited solely to the amplification of signals.
 Through proper design, BJTs can be used as switches for computer logic
circuits and control applications.

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4.11 Transistor Switching Networks Cont’d
 Proper design for the inversion
process requires that the
operating point switch from
cutoff to saturation along the
load line depicted in Fig. 4.51.
 For this purpose assume
I C  I CE O  0 m A when
I B  0 A V CE  V CE sa t  0 V
 When V i and
5 V , the BJT will be
.
“ON” and the design must
ensure that the network is
heavily saturated by a level of
.A
I B  50 

Figure 4.51: Transistor inverter

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 4.11 Transistor Switching Networks Cont’d
 The saturation level for the collector current is
V CC
I Csa t  [4.56]
RC

 The level of I B in the active region just before saturation results can be
approximated by I Csa t
I Bmax 
 dc
 For the saturation level we must therefore ensure that the following condition is
met:
I Csa t
IB  [4.57]
dc
 For the network of Fig. 4.51, when V i  5 V , then
V i  0.7 V 5 V  0.7 V
IB    63  A
RB 68 k 

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 4.11 Transistor Switching Networks Cont’d
 Furthermore V CC 5V
I Csa t    6.1 m A
RC 0.82 k 
 Testing Eq. [4.57] yields
6.1 m A I Csa t
I B  63  A    48.8  A
 dc 125
 For V i  0 V , I B  0  A , and assuming that I C  I CE O  0 m A , the voltage
drop across R C as determined by V R  I C R C  0 V , resulting inV C  5 V
C

for the response indicated in Fig. 4.51a.

V CE sa t
R sa t 
I Csa t

V CC
Figure 4.52: Saturation Figure 4.53: Cutoff R cu t off 
conditions and resulting conditions and resulting I CE O
resistance. resistance.

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 4.12 Bias Stabilization
 Stability of a system is a measure of the sensitivity of a network to variations in
its parameters.
  : increases with increase in temperature
 V B E : decreases about 2.5 m V per degree Celsius ( oC ) increase in
temperature
 I CO (reverse saturation current): doubles in value for every 10 o C increase in
temperature.
Stability Factors
 Defined for each parameter affecting bias as follows:
I C
S  I CO   [4.58]
I CO
I C
S V B E   [4.59]
V B E
I C
S    [4.60]

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 4.12 Bias Stabilization Cont’d
S(ICO)
 Fixed-Bias Configuration
S  I CO    [4.61]
 Emitter-Bias Configuration
 1  R B R E 
S  I CO   [4.62]
  RB RE
 Voltage-Divider Bias Configuration
 1  R Th R E 
S  I CO   [4.63]
  R Th R E
 Feedback-Bias Configuration (RE = 0 Ω)
 1  R B R C 
S  I CO   [4.64]
  R B RC

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 4.12 Bias Stabilization Cont’d
S(VBE)
 Fixed-Bias Configuration
S V B E     R B [4.65]
 Emitter-Bias Configuration
 R E
S V B E   [4.66]
  RB RE
 Voltage-Divider Bias Configuration
 R E
S V B E   [4.67]
  R Th R E
 Feedback-Bias Configuration (RE = 0 Ω)
 R C
S  I CO   [4.68]
  R B RC

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 4.12 Bias Stabilization Cont’d
S(β)
 Fixed-Bias Configuration
S     I C1 1 [4.69]
 Emitter-Bias Configuration
I C I C1 1  R B R E 
S     [4.70]
 1   2  R B R E 
 Voltage-Divider Bias Configuration
I C I C1 1  R Th R E 
S     [4.71]
 1  2  R Th R E 
 Feedback-Bias Configuration (RE = 0 Ω)
I C1  R B  R C 
S    [4.72]
1  R B   2 R C 

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 End of Lecture 4

Thank you for your attention!

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