Microprocessor

• Microprocessor (µP) is the “brain” of a computer that

has been implemented on one semiconductor chip.
• The word comes from the combination micro and
processor.
• Processor means a device that processes
whatever(binary numbers, 0’s and 1’s)
⮚ To process means to manipulate. It describes all
manipulation.
⮚ Micro - > extremely small

1
 Definition of a Microprocessor.
The microprocessor is a programmable
device that takes in numbers, performs on
them arithmetic or logical operations
according to the program stored in memory
and then produces other numbers as a result.

2
 Microprocessor ?

A microprocessor is multi
programmable clock driven
register based semiconductor
device that is used to fetch ,
process & execute a data
within fraction of seconds.
3
 Applications
• Calculators
• Accounting system
• Games machine
• Instrumentation
• Traffic light Control
• Multi user, multi-function environments
• Military applications
• Communication systems
4
MICROPROCESSOR HISTORY

5
 DIFFERENT PROCESSORS AVAILABLE

Socket
Pinless
Processor

Processor Slot
Processor

Processor
Slot

6
 Development of Intel Microprocessors
• 8086 - 1979
• 286 - 1982
• 386 - 1985
• 486 - 1989
• Pentium - 1993
• Pentium Pro - 1995
• Pentium MMX -1997
• Pentium II - 1997
• Pentium II Celeron - 1998
• Pentium II Zeon - 1998
• Pentium III - 1999
• Pentium III Zeon - 1999
• Pentium IV - 2000
• Pentium IV Zeon - 2001

7
GENERATION OF PROCESSORS
Processor Bits Speed

8080 8 2 MHz

8086 16 4.5 – 10
MHz
8088 16 4.5 – 10
MHz
80286 16 10 – 20
MHz
80386 32 20 – 40
MHz
80486 32 40 – 133
MHz

8
GENERATION OF PROCESSORS

Processor Bits Speed

Pentium 32 60 – 233
MHz
Pentium 32 150 – 200
Pro MHz
Pentium II, 32 233 – 450
Celeron , MHz
Xeon
Pentium 32 450 MHz –
III, Celeron 1.4 GHz
, Xeon
Pentium IV, 32 1.3 GHz –
Celeron , 3.8 GHz
Xeon
Itanium 64 800 MHz –
3.0 GHz
9
Intel 4004
⮚ Introduced in 1971.
⮚ It was the first
microprocessor by Intel.
⮚ It was a 4-bit µP.
⮚ Its clock speed was 740KHz.
⮚ It had 2,300 transistors.
⮚ It could execute around
60,000 instructions per
second.
10
Intel 4040
⮚ Introduced in 1971.
⮚ It was also 4-bit µP.

11
8-bit Microprocessors

12
Intel 8008
⮚ Introduced in 1972.
⮚ It was first 8-bit µP.
⮚ Its clock speed was
500 KHz.
⮚ Could execute
50,000 instructions
per second.

13
Intel 8080
⮚ Introduced in 1974.
⮚ It was also 8-bit µP.
⮚ Its clock speed was 2
MHz.
⮚ It had 6,000
transistors.

14
Intel 8085 ⮚Introduced in 1976.
⮚It was also 8-bit µP.
⮚Its clock speed was 3 MHz.
⮚Its data bus is 8-bit and
address bus is 16-bit.
⮚It had 6,500 transistors.
⮚Could execute 7,69,230
instructions per second.
⮚It could access 64 KB of
memory.
⮚It had 246 instructions.
15
16-bit Microprocessors

16
 ⮚ Introduced in 1978.

INTEL 8086 ⮚ It was first 16-bit µP.

⮚ Its clock speed is 4.77 MHz, 8 MHz

and 10 MHz, depending on the
version.

⮚ Its data bus is 16-bit and address bus

is 20-bit.

⮚ It had 29,000 transistors.

⮚ Could execute 2.5 million instructions

per second.

⮚ It could access 1 MB of memory.

⮚ It had 22,000 instructions.

⮚ It had Multiply and Divide 17

instructions.
INTEL 8088
⮚ Introduced in 1979.

⮚ It was also 16-bit µP.

⮚ It was created as a cheaper

version of Intel’s 8086.

⮚ It was a 16-bit processor

with an 8-bit external bus.

18
INTEL 80186 & 80188
⮚ Introduced in 1982.
⮚ They were 16-bit µPs.
⮚ Clock speed was 6 MHz.
⮚ 80188 was a cheaper
version of 80186 with an 8-
bit external data bus.

19
INTEL 80286
⮚ Introduced in 1982.
⮚ It was 16-bit µP.
⮚ Its clock speed was 8 MHz.
⮚ Its data bus is 16-bit and
address bus is 24-bit.
⮚ It could address 16 MB of
memory.
⮚ It had 1,34,000 transistors.
20
32-BIT MICROPROCESSORS

21
 ⮚ Introduced in 1986.
INTEL 80386 ⮚ It was first 32-bit µP.
⮚ Its data bus is 32-bit and
address bus is 32-bit.
⮚ It could address 4 GB of
memory.
⮚ It had 2,75,000 transistors.
⮚ Its clock speed varied from
16 MHz to 33 MHz
depending upon the various
versions.
22
 ⮚ Introduced in 1989.
INTEL 80486
⮚ It was also 32-bit µP.
⮚ It had 1.2 million
transistors.
⮚ Its clock speed varied from
16 MHz to 100 MHz
depending upon the various
versions.
⮚ 8 KB of cache memory was
introduced.

23
 ⮚ Introduced in 1993.
INTEL PENTIUM
⮚ It was also 32-bit µP.

⮚ It was originally named

80586.

⮚ Its clock speed was 66

MHz.

⮚ Its data bus is 32-bit and

address bus is 32-bit.

24
INTEL PENTIUM PRO
⮚ Introduced in 1995.
⮚ It was also 32-bit µP.
⮚ It had 21 million transistors.
⮚ Cache memory:
⮚ 8 KB for instructions.

⮚ 8 KB for data.

25
INTEL PENTIUM II
⮚ Introduced in 1997.
⮚ It was also 32-bit µP.
⮚ Its clock speed was 233
MHz to 500 MHz.
⮚ Could execute 333 million
instructions per second.

26
INTEL PENTIUM II XEON
⮚ Introduced in 1998.

⮚ It was also 32-bit µP.

⮚ It was designed for servers.

⮚ Its clock speed was 400

MHz to 450 MHz.

27
INTEL PENTIUM III
⮚ Introduced in 1999.
⮚ It was also 32-bit µP.
⮚ Its clock speed varied from
500 MHz to 1.4 GHz.
⮚ It had 9.5 million
transistors.

28
INTEL PENTIUM IV
⮚ Introduced in 2000.

⮚ It was also 32-bit µP.

⮚ Its clock speed was from 1.3

GHz to 3.8 GHz.

⮚ It had 42 million transistors.

29
 ⮚ Introduced in 2006.
INTEL DUAL CORE
⮚ It is 32-bit or 64-bit µP.

30
31
64-BIT MICROPROCESSORS

32
Intel Core 2 Intel Core i3

33
INTEL CORE I5 INTEL CORE I7

34
 Basic Terms
• Bit: A digit of the binary number { 0 or 1 }
• Nibble: 4 bit Byte: 8 bit word: 16 bit
• Double word: 32 bit
• Data: binary number/code operated by an instruction
• Address: Identification number for memory locations
• Clock: square wave used to synchronize various
devices in µP
• Memory Capacity = 2^n ,
n->no. of address lines

35
 BUS CONCEPT
• BUS: Group of conducting lines that carries data ,
address & control signals.
CLASSIFICATION OF BUSES:
1.DATA BUS: group of conducting lines that carries data.
2. ADDRESS BUS: group of conducting lines that carries
address.
3.CONTROL BUS: group of conducting lines that carries
control signals {RD, WR etc}
CPU BUS: group of conducting lines that directly
connected to µP
SYSTEM BUS: group of conducting lines that carries
data , address & control signals in a µP system 36
 TRISTATE LOGIC
3 logic levels are:
• High State (logic 1)
• Low state (logic 0)
• High Impedance state

High Impedance:  output is not being driven to any defined logic level by

the output circuit.

37
 Basic Microprocessors System
Central Processing Unit
Arithmetic
Control -
Unit Logic
ProcessingUnit
Input Data into Output
Devices Information
Primary Storage Devices
Unit
Keyboard, Monito
Mouse r
etc Printer

Disks, Tapes, Optical Disks

Secondary Storage Devices 38

 UNIT

1
THE 8086 MICROPROCESSOR

39
 8086 Microprocessor-introduction
⮚ INTEL launched 8086 in 1978
⮚ 8086 is a 16-bit microprocessor with
• 16-bit Data Bus {D0-D15}
• 20-bit Address Bus {A0-A19} [can access upto
2^20= 1 MB memory locations] .
⮚ It has multiplexed address and data bus
AD0-AD15 and A16–A19.
⮚ It can support upto 64K I/O ports
40
 8086 Microprocessor
⮚ It provides 14, 16-bit registers.
⮚ 8086 requires one phase clock with a 33%
duty cycle to provide optimized internal
timing.
– Range of clock:
• 5 MHz for 8086
• 8Mhz for 8086-2
• 10Mhz for 8086-1
41
INTEL 8086 - Pin Diagram/Signal Description

42
 INTEL 8086 - Pin Details

Power Supply
5V ± 10%
Ground

Reset
Registers, seg
regs, flags
CS: FFFFH, IP:
0000H
If high for
minimum 4
Clock clks
Duty cycle: 33%
43
 INTEL 8086 - Pin Details

Address/Data Bus:
Contains address Address Latch Enable:
bits A15-A0 when ALE
is 1 & data bits D15 – When high,
multiplexed
D0 when ALE is 0.
address/data bus
contains address
information.

44
 INTEL 8086 - Pin Details

INTERRUPT

Non - maskable
interrupt

Interrupt
acknowledge

Interrupt request
45
INTEL 8086 - Pin Details

Direct
Memory
Access

Hold

Hold
acknowledge

46
INTEL 8086 - Pin Details

Address/Status Bus
Address bits A19 –
A16 & Status bits S6 –
S3

47
 INTEL 8086 - Pin Details

BHE#, A0: Bus High Enable/S7

0,0: Whole word Enables most
(16-bits) significant data bits
0,1: High byte
D15 – D8 during read
to/from odd address or write operation.
1,0: Low byte S7: Always 1.
to/from even address

1,1: No selection

48
 INTEL 8086 - Pin Details

Min/Max mode
Minimum Mode: +5V
Maximum Mode: 0V

Minimum Mode Pins

Maximum Mode
Pins

49
Minimum Mode- Pin Details

Read Signal

Write Signal

Memory or I/0

Data
Transmit/Receive

Data Bus Enable

50
 Maximum Mode - Pin Details

S2 S1 S0
000: INTA
001: read I/O port
010: write I/O port
011: halt
100: code access Status Signal
101: read memory
110: write memory Inputs to 8288 to
111: none -passive generate eliminated
signals due to max
mode.

51
 Maximum Mode - Pin Details

Lock Output
Used to lock peripherals
off the system
DMA
Activated by using the
Request/Grant
LOCK: prefix on any
instruction

Lock Output

52
 Maximum Mode - Pin Details

QS1 QS0
00: Queue is idle
01: First byte of opcode
10: Queue is empty
11: Subsequent byte of
opcode

Queue Status
Used by numeric
coprocessor (8087)

53
 8086 Internal Architecture
⮚ 8086 employs parallel processing
⮚ 8086 CPU has two parts which operate at the
same time
• Bus Interface Unit 8086 CPU
• Execution Unit
⮚ CPU functions Bus Interface
Unit (BIU)
1. Fetch

2. Decode Execution
Unit
3. Execute (EU)

54
 Bus Interface Unit
⮚ Sends out addresses for memory locations
⮚ Fetches Instructions from memory
⮚ Reads/Writes data to memory
⮚ Sends out addresses for I/O ports
⮚ Reads/Writes data to Input/Output ports

55
 Execution Unit
⮚ Tells BIU (addresses) where to fetch
instructions or data
⮚ Decodes & Executes instructions

⮚ Dividing the work between BIU & EU

speeds up processing

56
Architecture Diagram of 8086

57
 Memory
∑ Interface

EXTRA SEGMENT (ES) BIU

CODE SEGMENT (CS)
6 5 4 3 2 1
STACK SEGMENT (SS)
DATA SEGMENT (DS) Instruction Queue
INSTRUCTION POINTER (IP)

Instruction
Decoder
AH AL
BH BL
ARITHMETIC
CH CL LOGIC UNIT
DH DL CONTROL
SYSTEM
STACK POINTER (SP)
BASE POINTER (BP)
OPERANDS
SOURCE INDEX (SI)
DESTINATION INDEX (DI)
FLAGS
EU 58
 Execution Unit
⮚ Main components are
• Instruction Decoder
• Control System
• Arithmetic Logic Unit
• General Purpose Registers
• Flag Register
• Pointer & Index registers

59
 Instruction Decoder
⮚ Translates instructions fetched from memory
into a series of actions which EU carries out

Control System
⮚ Generates timing and control signals to
perform the internal operations of the
microprocessor

Arithmetic Logic Unit

⮚ EU has a 16-bit ALU which can ADD,
SUBTRACT, AND, OR, increment, decrement,
complement or shift binary numbers
60
 General Purpose Registers
⮚ EU has 8 general AH AL
purpose registers BH BL
⮚ Can be individually
used for storing 8-bit CH CL
data DH DL
⮚ AL register is also
called Accumulator AH AL AX
⮚ Two registers can also
BH BL BX
be combined to form
16-bit registers CH CL CX
⮚ The valid register pairs
are – AX, BX, CX, DX DH DL DX
61
 Flag Register
⮚ 8086 has a 16-bit flag register
⮚ Contains 9 active flags
⮚ There are two types of flags in 8086
• Conditional flags – six flags, set or reset
by EU on the basis of results of some
arithmetic operations
• Control flags – three flags, used to control
certain operations of the processor

62
 Flag Register
U U U U OF DF IF TF SF ZF U AF U PF U CF

1. CF CARRY FLAG
Conditional Flags
2. PF PARITY FLAG
(Compatible with 8085,
3. AF AUXILIARY CARRY
except OF)
4. ZF ZERO FLAG
5. SF SIGN FLAG

6. OF OVERFLOW FLAG

7. TF TRAP FLAG Control Flags 63

8. IF INTERRUPT FLAG
 Flag Register
Auxiliary Carry Flag
Carry Flag
This is set, if there is a carry from the
lowest nibble, i.e, bit three during This flag is set, when there is
addition, or borrow for the lowest a carry out of MSB in case of
nibble, i.e, bit three, during addition or a borrow in case
subtraction. of subtraction.

Sign Flag Zero Flag Parity Flag

This flag is set, when the This flag is set, if the result of This flag is set to 1, if the lower
result of any computation the computation or comparison byte of the result contains even
is negative performed by an instruction is number of 1’s ; for odd number
zero of 1’s set to zero.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

OF DF IF TF SF ZF AF PF CF

Tarp Flag
Over flow Flag If this flag is set, the processor
This flag is set, if an overflow occurs, i.e, if the result of a signed enters the single step execution
operation is large enough to accommodate in a destination
mode by generating internal
register. The result is of more than 7-bits in size in case of 8-bit
signed operation and more than 15-bits in size in case of 16-bit interrupts after the execution of
sign operations, then the overflow will be set. each instruction

Direction Flag Interrupt Flag

This is used by string manipulation instructions. If this flag bit
is ‘0’, the string is processed beginning from the lowest Causes the 8086 to recognize
address to the highest address, i.e., auto incrementing mode. external mask interrupts; clearing IF
Otherwise, the string is processed from the highest address disables these interrupts.
towards the lowest address, i.e., auto incrementing mode. 64
 Registers, Flag

8086 registers
categorized 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

into 4 groups OF DF IF TF SF ZF AF PF CF

Sl.No. Type Register width Name of register

1 General purpose 16 bit AX, BX, CX, DX
register
8 bit AL, AH, BL, BH, CL, CH, DL, DH

2 Pointer register 16 bit SP, BP

3 Index register 16 bit SI, DI

4 Instruction Pointer 16 bit IP

5 Segment register 16 bit CS, DS, SS, ES

6 Flag (PSW) 16 bit Flag register

65
 Registers and Special Functions

Register Name of the Register Special Function

AX 16-bit Accumulator Stores the 16-bit results of arithmetic and logic operations

AL 8-bit Accumulator Stores the 8-bit results of arithmetic and logic operations

BX Base register Used to hold base value in base addressing mode to

access memory data

CX Count Register Used to hold the count value in SHIFT, ROTATE and LOOP
instructions

DX Data Register Used to hold data for multiplication and division operations

SP Stack Pointer Used to hold the offset address of top stack memory

BP Base Pointer Used to hold the base value in base addressing using SS
register to access data from stack memory

SI Source Index Used to hold index value of source operand (data) for string
instructions

DI Data Index Used to hold the index value of destination operand (data)
for string operations 66
 Bus Interface Unit
⮚ Main Components are
• Instruction Queue
• Segment Registers
• Instruction Pointer

67
 Memory
∑ Interface

EXTRA SEGMENT (ES) BIU

CODE SEGMENT (CS)
6 5 4 3 2 1
STACK SEGMENT (SS)
DATA SEGMENT (DS) Instruction Queue
INSTRUCTION POINTER (IP)

Instruction
Decoder
AH AL
BH BL
ARITHMETIC
CH CL LOGIC UNIT
DH DL CONTROL
SYSTEM
STACK POINTER (SP)
BASE POINTER (BP)
OPERANDS
SOURCE INDEX (SI)
DESTINATION INDEX (DI)
FLAGS
EU 68
 Instruction Queue
⮚ 8086 employs parallel processing
⮚ When EU is busy decoding or executing
current instruction, the buses of 8086 may
not be in use.
⮚ At that time, BIU can use buses to fetch upto
six instruction bytes for the following
instructions
⮚ BIU stores these pre-fetched bytes in a FIFO
register called Instruction Queue
⮚ When EU is ready for its next instruction, it
simply reads the instruction from the queue
in BIU
69
 Pipelining
⮚ EU of 8086 does not have to wait in
between for BIU to fetch next
instruction byte from memory
⮚ So the presence of a queue in 8086
speeds up the processing
⮚ Fetching the next instruction while the
current instruction executes is called
pipelining

70
 Memory Segmentation
⮚ 8086 has a 20-bit address bus
⮚ So it can address a maximum of 1MB of
memory
⮚ 8086 can work with only four 64KB segments
at a time within this 1MB range
⮚ These four memory segments are called
• Code segment
• Stack segment
• Data segment
• Extra segment

71
 Memory
64KB Memory 1
00000H
Segment 2

3
4
4
5
Only 4 such segments can be 6
addressed at a time 7

8
1MB
9 Address
10 Range
11

12

13

14

15

16
FFFFFH
72
 Code Segment
⮚ That part of memory from where BIU is
currently fetching instruction code bytes

Stack Segment
⮚ A section of memory set aside to store
addresses and data while a subprogram
executes

Data & Extra Segments

⮚ Used for storing data values to be used in
the program

73
 Memory
Code Segment 1
00000H
2

4
Data & Extra 5

Segments 6

8 1MB
9 Address
10 Range
11

12

13

14

15

Stack Segment 16
FFFFFH
74
 Segment Registers
⮚ hold the upper 16-bits of the starting
address for each of the segments
⮚ The four segment registers are
• CS (Code Segment register)
• DS (Data Segment register)
• SS (Stack Segment register)
• ES (Extra Segment register)

75
 Memory
1 00000H
CS 1000 0H Code Segment
3

DS 4000 0H Data Segment

Extra Segment
ES 5000 0H
7

Starting Addresses
8
1MB
9
Address
10
Range
of Segments
11

12

13

14

15

SS F000 0H Stack Segment

FFFFFH 76
⮚ Address of a segment is of 20-bits
⮚ A segment register stores only upper 16-
bits
⮚ BIU always inserts zeros for the lowest 4-
bits of the 20-bit starting address.
⮚ E.g. if CS = 348AH, then the code
segment will start at 348A0H
⮚ A 64-KB segment can be located
anywhere in the memory, but will start at
an address with zeros in the lowest 4-bits
77
Instruction Pointer (IP) Register
⮚ a 16-bit register
⮚ Holds 16-bit offset, of the next instruction
byte in the code segment
⮚ BIU uses IP and CS registers to generate
the 20-bit address of the instruction to be
fetched from memory

78
 Physical Address Calculation Memory
Start of Code Segment 1 00000H
348A0H Data
Segment
IP = 4214H 3

MOV AL, 4
Code Byte 38AB4H BL Code
Segment
Extra
Segment
7
1MB
8
9
Address
10
Range
CS 348A0 H 11
IP + 4214 H 12

13
Physical Address 38AB4 H 14
15

Stack
Segment 79
FFFFFH
 Stack Segment (SS) Register
Stack Pointer (SP) Register
⮚ Upper 16-bits of the starting address of
stack segment is stored in SS register
⮚ It is located in BIU
⮚ SP register holds a 16-bit offset from the
start of stack segment to the top of the
stack
⮚ It is located in EU

80
Other Pointer & Index Registers
⮚ Base Pointer (BP) register
⮚ Source Index (SI) register
⮚ Destination Index (DI) register
⮚ Can be used for temporary storage of data
⮚ Main use is to hold a 16-bit offset of a data
word in one of the segments

81
ADDRESSING
MODES OF
8086
82
 Various Addressing Modes
1. Immediate Addressing Mode
2. Register Addressing Mode
3. Direct Addressing Mode
4. Register Indirect Addressing Mode
5. Index Addressing Mode
6. Based Addressing Mode
7. Based & Indexed Addressing Mode
8. Based & Indexed with displacement Addressing Mode
9. Strings Addressing Mode

83
Presented by C.GOKUL,AP/EEE , Velalar College of Engg & Tech, Erode
 1. IMMEDIATE ADDRESSING MODE
• The instruction will specify the name
of the register which holds the data to
be operated by the instruction.

• Source data is within the

instruction

• Ex: MOV AX,10AB H

🡺 AL=ABH, AH=10H

84
 2.REGISTER ADDRESSING MODE
• In immediate addressing mode, an
8-bit or 16-bit data is specified as
part of the instruction

• Ex: MOV AX,BL H

MOV AX,BL H

85
 3. DIRECT ADDRESSING MODE

• Memory address is supplied with in

the instruction
• Mnemonic: MOV AH,[MEMBDS]
AH [1000H]
• But the memory address is not
index or pointer register

86
 4. REGISTER INDIRECT ADDRESSING MODE

• Memory address is supplied in an index or

pointer register
• EX:

MOV AX,[SI] ; AL [SI] ; AH [SI+1]

JMP [DI] ; IP [DI+1: DI]
INC BYTE PTR [BP] ; [BP] [BP]+1
DEC WORD PTR [BX] ;
[BX+1:BX] [BX+1:BX]-1
87
 5.Indexed Addressing Mode
• Memory address is the sum of index
register plus displacement
MOV AX,[SI+2] AL [SI+2]; AH [SI+3]
JMP [DI+2] IP [BX+3:BX+2]

88
 6. Based Addressing Mode
• Memory address is the sum of the BX or BP
base register plus a displacement within
instruction
• Ex:
MOV AX,[BP+2] AL [BP+2]; AH [BP+3]
JMP [BX+2] IP [BX+3:BX+2]

89
 7.BASED & INDEX ADDRESSING MODES

• Memory address is the sum of the index register

& base register
Ex:
MOV AX,[BX+SI] ; AL [BX+SI] ; AH [BX+SI+1]
JMP [BX+DI] ; IP [BX+DI+1 : BX+DI]
INC BYTE PTR [BP+SI] ; [BP] [BP]+1
DEC WORD PTR [BP+DI] ;
[BX+1:BX] [BX+1:BX]-1

90
 8. BASED & INDEXED WITH DISPLACEMENT ADDRESSING MODE

• Memory address is the sum of an index register ,

base register and displacement within instruction

MOV AX,[BX+SI+6] ; AL [BX+SI+6] ; AH [BX+SI+7]

JMP [BX+DI+6] ; IP [BX+DI+7 : BX+DI+6]
INC BYTE PTR [BP+SI+5] ;
DEC WORD PTR [BP+DI+5] ;

Presented by C.GOKUL,AP/EEE , Velalar College of Engg & Tech, Erode 91

 9. Strings Addressing Mode

• The memory source address is a register SI in

the data segment, and the memory destination
address is register DI in the extra segment

• Ex: MOVSB [ES:DI] [DS:SI]

• If DF=0 SI SI+1 , DI DI+1

DF=1 SI SI-1 , DI DI-1
92
INSTRUCTION
SET of 8086

93
 Instruction set basics
• Instruction:- An instruction is a binary pattern designed inside
a microprocessor to perform a specific function.

• Opcode:- It stands for operational code. It specifies the type of

operation to be performed by CPU. It is the first field in the
machine language instruction format.
• E.g. 08 is the opcode for instruction “MOV X,Y”.

• Operand:- We can also say it as data on which operation

should act. operands may be register values or memory values.
The CPU executes the instructions using information present in
this field. It may be 8-bit data or 16-bit data. 94
 Instruction set basics

• Assembler:- it converts the instruction into sequence of

binary bits, so that this bits can be read by the processor.

• Mnemonics:- these are the symbolic codes for either

instructions or commands to perform a particular
function.
• E.g. MOV, ADD, SUB etc.

95
Types of instruction set of 8086
microprocessor
(1). Data Copy/Transfer instructions.

(2). Arithmetic & Logical instructions.

(3). Branch instructions.

(4). Loop instructions.

(5). Machine Control instructions.

(6). Flag Manipulation instructions.

(7). Shift & Rotate instructions.

(8). String instructions.

96
(1). Data copy/transfer instructions.

(1). MOV Destination, Source

⚫ There will be transfer of data from source to destination.

⚫ Source can be register, memory location or immediate data.
⚫ Destination can be register or memory operand.
⚫ Both Source and Destination cannot be memory location or
segment registers at the same time.
⚫ E.g.
⚫ (1). MOV CX, 037A H;
⚫ (2). MOV AL, BL;
⚫ (3). MOV BX, [0301 H];
97
BEFORE AFTER
EXECUTION EXECUTION
AX 2000H MOV BX,AX BX 2000H

BEFORE AFTER
EXECUTION EXECUTION
AH AL AH AL
BH BL BH BL
CH CL MOV CL,M CH CL 40
DH DL 40 DH DL 40

98
Stack Pointer
⚫It is a 16-bit register, contains the address of the data
item currently on top of the stack.

⚫Stack operation includes pushing (providing) data on

to the stack and popping (taking)data from the stack.

⚫Pushing operation decrements stack pointer and

Popping operation increments stack pointer. i.e. there
is a last in first out (LIFO) operation.

99
(2). Push Source

⚫ Source can be register, segment register or memory.

⚫ This instruction pushes the contents of specified source
on to the stack.
⚫ In this stack pointer is decremented by 2.
⚫ The higher byte data is pushed first (SP-1).
⚫ Then lower byte data is pushed (SP-2).

⚫ E.g.:
⚫ (1). PUSH AX;
⚫ (2). PUSH DS;
⚫ (3). PUSH [5000H];
100
 INITIAL POSITION

(1) STACK
POINTER
DECREMENTS SP & STORES HIGHER
BYTE

(2) STACK
POINTER HIGHER BYTE

DECREMENTS SP & STORES LOWER

BYTE
(3) STACK
POINTER LOWER BYTE
HIGHER BYTE

101
 BEFORE EXECUTION
SP 2002H
2000H
BH BL
2001H
CH 10 CL 50
DH DL
2002H

PUSH CX
AFTER EXECUTION
2000H 50
SP 2000H
BH BL
2001H 10
CH 10 CL 50

DH DL 2002H

102
(3) POP Destination

⚫ Destination can be register, segment register or memory.

⚫ This instruction pops (takes) the contents of specified
destination.
⚫ In this stack pointer is incremented by 2.
⚫ The lower byte data is popped first (SP+1).
⚫ Then higher byte data is popped (SP+2).

⚫ E.g.
⚫ (1). POP AX;
⚫ (2). POP DS;
⚫ (3). POP [5000H];
103
 INITIAL POSITION AND READS LOWER
BYTE
(1) STACK
POINTER LOWER BYTE

INCREMENTS SP & READS HIGHER BYTE

LOWER BYTE
(2) STACK HIGHER BYTE
POINTER

INCREMENTS SP

LOWER BYTE
HIGHER BYTE

(3) STACK
POINTER
104
 BEFORE EXECUTION

2000H 30
SP 2000H
2001H 50
BH BL
2002H

POP BX
AFTER EXECUTION
2000H 30
SP 2002H 2001H 50
BH 5 BL 30 2002H
0 105
(4). XCHG Destination, source;

• This instruction exchanges contents of Source with

destination.

• It cannot exchange two memory locations directly.

•The contents of AL are exchanged with BL.

•The contents of AH are exchanged with BH.

•E.g.
(1). XCHG BX, AX;
(2). XCHG [5000H],AX;
106
BEFORE EXECUTION AFTER
EXECUTION
AH 2 AL 40 AH 70 AL 80
0
BH 70 BL 80 BH 20 BL 40

XCHG AX,BX
107
(5)IN AL/AX, 8-bit/16-bit port address

⚫It reads from the specified port address.

⚫It copies data to accumulator from a port with 8-
bit or 16-bit address.
⚫DX is the only register is allowed to carry port
address.
⚫E.g.
(1). IN AL, 80H;
(2). IN AX,DX; //DX contains address of 16-bit
port.
108
 BEFORE EXECUTION

PORT 10 AL
80H

IN AL,80H
AFTER EXECUTION

PORT 10 AL 10
80H
109
OUT 8-bit/16-bit port address, AL/AX

⚫It writes to the specified port address.

⚫It copies contents of accumulator to the port with
8-bit or 16-bit address.
⚫DX is the only register is allowed to carry port
address.
⚫E.g.
(1). OUT 80H,AL;
(2). OUT DX,AX; //DX contains address of 16-bit
port.
110
 BEFORE EXECUTION

PORT 10 AL 40
50H

OUT 50H,AL
AFTER EXECUTION

PORT 40 AL 40
50H
111
(7) XLAT

⚫Also known as translate instruction.

⚫It is used to find out codes in case of code conversion.
⚫i.e. it translates code of the key pressed to the
corresponding 7-segment code.
⚫After execution this instruction contents of AL register
always gets replaced.
⚫E.g. XLAT;

112
8.LEA 16-bit register (source), address (dest.)

⚫LEA Also known as Load Effective Address

(LEA).
⚫It loads effective address formed by the
destination into the source register.

⚫E.g.
(1). LEA BX,Address;
(2). LEA SI,Address[BX];

113
(9). LDS 16-bit register (source), address (dest.);
(10). LES 16-bit register (source), address (dest.);

⚫LDS Also known as Load Data Segment (LDS).

⚫LES Also known as Load Extra Segment (LES).
⚫It loads the contents of DS (Data Segment) or ES
(Extra Segment) & contents of the destination to
the contents of source register.

⚫E.g.
(1). LDS BX,5000H;
(2). LES BX,5000H;
114
 (1). LDS BX,5000H;
(2). LES BX,5000H;

15 0 7 0
BX 20 10 10
5000H
20
5001H
30
DS/ES 40 30 5002H
40
5003H

115
(11). LAHF:- This instruction loads the AH register
from the contents of lower byte of the flag register.
⚫ This command is used to observe the status of the all
conditional flags of flag register.
E.g. LAHF;

(12). SAHF:- This instruction sets or resets all

conditional flags of flag register with respect to the
corresponding bit positions.
⚫ If bit position in AH is 1 then related flag is set
otherwise flag will be reset.
E.g. SAHF;
116
PUSH & POP
(13). PUSH F:- This instruction decrements the stack
pointer by 2.
⚫ It copies contents of flag register to the memory location
pointed by stack pointer.
⚫ E.g. PUSH F;

(14). POP F:- This instruction increments the stack pointer

by 2.
⚫ It copies contents of memory location pointed by stack
pointer to the flag register.
⚫ E.g. POP F;
117
(2). Arithmetic Instructions
⚫These instructions perform the
operations like:

⚫Addition,
⚫Subtraction,
⚫Increment,
⚫Decrement.

118
(2). Arithmetic Instructions
(1). ADD destination, source;

⚫ This instruction adds the contents of source operand with the

contents of destination operand.
⚫ The source may be immediate data, memory location or register.
⚫ The destination may be memory location or register.
⚫ The result is stored in destination operand.
⚫ AX is the default destination register.

⚫ E.g. (1). ADD AX,2020H;

(2). ADD AX,BX;
119
 BEFORE EXECUTION AFTER EXECUTION

AH 30 AL 30
AH 10 AL 10 ADD AX,2020H

1010
+2020
3030

BEFORE EXECUTION AFTER EXECUTION

AH 10 AL 10 AH 30 AL 30
ADD AX,BX
BH 20 BL 20 BH 20 BL 20

120
ADC destination, source
⚫ This instruction adds the contents of source operand with
the contents of destination operand with carry flag bit.
⚫ The source may be immediate data, memory location or
register.
⚫ The destination may be memory location or register.
⚫ The result is stored in destination operand.
⚫ AX is the default destination register.

⚫ E.g. (1). ADC AX,2020H;

(2). ADC AX,BX;
121
(3) INC source
⚫This instruction increases the contents of source
operand by 1.
⚫The source may be memory location or register.
⚫The source can not be immediate data.
⚫The result is stored in the same place.

⚫E.g. (1). INC AX;

(2). INC [5000H];

122
BEFORE EXECUTION AFTER EXECUTION

AH 10 AL 10 INC AX AH 10 AL 11

BEFORE EXECUTION AFTER EXECUTION

5000H 1010 INC [5000H] 5000H 1011

123
4. DEC source
⚫This instruction decreases the contents of source
operand by 1.
⚫The source may be memory location or register.
⚫The source can not be immediate data.
⚫The result is stored in the same place.

⚫E.g. (1). DEC AX;

(2). DEC [5000H];

124
 BEFORE EXECUTION AFTER EXECUTION

AH 10 AL 10 DEC AX AH 10 AL 09

BEFORE EXECUTION AFTER EXECUTION

5000H 1010 DEC [5000H] 5000H 1009

125
(5) SUB destination, source;
⚫This instruction subtracts the contents of source
operand from contents of destination.
⚫The source may be immediate data, memory location
or register.
⚫The destination may be memory location or register.
⚫The result is stored in the destination place.

⚫E.g. (1). SUB AX,1000H;

(2). SUB AX,BX;
126
BEFORE EXECUTION AFTER EXECUTION

AH 20 AL 00 SUB AX,1000H AH 10 AL 00

2000
-1000
=1000

BEFORE EXECUTION AFTER EXECUTION

AH 20 AL 00 AH 10 AL 00
BH 10 BL 00 SUB AX,BX
BH 10 BL 00
127
(6). SBB destination, source;
⚫ Also known as Subtract with Borrow.
⚫ This instruction subtracts the contents of source operand
& borrow from contents of destination operand.
⚫ The source may be immediate data, memory location or
register.
⚫ The destination may be memory location or register.
⚫ The result is stored in the destination place.

⚫ E.g. (1). SBB AX,1000H;

(2). SBB AX,BX;
128
BEFORE EXECUTION AFTER EXECUTION

B 1 SBB AX,1000H
AH 2 AL 20 AH 1 AL 19
0 2020 0
- 1000
1020-1=1019
BEFORE EXECUTION AFTER EXECUTION
B 1
AH 20 AL 20 AH 10 AL 19
SBB AX,BX
BH 10 BL 10 BH 10 BL 10
2050
129
(7). CMP destination, source
⚫ Also known as Compare.
⚫ This instruction compares the contents of source
operand with the contents of destination operands.
⚫ The source may be immediate data, memory location
or register.
⚫ The destination may be memory location or register.
⚫ Then resulting carry & zero flag will be set or reset.

⚫ E.g. (1). CMP AX,1000H;

(2). CMP AX,BX;
130
 D=S: CY=0,Z=1
BEFORE EXECUTION D>S: CY=0,Z=0
D<S: CY=1,Z=0 AFTER EXECUTION

AH 10 AL 00
CMP AX,BX CY 0 Z 1
BH 10 BL 00

BEFORE EXECUTION AFTER EXECUTION

AH 10 AL 00
CMP AX,BX CY 0 Z 0
BH 00 BL 10

BEFORE EXECUTION AFTER EXECUTION

AH 10 AL 00
CMP AX,BX CY Z 0
BH 20 BL 00 1

131
 ⚫AAA (ASCII Adjust after Addition):
⚫The data entered from the terminal is in ASCII format.

⚫In ASCII, 0 – 9 are represented by 30H – 39H.

⚫This instruction allows us to add the ASCII codes.

⚫This instruction does not have any operand.

⚫Other ASCII Instructions:

⚫AAS (ASCII Adjust after Subtraction)

⚫AAM (ASCII Adjust after Multiplication)

⚫AAD (ASCII Adjust Before Division)

132
 ⚫DAA (Decimal Adjust after Addition)
⚫It is used to make sure that the result of adding two BCD
numbers is adjusted to be a correct BCD number.
⚫It only works on AL register.

⚫DAS (Decimal Adjust after Subtraction)

⚫It is used to make sure that the result of subtracting two
BCD numbers is adjusted to be a correct BCD number.
⚫It only works on AL register.

133
MUL operand
⚫ Unsigned Multiplication.
⚫ Operand contents are positively signed.
⚫ Operand may be general purpose register or memory location.
⚫ If operand is of 8-bit then multiply it with contents of AL.
⚫ If operand is of 16-bit then multiply it with contents of AX.
⚫ Result is stored in accumulator (AX).

⚫ E.g. (1). MUL BH // AX= AL*BH; // (+3) * (+4) = +12.

⚫ (2). MUL CX // AX=AX*CX;

134
IMUL operand
⚫ Signed Multiplication.
⚫ Operand contents are negatively signed.
⚫ Operand may be general purpose register, memory location or
index register.
⚫ If operand is of 8-bit then multiply it with contents of AL.
⚫ If operand is of 16-bit then multiply it with contents of AX.
⚫ Result is stored in accumulator (AX).

⚫ E.g. (1). IMUL BH // AX= AL*BH; // (-3) * (-4) = 12.

⚫ (2). IMUL CX // AX=AX*CX;

135
DIV operand
⚫ Unsigned Division.
⚫ Operand may be register or memory.
⚫ Operand contents are positively signed.
⚫ Operand may be general purpose register or memory
location.
⚫ AL=AX/Operand (8-bit/16-bit) & AH=Remainder.

⚫ E.g. MOV AX, 0203 // AX=0203

⚫ MOV BL, 04 // BL=04
⚫ IDIV BL // AL=0203/04=50 (i.e. AL=50 & AH=03)
136
IDIV operand
⚫ SignedDivision.
⚫ Operand may be register or memory.
⚫ Operand contents are negatively signed.
⚫ Operand may be general purpose register or memory location.
⚫ AL=AX/Operand (8-bit/16-bit) & AH=Remainder.

⚫ E.g. MOV AX, -0203 // AX=-0203

⚫ MOV BL, 04 // BL=04
⚫ DIV BL // AL=-0203/04=-50 (i.e. AL=-50 & AH=03)

137
Multiplication and Division Examples

138
139
140
141
 LOGICAL (or) Bit Manipulation
Instructions
⚫These instructions are used at the bit level.
⚫These instructions can be used for:
⚫Testing a zero bit
⚫Set or reset a bit
⚫Shift bits across registers

142
Bit Manipulation Instructions(LOGICAL Instructions)

• AND
– Especially used in clearing certain bits (masking)
xxxx xxxx AND 0000 1111 = 0000 xxxx
(clear the first four bits)
– Examples: AND BL, 0FH

• OR
– Used in setting certain bits
xxxx xxxx OR 0000 1111 = xxxx 1111
(Set the upper four bits)

143
 ⚫XOR
– Used in Inverting bits

xxxx xxxx XOR 0000 1111 = xxxxx’x’x’x’

-Example: Clear bits 0 and 1, set bits 6 and 7, invert bit 5

of register CL:

AND CL, FCH ; 1111 1100B

OR CL, C0H ; 1100 0000B
XOR CL, 20H ; 0010 0000B

144
 SHL Instruction
⚫The SHL (shift left) instruction performs a logical left
shift on the destination operand, filling the lowest bit
with 0.

mov dl,5d

shl dl,1

145
 SHR Instruction
⚫The SHR (shift right) instruction performs a logical
right shift on the destination operand. The highest bit
position is filled with a zero.

MOV DL,80d
SHR DL,1 ; DL = 40
SHR DL,2 ; DL = 10
146
 SAR Instruction
⚫SAR (shift arithmetic right) performs a right
arithmetic shift on the destination operand.

An arithmetic shift preserves the number's sign.

MOV DL,-80
SAR DL,1 ; DL = -40
SAR DL,2 ; DL = -10
147
 Shifting left n bits multiplies the operand by 2n
For example, 5 * 22 = 20

Shifting right n bits divides the operand by 2n

For example, 80 / 23 = 10

mov dl,5

shl dl,1

148
 ROL Instruction
⚫ROL (rotate) shifts each bit to the left
⚫The highest bit is copied into both the Carry flag
and into the lowest bit
⚫No bits are lost

MOV Al,11110000b
ROL Al,1 ; AL = 11100001b

MOV Dl,3Fh
ROL Dl,4 ; DL = F3h
149
 ROR Instruction
⚫ROR (rotate right) shifts each bit to the right
⚫The lowest bit is copied into both the Carry flag and
into the highest bit
⚫No bits are lost

MOV AL,11110000b
ROR AL,1 ; AL = 01111000b

MOV DL,3Fh
ROR DL,4 ; DL = F3h
150
 RCL Instruction
⚫ RCL (rotate carry left) shifts each bit to the left
⚫ Copies the Carry flag to the least significant bit
⚫ Copies the most significant bit to the Carry flag

CLC ; CF = 0
MOV BL,88H ; CF,BL = 0 10001000b
RCL BL,1 ; CF,BL = 1 00010000b
RCL BL,1 ; CF,BL = 0 00100001b
151
 RCR Instruction
⚫RCR (rotate carry right) shifts each bit to the right
⚫Copies the Carry flag to the most significant bit
⚫Copies the least significant bit to the Carry flag

STC ; CF = 1
MOV AH,10H ; CF,AH = 00010000 1
RCR AH,1 ; CF,AH = 10001000 0

152
 Branching Instructions (or)
Program Execution Transfer
Instructions
⚫These instructions cause change in the sequence of the
execution of instruction.
⚫This change can be through a condition or sometimes
unconditional.
⚫The conditions are represented by flags.

153
 ⚫CALL Des:
⚫This instruction is used to call a subroutine or function or
procedure.
⚫The address of next instruction after CALL is saved onto
stack.
⚫RET:
⚫It returns the control from procedure to calling program.
⚫Every CALL instruction should have a RET.

154
SUBROUTINE & SUBROUTINE HANDILING
INSTRUCTIONS

Main program

Subroutine A

First Instruction
Call subroutine A
Next instruction

Return
Call subroutine A
Next instruction

155
 ⚫JMP Des:
⚫This instruction is used for unconditional jump from one
place to another.

⚫Jxx Des (Conditional Jump):

⚫All the conditional jumps follow some conditional
statements or any instruction that affects the flag.

156
 Conditional Jump Table
Mnemonic Meaning
JA Jump if Above
JAE Jump if Above or Equal
JB Jump if Below
JBE Jump if Below or Equal
JC Jump if Carry
JE Jump if Equal
JNC Jump if Not Carry
JNE Jump if Not Equal
JNZ Jump if Not Zero
JPE Jump if Parity Even
JPO Jump if Parity Odd
JZ Jump if Zero
157
 ⚫Loop Des:
⚫This is a looping instruction.
⚫The number of times looping is required is placed in the CX
register.
⚫With each iteration, the contents of CX are decremented.
⚫ZF is checked whether to loop again or not.

158
 String Instructions
⚫String in assembly language is just a sequentially stored
bytes or words.
⚫There are very strong set of string instructions in 8086.
⚫By using these string instructions, the size of the program
is considerably reduced.

159
 ⚫CMPS Des, Src:
⚫It compares the string bytes or words.

⚫SCAS String:
⚫It scans a string.
⚫It compares the String with byte in AL or with word
in AX.

160
 ⚫MOVS / MOVSB / MOVSW:
⚫It causes moving of byte or word from one string to another.
⚫In this instruction, the source string is in Data Segment and
destination string is in Extra Segment.
⚫SI and DI store the offset values for source and destination
index.

161
 ⚫REP (Repeat):
⚫This is an instruction prefix.
⚫It causes the repetition of the instruction until CX becomes
zero.
⚫E.g.: REP MOVSB STR1, STR2
⚫ It copies byte by byte contents.
⚫ REP repeats the operation MOVSB until CX becomes zero.

162
 Processor Control Instructions
⚫These instructions control the processor itself.
⚫8086 allows to control certain control flags that:
⚫causes the processing in a certain direction
⚫processor synchronization if more than one microprocessor
attached.

163
 ⮚STC
⚫It sets the carry flag to 1.
⮚CLC
⚫It clears the carry flag to 0.
⮚CMC
⚫It complements the carry flag.

164
 ⮚STD:
⚫It sets the direction flag to 1.
⚫If it is set, string bytes are accessed from higher memory
address to lower memory address.

⮚CLD:
⚫It clears the direction flag to 0.
⚫If it is reset, the string bytes are accessed from lower
memory address to higher memory address.

165
 ⮚ HLT instruction – HALT processing
The HLT instruction will cause the 8086 to stop fetching and
executing instructions.

⮚NOP instruction
this instruction simply takes up three clock cycles and does no
processing.

⮚LOCK instruction
this is a prefix to an instruction. This prefix makes sure that
during execution of the instruction, control of system bus is not
taken by other microprocessor.

⮚WAIT instruction
this instruction takes 8086 to an idle condition. The
CPU will not do any processing during this.
166
 INSTRUCTION SET-summary
1.DATA TRANSFER INSTRUCTIONS

Mnemonic Meaning Format Operation

MOV Move Mov D,S (S) 🡪 (D)

XCHG Exchange XCHG D,S (S) (D)

LEA Load Effective Address LEA Reg16,EA EA 🡪 (Reg16)

PUSH pushes the operand into top of PUSH BX

stack.

POP pops the operand from top of POP BX

stack to Des.

IN transfers the operand from IN AX,0028

specified port to accumulator
register.

OUT transfers the operand from OUT 0028,BX

accumulator to specified
port.

167
 2. ARITHMETIC INSTRUCTIONS
Mnemonic Meaning Format Operation

SUB Subtract SUB D,S (D) - (S) 🡪 (D)

Borrow 🡪 (CF)

SBB Subtract with SBB D,S (D) - (S) - (CF) 🡪 (D)

borrow
DEC Decrement by one DEC D (D) - 1 🡪 (D)

NEG Negate NEG D

DAS Decimal adjust for DAS Convert the result in AL to packed
subtraction decimal format

AAS ASCII adjust for AAS (AL) difference (AH) dec by 1 if

subtraction borrow

ADD Addition ADD D,S (S)+(D) 🡪 (D) carry 🡪 (CF)

ADC Add with carry ADC D,S (S)+(D)+(CF) 🡪 (D) carry 🡪 (CF)

INC Increment by one INC D (D)+1 🡪 (D)

AAA ASCII adjust for AAA If the sum is >9, AH

addition is incremented by 1
DAA Decimal adjust for DAA Adjust AL for decimal Packed BCD
168
addition
3. Bit Manipulation Instructions(Logical Instructions)
Mnemonic Meaning Format Operation

AND Logical AND AND D,S (S) · (D) → (D)

OR Logical Inclusive OR OR D,S (S)+(D) → (D)

XOR Logical Exclusive OR XOR D,S (S) + (D)→(D)

NOT LOGICAL NOT NOT D (D) → (D)

169
Presented by C.GOKUL,AP/EEE , Velalar College of Engg & Tech, Erode
 Shift & Rotate Instructions
Mnemonic Meaning Format
SAL/SHL Shift arithmetic Left/ SAL/SHL D, Count
Shift Logical left

SHR Shift logical right SHR D, Count

SAR Shift arithmetic SAR D, Count

right

Mnemonic Meaning Format

ROL Rotate Left ROL D,Count

ROR Rotate Right ROR D,Count

RCL Rotate Left through Carry RCL D,Count

RCR Rotate right through Carry RCR D,Count

170
 4. Branching or PROGRAM EXECUTION
TRANSFER INSTRUCTIONS
• CALL - call a subroutine
• RET - returns the control from procedure to calling
program
• JMP Des – Unconditional Jump
• Jxx Des – conditional Jump (ex: JC 8000)
• Loop Des

171
 5. STRING INSTRUCTIONS
• CMPS Des, Src - compares the string bytes
• SCAS String - scans a string
• MOVS / MOVSB / MOVSW - moving of byte or
word
• REP (Repeat) - repetition of the instruction

172
 6. PROCESSOR CONTROL INSTRUCTIONS
• STC – set the carry flag (CF=1)
• CLC – clear the carry flag (CF=0)
• STD – set the direction flag (DF=1)
• CLD – clear the direction flag (DF=0)
• HLT – stop fetching & execution
• NOP – no operation(no processing)
• LOCK - control of system bus is not taken by other µP
• WAIT - CPU will not do any processing
• ESC - µP does NOP or access a data from memory for coprocessor
173
Assembler
Directives
174
Directives Expansion

175
• ASSUME Directive - The ASSUME directive is
used to tell the assembler that the name of
the logical segment should be used for a
specified segment.
• DB(define byte) - DB directive is used to
declare a byte type variable or to store a byte
in memory location.
• DW(define word) - The DW directive is used
to define a variable of type word or to reserve
storage location of type word in memory.

Presented by C.GOKUL,AP/EEE , Velalar College of Engg & Tech, Erode 176

• DD(define double word) :This directive is used to
declare a variable of type double word or restore
memory locations which can be accessed as type
double word.
• DQ (define quadword) :This directive is used to
tell the assembler to declare a variable 4 words
in length or to reserve 4 words of storage in
memory .
• DT (define ten bytes):It is used to inform the
assembler to define a variable which is 10 bytes
in length or to reserve 10 bytes of storage in
memory.
177
• END- End program .This directive indicates the
assembler that this is the end of the program
module. The assembler ignores any
statements after an END directive.
• ENDP- End procedure: It indicates the end of
the procedure (subroutine) to the assembler.
• ENDS-End Segment: This directive is used with
the name of the segment to indicate the end
of that logical segment.
• EQU - This EQU directive is used to give a
name to some value or to a symbol.
178
• PROC - The PROC directive is used to identify
the start of a procedure.
• PTR -This PTR operator is used to assign a
specific type of a variable or to a label.
• ORG -Originate : The ORG statement
changes the starting offset address of the
data.

179
 Directives examples
• ASSUME CS:CODE cs=> code segment
• ORG 3000
• NAME DB ‘THOMAS’
• POINTER DD 12341234H
• FACTOR EQU 03H

180
Assembly Language
Programming(ALP)
8086

181
 Program 1: Increment an 8-bit number

• MOV AL, 05H Move 8-bit data to AL.

• INC AL Increment AL.

Program 2: Increment an 16-bit number

• MOV AX, 0005H Move 16-bit data to AX.

• INC AX Increment AX.

Presented by C.GOKUL,AP/EEE , Velalar College of Engg & Tech, Erode 182

 Program 3: Decrement an 8-bit number

• MOV AL, 05H Move 8-bit data to AL.

• DEC AL Decrement AL.

Program 4: Decrement an 16-bit number

• MOV AX, 0005H Move 16-bit data to AX.

• DEC AX Decrement AX.

183
 Program 5: 1’s complement of an 8-bit
number.
• MOV AL, 05H Move 8-bit data to AL.
• NOT AL Complement AL.
Program 6: 1’s complement of a 16-bit
number.
• MOV AX, 0005H Move 16-bit data to AX.
• NOT AX Complement AX.

184
 Program 7: 2’s complement of an 8-bit
number.
• MOV AL, 05H Move 8-bit data to AL.
• NOT AL Complement AL.
• INC AL Increment AL

Program 8: 2’s complement of a 16-bit

number.
• MOV AX, 0005H Move 16-bit data to AX.
• NOT AX Complement AX.
• INC AX Increment AX

185
 Program 7: 2’s complement of an 8-bit
• MOV AL, 05H
number.
Move 8-bit data to AL.
• NOT AL Complement AL.
• INC AL Increment AL

Program 8: 2’s complement of a 16-bit

number.
• MOV AX, 0005H Move 16-bit data to AX.
• NOT AX Complement AX.
• INC AX Increment AX

186
 Program 9: Add two 8-bit numbers
MOV AL, 05H Move 1 8-bit number to AL.
st

MOV BL, 03H Move 2nd 8-bit number to BL.

ADD AL, BL Add BL with AL.

Program 10: Add two 16-bit numbers

MOV AX, 0005H Move 1 16-bit number to AX.
st

MOV BX, 0003H Move 2nd 16-bit number to BX.

ADD AX, BX Add BX with AX.

187
 Program 11: subtract two 8-bit numbers
MOV AL, 05H Move 1 8-bit number to AL.
st

MOV BL, 03H Move 2nd 8-bit number to BL.

SUB AL, BL subtract BL from AL.

Program 12: subtract two 16-bit numbers

MOV AX, 0005H Move 1 16-bit number to AX.
st

MOV BX, 0003H Move 2nd 16-bit number to BX.

SUB AX, BX subtract BX from AX.

188
 Program 13: Multiply two 8-bit unsigned
numbers.
MOV AL, 04H Move 1st 8-bit number to AL.
MOV BL, 02H Move 2nd 8-bit number to BL.
MUL BL Multiply BL with AL and the result will
be in AX.

Program 14: Multiply two 8-bit signed

numbers.
MOV AL, 04H Move 1st 8-bit number to AL.
MOV BL, 02H Move 2nd 8-bit number to BL.
IMUL BL Multiply BL with AL and the result will
be in AX.

189
 Program 15: Multiply two 16-bit unsigned
numbers.
MOV AX, 0004H Move 1st 16-bit number to AL.
MOV BX, 0002H Move 2nd 16-bit number to BL.
MUL BX Multiply BX with AX and the result will

be in DX:AX {4*2=0008=> 08=> AX , 00=> DX}

Program 16: Divide two 16-bit unsigned
numbers.
MOV AX, 0004H Move 1st 16-bit number to AL.
MOV BX, 0002H Move 2nd 16-bit number to BL.
DIV BX Divide BX from AX and the result will be in AX & DX
{4/2=0002=> 02=> AX ,00=>DX}
(ie: Quotient => AX , Reminder => DX )

Presented by C.GOKUL,AP/EEE , Velalar College of Engg & Tech, Erode 190

 Detailed coding
16 BIT ADDITION

191
 Detailed coding
16 BIT SUBTRACTION

192
16 BIT MULTIPLICATION

193
16 BIT DIVISION

194
 SUM of N numbers
MOV AX,0000
MOV SI,1100
MOV DI,1200
MOV CX,0005 5 NUMBERS TO BE TAKEN SUM
MOV DX,0000
L1: ADD AX,[SI]
INC SI
INC DX
CMP CX,DX
JNZ L1
MOV [1200],AX
HLT
195
 Average of N numbers
MOV AX,0000
MOV SI,1100
MOV DI,1200
MOV CX,0005 5 NUMBERS TO BE TAKEN AVERAGE
MOV DX,0000
L1: ADD AX,[SI]
INC SI
INC DX
CMP CX,DX
JNZ L1
DIV CX AX=AX/5(AVERAGE OF 5 NUMBERS)
MOV [1200],AX
HLT
Presented by C.GOKUL,AP/EEE , Velalar College of Engg & Tech,
196Erode
 FACTORIAL of N
MOV CX,0005 5 Factorial=5*4*3*2*1=120
MOV DX,0000
MOV AX,0001
L1: MUL CX
DEC DX
CMP CX,DX
JNZ L1
MOV [1200],AX
HLT

197
ASCENDING ORDER

198
199
 DECENDING ORDER

Note: change the coding JNB L1 into JB L1 in the LINE 10

200
LARGEST, smallest NUMBER IN AN ARRAY

201
LARGEST NUMBER

202
SMALLEST NUMBER

203
 Modular
Programming
204
• Generally , industry-programming projects consist of
thousands of lines of instructions or operation code.
• The size of the modules are reduced to a humanly
comprehensible and manageable level.
• Program is composed from several smaller
modules. Modules could be developed by
separate teams concurrently.OBJ modules (Object
modules).
• The .OBJ modules so produced are combined using a
LINK program.
• Modular programming techniques simplify the
software development process
205
CHARACTERISTICS of module:
1. Each module is independent of other modules.
2. Each module has one input and one output.
3. A module is small in size.
4. Programming a single function per module is a goal
Advantages of Modular Programming:
• It is easy to write, test and debug a module.
• Code can be reused.
• The programmer can divide tasks.
• Re-usable Modules can be re-used within a program
DRAWBACKS:
Modular programming requires extra time and memory

206
MODULAR PROGRAMMING:
1.LINKING & RELOCATION
2.STACKS
3.Procedures
4.Interrupts & Interrupt Routines
5.Macros

207
 LINKING &
RELOCATION
208
 LINKER
• A linker is a program used to join together several object
files into one large object file.
• The linker produces a link file which contains the binary
codes for all the combined modules.

The linker program is invoked using the following

options.
C> LINK
or
C>LINK MS.OBJ
209
• The loader is a part of the operating system
and places codes into the memory after
reading the ‘.exe’ file
• A program called locator reallocates the
linked file and creates a file for permanent
location of codes in a standard format.

210
Creation and execution of a program

211
Loader
->Loader is a utility program which takes object code as
input prepares it for execution and loads the executable
code into the memory .
->Loader is actually responsible for initializing the process
of execution.
Functions of loaders:
1.It allocates the space for program in the memory(Allocation)
2.It resolves the code between the object modules(Linking)
3. some address dependent locations in the program, address constants
must be adjusted according to allocated space(Relocation)
4. It also places all the machine instructions and data of corresponding
programs and subroutines into the memory .(Loading)

212
 Relocating loader (BSS Loader)
• When a single subroutine is changed then all the
subroutine needs to be reassembled.
• The binary symbolic subroutine (BSS) loader used
in IBM 7094 machine is relocating loader.
• In BSS loader there are many procedure
segments
• The assembler reads one sourced program and
assembles each procedure segment
independently
213
• The output of the relocating loader is the object program
• The assembler takes the source program as input; this source
program may call some external routines.
SEGMENT COMBINATION:
ASM-86 assembler regulating the way segments with the same
name are concatenated & sometimes they are overlaid.
Form of segment directive:
Segment name SEGEMENT Combine-type
Possible combine-type are:
• PUBLIC
• COMMON
• STACK
• AT
• MEMORY
214
• PUBLIC – If the segments in different modules
have the same name and combine-type PUBLIC,
then they are concatenated into a single element
in the load module. The ordering in the
concatenation is specified by the linker command.
•  COMMON – If the segments in different object
modules have the same name and the combine-
type is COMMON, then they are overlaid so that
they have the same starting address. The length of
the common segment is that of the longest
segment being overlaid.

215
• STACK – If segments in different object modules
have the same name and the combine type
STACK, then they become one segment whose
length is the sum of the lengths of the
individually specified segments. In effect, they
are combined to form one large stack
• AT – The AT combine-type is followed by an
expression that evaluates to a constant which is
to be the segment address. It allows the user to
specify the exact location of the segment in
memory.
216
Access to External Identifiers

• If an identifier is defined in an object module, then

it is said to be a local (or internal) identifier relative
to the module. If it is not defined in the module
but is defined in one of the other modules being
linked, then it is referred to as an external (or
global) identifier relative to the module.

217
Procedures
218
• Procedure is a part of code that can be called from
your program in order to make some specific task.
Procedures make program more structural and
easier to understand.
• syntax for procedure declaration:
name PROC
…………. ; here goes the code
…………. ; of the procedure ...
RET
name ENDP
here PROC is the procedure name.(used in top & bottom)
RET - used to return from OS. CALL-call a procedure
PROC & ENDP – complier directives
CALL & RET - instructions 219
 EXAMPLE 1 (call a procedure)
ORG 100h
CALL m1
MOV AX, 2
RET ; return to operating system.

m1 PROC
MOV BX, 5
RET ; return to caller.
m1 ENDP
END
• The above example calls procedure m1, does MOV BX, 5 &
returns to the next instruction after CALL: MOV AX, 2.

Presented by C.GOKUL,AP/EEE , Velalar College of Engg & Tech, Erode 220

Example 2 : several ways to pass parameters
to procedure
ORG 100h
MOV AL, 1
MOV BL, 2
CALL m2
CALL m2
CALL m2
CALL m2
RET ; return to operating system.

m2 PROC
MUL BL ; AX = AL * BL.
RET ; return to caller.
m2 ENDP
END value of AL register is update every time the
procedure is called.
final result in AX register is 16 (or 10h) 221
STACK
222
• Stack is an area of memory for keeping
temporary data.
• STACK is used by CALL & RET instructions.
PUSH -stores 16 bit value in the stack.
POP -gets 16 bit value from the stack.
• PUSH and POP instruction are especially useful
because we don't have too much registers to operate
1. Store original value of the register in stack (using
PUSH).
2. Use the register for any purpose.
3. Restore the original value of the register from stack
(using POP).
223
Example-1 (store value in STACK using PUSH
& POP)
ORG 100h
MOV AX, 1234h
PUSH AX ; store value of AX in stack.
MOV AX, 5678h ; modify the AX value.
POP AX ; restore the original value of AX.
RET
END

224
 Example 2: use of the stack is for
exchanging the values
ORG 100h
MOV AX, 1212h ; store 1212h in AX.
MOV BX, 3434h ; store 3434h in BX
PUSH AX ; store value of AX in stack.
PUSH BX ; store value of BX in stack.
POP AX ; set AX to original value of BX.
POP BX ; set BX to original value of AX.
RET
END
push 1212h and then 3434h, on pop we will
first get 3434h and only after it 1212h 225
MACROS
226
• Macros are just like procedures, but not really.
• Macros exist only until your code is compiled
• After compilation all macros are replaced with
real instructions
• several macros to make coding easier(Reduce
large & complex programs)
Example (Macro definition)
name MACRO [parameters,...]
<instructions>
ENDM
227
 Example1 : Macro Definitions
SAVE MACRO definition of MACRO name SAVE

PUSH AX
PUSH BX
PUSH CX
ENDM

RETREIVE MACRO Another definition of MACRO name RETREIVE

POP CX
POP BX
POP AX
ENDM

228
229
 MACROS with Parameters
Example:
COPY MACRO x, y ; macro named COPY with
2 parameters{x, y}
PUSH AX
MOV AX, x
MOV y, AX
POP AX
ENDM
230
 INTERRUPTS
&
INTERRUPT SERVICE
ROUTINE(ISR)
231
 INTERRUPT & ISR ?
• ‘Interrupts’ is to break the sequence of
operation.
• While the CPU is executing a program, on
‘interrupt’ breaks the normal sequence of
execution of instructions, diverts its execution
to some other program called Interrupt
Service Routine (ISR)

232
233
234
235
• Maskable Interrupt: An Interrupt that can be
disabled or ignored by the instructions of CPU
are called as Maskable Interrupt.
• Non- Maskable Interrupt: An interrupt that
cannot be disabled or ignored by the instructions
of CPU are called as Non- Maskable Interrupt.
• Software interrupts are machine instructions
that amount to a call to the designated interrupt
subroutine, usually identified by interrupt
number.  Ex: INT0 - INT255

236
237
238
239
240
241
 INTERRUPT VECTOR TABLE

256 INTERRUPTS OF 8086 ARE DIVIDED IN TO 3 GROUPS

1. TYPE 0 TO TYPE 4 INTERRUPTS-

These Are Used For Fixed Operations And Hence Are Called
Dedicated Interrupts

2. TYPE 5 TO TYPE 31 INTERRUPTS

Not Used By 8086,reserved For Higher Processors Like 80286
80386 Etc

3. TYPE 32 TO 255 INTERRUPTS

Available For User, called User Defined Interrupts These Can
Be H/W Interrupts And Activated Through Intr Line Or Can Be
S/W Interrupts. 242
⮚Type – 0 Divide Error Interrupt
Quotient is too large cant be fit in AL/AX or Divide By Zero {AX/0=∞}
⮚Type –1 Single Step Interrupt
used for executing the program in single step mode by setting Trap Flag
To Set Trap Flag PUSHF
MOV BP,SP
OR [BP+0],0100H;SET BIT8
POPF

⮚Type – 2 Non Maskable Interrupt

This Interrupt is used for executing ISR of NMI Pin (Positive Egde Signal). NMI
cant be masked by S/W

⮚Type – 3 Break Point Interrupt

used for providing BREAK POINTS in the program

⮚Type – 4 Over Flow Interrupt

used to handle any Overflow Error after signed arithmetic
243
 PRIORITY OF INTERRUPTS
Interrupt Type Priority

INT0, INT3-INT 255, Highest

NMI(INT2)

INTR

SINGLE STEP Lowest

244
 Byte &
String
Manipulation
245
 Move, compare, store, load, scan

Refer String Instructions in Instruction Set

Slide No: 160-163

246
 Byte Manipulation
Example 3:
Example 1:
MOV AX,[1000]
MOV AX,[1000]
MOV BX,[1002]
MOV BX,[1002]
AND AX,BX XOR AX,BX
MOV [2000],AX MOV [2000],AX
HLT HLT
Example 2: Example 4:
MOV AX,[1000]
MOV AX,[1000]
MOV BX,[1002]
OR AX,BX
NOT AX
MOV [2000],AX MOV [2000],AX
HLT HLT
247
Presented by C.GOKUL,AP/EEE , Velalar College of Engg & Tech, Erode
 STRING MANIPULATION
1. Copying a string (MOV SB)
MOV CX,0003 copy 3 memory locations
MOV SI,1000
MOV DI,2000
L1 CLD
MOV SB
DEC CX decrement CX
JNZ L1
HLT
248
2. Find & Replace

249
 DEPARTMENTS: CSE,IT,ECE,ECE,MECH
Regulation : 2013

UNIT-2
8086 SYSTEM
BUS STRUCTURE
250
8086 signals or Pin Diagram

Refer UNIT-1 Slide No: 43-54

251
 Minmode operation
Time-
signals (MN/MX=1)
0V=“0”, GND 1 40 Vcc multiplexed
reference AD14 AD15 5V±10% Address
for all AD13 A16/S3 Bus /Status
voltages AD12 A17/S4 Maxmode operation signals
AD11 A18/S5 signals (MN/MX=0) (outputs)
AD10 A19/S6
AD9 ___ Control Operation Mode,
AD8 BHE/S7 (HIGH) Bus (input):
Time-multiplexed AD7 INTEL ___ (in,out) 1 = minmode
Address / Data Bus AD6 8086 MN/MX
(8088 generates all
(bidirectional) AD5 ___
the needed control
AD4 RD
signals for a small
AD3 ___ ____ Status system),
Hardware AD2 HOLD (RQ/GT0)signals
interrupt requests AD1 ___ ____ (outputs)
0 = maxmode
(inputs) AD0 HLDA (RQ/GT1)
(8288 Bus
NMI ___ ______
Controller expands
2...5MHz, INTR WR (LOCK) Interrupt the status signals
1/3 duty cycle CLK __ __ acknowledge
to generate more
(input) GND 20 21 IO/M (S2) (output) 252
control signals)
__ __
MINIMUM MODE SIGNALS

253
MAXIMUM MODE SIGNALS

254
SYSTEM BUS
TIMING
255
 System Timing Diagrams
❑ T-State:
— One clock period is referred to as a T-State

T-State

— An operation takes an integer number of T-

States
❑ CPU Bus Cycle:
— A bus cycle consists of 4 or more T-States

T1 T2 T3 T4

256
 Memory Read Timing Diagrams

• Dump address on address bus.

• Issue a read ( RD ) and set M/ IO to 1.
• Wait for memory access cycle.

257
 Memory Write Timing Diagrams
• Dump address on address bus.
• Dump data on data bus.
• Issue a write ( WR ) and set M/ IO to 1.

258
 Bus Timing
During T 1 :
• The address is placed on the Address/Data bus.
• Control signals M/ IO , ALE and DT/ R specify memory or I/O, latch the address
onto the address bus and set the direction of data transfer on data bus.
During T 2 :
• 8086 issues the RD or WR signal, DEN , and, for a write, the data.
• DEN enables the memory or I/O device to receive the data for writes and the 8086 to
receive the data for reads.
During T 3 :
• This cycle is provided to allow memory to access data.
• READY is sampled at the end of T 2 .
• If low, T 3 becomes a wait state.
• Otherwise, the data bus is sampled at the end of T 3 .
During T 4 :
• All bus signals are deactivated, in preparation for next bus cycle.
• Data is sampled for reads, writes occur for writes.

259
 Setup & Hold Time

⮚Setup time – The time before the rising edge of the clock, while the data
must be valid and constant
⮚Hold time – The time after the rising edge of the clock during which the data
must remain valid and constant

260
 WAIT State

• A wait state (Tw) is an extra clocking period, inserted

between T2 and T3, to lengthen the bus cycle, allowing
slower memory and I/O components to respond.

• The READY input is sampled at the end of T2, and again,

if necessary in the middle of Tw. If READY is ‘0’ then a
Tw is inserted.
261
 Basic
configurations

262
 BASIC CONFIGURATIONS-
1.Minimum Mode 2.Maximum Mode
– Minimum mode(MN/MX=Vcc)
• Pin #33 (MN/MX) connect to +5V
• Pin 24-31 are used as memory and I/O control signal
• The control signals are generated internally by the 8086/88
• More cost-efficient
– Maximum mode(MN/MX=GND)
• Pin #33 (MN/MX) connect to Ground
• Some control signals are generated externally by the 8288
bus controller chip
• Max mode is used when math processor is used.

263
 Minimum Mode 8086 System
• 8086 is operated in minimum mode by
MN/MX pin to logic 1 ( Vcc ).
• In this mode, all the control signals are given
out by the microprocessor chip itself.

264
265
Explain Minimum mode Signals also: Refer Slide No 47-54

266
267
268
MAXIMUM MODE

269
 Explain Maximum mode Signals also: Refer Slide No 47-54

8288 – BUS CONTROLLER

270
271
272
MULTIPROCESSOR
CONFIGURATIONS

273
 Coprocessor 8087

Multiprocessor
configuration

274
 Multiprocessor configuration
• Multiprocessor Systems refer to the use of multiple
processors that executes instructions simultaneously
and communicate with each other using mail boxes and
Semaphores.

• Maximum mode of 8086 is designed to implement 3

basic multiprocessor configurations:
1. Coprocessor (8087)
2. Closely coupled (8089)
3. Loosely coupled (Multibus)

275
• Coprocessors and Closely coupled configurations are
similar in that both the 8086 and the external processor
shares the:
- Memory
- I/O system
- Bus & bus control logic
- Clock generator

276
 Co-processor – Intel 8087

• 8086 and 8087 reads  

instruction bytes and
• 8087 puts them in the
instructions respective queues
are inserted
in the 8086 • NOP
program
• 8087 instructions have
11011 as the MSB of
their first code byte

277
Coprocessor / Closely Coupled Configuration

278
 TEST pin of 8086
• Used in conjunction with the WAIT instruction in
multiprocessing environments.

• This is input from the 8087 coprocessor.

• During execution of a wait instruction, the CPU checks this

signal.

• If it is low, execution of the signal will continue; if not, it

will stop executing.

279
 1.Coprocessor Execution Example
Coprocessor cannot take control of the bus, it does everything through the CPU

280
 2.Closely Coupled Execution Example

• Closely Coupled
processor may take
control of the bus
independently.

• Two 8086’s cannot

be closely coupled.

281
 3.Loosely Coupled Configuration
• has shared system bus, system memory, and system
I/O.
• each processor has its own clock as well as its own
memory (in addition to access to the system resources).

• Used for medium to large multiprocessor systems.

• Each module is capable of being the bus master.

• Any module could be a processor capable of being a bus

master, a coprocessor configuration or a closely coupled
configuration.
282
283
 Loosely Coupled Configuration
• No direct connections between the modules.
• Each share the system bus and communicate through
shared resources.
• Processor in their separate modules can simultaneously
access their private subsystems through their local busses,
and perform their local data references and instruction
fetches independently. This results in improved degree of
concurrent processing.
• Excellent for real time applications, as separate modules
can be assigned specialized tasks
284
 Advantages of Multiprocessor Configuration

1. High system throughput can be achieved by having more than

one CPU.
2. The system can be expanded in modular form.
Each bus master module is an independent unit and normally resides on
a separate PC board. One can be added or removed without affecting the
others in the system.
3. A failure in one module normally does not affect the breakdown
of the entire system and the faulty module can be easily
detected and replaced
4. Each bus master has its own local bus to access dedicated
memory or IO devices. So a greater degree of parallel processing
can be achieved.

285
INTRODUCTION
TO ADVANCED
PROCESSORS
286
Intel family of microprocessor, bus and memory sizes

Microproces Data bus Address bus Memory size

sor width width
80186 16 20 1M

80286 16 24 16M

80386 DX 32 32 4G
80486 32 32 4G

Pentium 4 & 64 40 1T
core 2

Presented by C.GOKUL,AP/EEE , Velalar College of Engg & Tech, Erode 287

80186

288
80286

289
80386

290
 291

UNIT-3
I/O
INTERFACING
 292

Data Transfers
⌘Synchronous ----- Usually occur when
peripherals are located within the same
computer as the CPU. Close proximity
allows all state bits change at same time
on a common clock.
⌘Asynchronous ----- Do not require that
the source and destination use the same
system clock.
 293

Memory & IO Interfacing

MEMORY DEVICES I/O DEVICES

Presented by C.GOKUL,AP/EEE , Velalar College of Engg & Tech,
 294

⌘ interface memory (RAM, ROM,

EPROM'...) or I/O devices to 8086
microprocessor. Several memory chips or
I/O devices can connected to a
microprocessor. An address decoding circuit
is used to select the required I/O device
or a memory chip.
 295

IO mapped IO V/s Memory Mapped IO

Memory Mapped IO IO Mapped IO

⌘IO is treated as memory. ⌘IO is treated IO.
⌘16-bit addressing. ⌘8- bit addressing.
⌘More Decoder Hardware. ⌘Less Decoder Hardware.
⌘Can address 216=64k ⌘Can address 28=256
locations. locations.
⌘Less memory is available. ⌘Whole memory address
space is available.
 296

Memory Mapped IO IO Mapped IO

• Memory Instructions are • Special Instructions are

used. used like IN, OUT.
• Memory control signals • Special control signals
are used. are used.
• Arithmetic and logic • Arithmetic and logic
operations can be operations can not be
performed on data. performed on data.
• Data transfer b/w register • Data transfer b/w
and IO. accumulator and IO.
 297

Parallel communication
interface
INTEL 8255

Presented by C.GOKUL,AP/EEE , Velalar College of Engg & Tech,

 298

8255 PPI
• The 8255 chip is also called as Programmable
Peripheral Interface.
• The Intel’s 8255 is designed for use with Intel’s
8-bit, 16-bit and higher capability
microprocessors
• The 8255 is a 40 pin integrated circuit (IC),
designed to perform a variety of interface
functions in a computer environment.
• It is flexible and economical.
 299

PIN DIAGRAM OF 8255

 300

Signals of 8085
 8255 PIO/PPI
301

⌘It has 24 input/output lines which may be

individually programmed.
⌘2 groups of I/O pins are named as
Group A (Port-A & Port C Upper)
Group B (Port-B & Port C Lower)
⌘3 ports(each port has 8 bit)
Port A lines are identified by symbols PA0-PA7
Port B lines are identified by symbols PB0-PB7
Port C lines are identified by PC0-PC7 , PC3-PC0
ie: PORT C UPPER(PC7-PC4) , PORT C LOWER(PC3-PC0)
D0 - D7: data input/output lines for the
302

device. All information read from and

written to the 8255 occurs via these 8 data
lines. 

CS (Chip Select). If this line is a logical 0, the

microprocessor can read and write to the
8255.

RESET : The 8255 is placed into its reset

state if this input line is a logical 1
 303

• RD : This is the input line driven by the

microprocessor and should be low to
indicate read operation to 8255.
• WR : This is an input line driven by the
microprocessor. A low on this line
indicates write operation.
• A1-A0 : These are the address input lines and
are driven by the microprocessor.
 304

Control Logic
⌘CS signal is the master Chip Select
⌘A0 and A1 specify one of the two I/O Ports
CS A1 A0 Selected
0 0 0 Port A
0 0 1 Port B
0 1 0 Port C
0 1 1 Control
Register
1 X X 8255 is not
selected
Block Diagram of 8255A 305
 306

Block Diagram of 8255 (Architecture)

It has a 40 pins of 4 parts.

1. Data bus buffer
2. Read/Write control logic
3. Group A and Group B controls
4. Port A, B and C
 307

1. Data bus buffer

⌘This is a tristate bidirectional buffer used
to interface the 8255 to system data bus.
Data is transmitted or received by the
buffer on execution of input or output
instruction by the CPU.
 308

2. Read/Write control logic

⌘This unit accepts control signals ( RD, WR ) and
also inputs from address bus and issues
commands to individual group of control blocks
( Group A, Group B).
⌘It has the following pins.

CS , RD , WR , RESET , A1 , A0
 309

3. Group A and Group B controls

• These block receive control from the CPU and
issues commands to their respective ports.
Group A - PA and PCU ( PC7 –PC4)
Group B – PB and PCL ( PC3 –PC0)

a) Port A: This has an 8 bit latched/buffered

O/P and 8 bit input latch. It can be
programmed in 3 modes – mode 0, mode 1,
mode 2.
 310

b) Port B: It can be programmed in mode 0,

mode1
c) Port C : It can be programmed in mode 0
 311

CONTROL WORD REGISTER(CWR)

 312

Modes of Operation of 8255

⌘Bit Set/Reset(BSR) Mode
※Set/Reset bits in Port C
⌘I/O Mode
※Mode 0 (Simple input/output)
※Mode 1 (Handshake mode)
※Mode 2 (Bidirectional Data
Transfer)
 313

1. BSR Mode
 314
Bit/pin of port C
B3 B2 B1
selected
0 0 0 PC0
0 0 1 PC1
0 1 0 PC2
0 1 1 PC3
1 0 0 PC4
1 0 1 PC5
1 1 0 PC6
1 1 1 PC7

Concerned only with the 8-bits of Port C.

Set or Reset by control word
Ports A and B are not affected
 2. I/O MODE
315

a) Mode 0 (Simple Input or Output):

• Ports A and B are used as Simple I/O Ports

• Port C as two 4-bit ports
• Features
–Outputs are latched
–Inputs are not latched
–Ports do not have handshake or interrupt
capability
316
 317

b) Mode 1: (Input or Output with

Handshake)

• Handshake signals are exchanged

between MPU & Peripherals
• Features
– Ports A and B are used as Simple I/O Ports
– Each port uses 3 lines from Port C as
handshake signals
– Input & Output data are latched
– interrupt logic supported
 318

c) Mode 2: Bidirectional Data Transfer

• Used primarily in applications such as data

transfer between two computers
• Features
– Ports A can be configured as the bidirectional Port
– Port B in Mode 0 or Mode 1.
– Port A uses 5 Signals from Port C as handshake
signals for data transfer
– Remaining 3 Signals from Port C Used as –
Simple I/O or handshake for Port B
 319

Write a program to initialize 8255 in the configuration below.(assume address of the CW register as 23H).
(1) Port A: output with handshake
(2) Port B: input with handshake
(3) Port CL: output (4)Port CU: input

⌘Solution:
1 0 1 0 1 1 1 0 = AEH
Program:
MVI A,AEH ; LOAD CONTROL WORD

OUT 23H ; SEND CONTROL WORD

 320

Find the control word for the register arrangement

of the ports of Intel 8255 for mode 0 operation.

⌘Port A: Output, Port B: Output,

⌘Port CU: Output, Port CL: Output

Solution:

1 0 0 0 0 0 0 0 = 80H

The control word register for the above ports of Intel

8255 is 80H.
 321

Find the control word for the register arrangement

of the ports of Intel 8255 for mode 0 operation.
⌘Port A: Input, Port B: Input,
⌘Port CU: Input, Port CL: Input

Solution:

1 0 0 1 1 0 1 1 = 9BH

The control word register for the above ports of intel

8255 is 9BH.
 Basics of serial communication
1. Transmitter:
- A parallel-in, serial-out
shift register

2. Receiver: Parallel Transfer

- A serial-in, parallel-out
shift register.

-
322
TRANSMITTER 323

Receiver
 324

Serial communication
interface
INTEL 8251 USART
 325

UNIVERSAL SYNCHRONOUS ASYNCHRONOUS

RECEIVER TRANSMITTER (USART)

⌘Programmable chip designed for synchronous

and asynchronous serial data transmission
⌘28 pin DIP
⌘Coverts the parallel data into a serial stream of
bits suitable for serial transmission.
⌘Receives a serial stream of bits and convert it
into parallel data bytes to be read by a
microprocessor.
326
BLOCK DIAGRAM 327
 328

Five Sections
– Read/Write Control Logic
• Interfaces the chip with MPU
• Determine the functions according to the control word
• Monitors data flow
– Transmitter
• Converts parallel word received from MPU into serial bits
• Transmits serial bits over TXD line to a peripheral.
– Receiver
• Receives serial bits from peripheral
• Converts serial bits into parallel word
• Transfers the parallel word to the MPU
– Data Bus Buffer- 8 bit Bidirectional bus.
– Modem Controller
• Used to establish data communication modems over
telephone line
 329

Input Signals

⌘CS – Chip Select

※When this signal goes low, 8251 is selected by
MPU for communication
⌘C/D – Control/Data
※When this signal is high, the control register
or status register is addressed
※When it is low, the data buffer is addressed
※Control and Status register is differentiated by
WR and RD signals, respectively
 330

• WR – Write
– writes in the control register or sends outputs to the
data buffer.
– This connected to IOW or MEMW
• RD – Read
– Either reads a status from status register or accepts
data from the data buffer
– This is connected to either IOR or MEMR
• RESET - Reset
• CLK - Clock
– Connected to system clock
– Necessary for communication with microprocessor.
 331

CS C/D RD WR Function
0 1 1 0 MPU writes instruction in the
control register
0 1 0 1 MPU reads status from the status
register
0 0 1 0 MPU outputs the data to the Data
Buffer
0 0 0 1 MPU accepts data from the Data
Buffer
1 X X X USART is not Selected
 332

• Control Register
– 16-bit register
– This register can be accessed an output port
when the C/D pin is high
• Status Register
– Checks ready status of a peripheral
• Data Buffer
 333

Transmitter Section

⌘Accepts parallel data and converts it into

serial data
⌘Two registers
※Buffer Register
✡To hold eight bits
※Output Register
✡Converts eight bits into a stream of serial bits
※Transmits data on TxD pin with appropriate
framing bits(Start and Stop)
 334

Signals Associated with Transmitter Section

• TxD – Transmit Data

– Serial bits are transmitted on this line
• TxC – Transmitter Clock
– Controls the rate at which bits are transmitted
• TxRDY – Transmitter Ready
– Can be used either to interrupt the MPU or
indicate the status
• TxE – Transmitter Empty
– Logic 1 on this line indicate that the output
register is empty
 335

Receiver Section

⌘Accepts serial data from peripheral and

converts it into parallel data
⌘The section has two registers
※Input Register
※Buffer Register
 336

Signals Associated with Receiver Section

⌘RxD – Receive Data

※Bits are received serially on this line and converted
into parallel byte in the receiver input
⌘RxC – Receiver Clock
⌘RxRDY – Receiver Ready
※It goes high when the USART has a character in
the buffer register and is ready to transfer it to the
MPU
 337

Signals Associated with Modem Control

• DSR- Data Set Ready

– Normally used to check if the Data Set is ready when
communicating with a modem
• DTR – Data Terminal Ready
– device is ready to accept data when the 8251 is
communicating with a modem.
• RTS – Request to send Data
– the receiver is ready to receive a data byte from modem
• CTS – Clear to Send
 338

Control words
339
340
341
342
 343
Interfacing of 8255(PPI) with 8085 processor:
344
 11-345

Programming 8251
❑ 8251 mode register

7 6 5 4 3 2 1 0 Mode register

Number of Baud Rate

Parity enable
Stop bits
0: disable 00: Syn. Mode
00: invalid 1: enable 01: x1 clock
01: 1 bit 10: x16 clock
10: 1.5 bits Character length
11: x64 clock
11: 2 bits 00: 5 bits
01: 6 bits
Parity
10: 7 bits
0: odd
11: 8 bits
1: even
 11-346

❑ 8251 command register

SBR
EH IR RTS ER RxE DTR TxE command register
K

TxE: transmit enable

DTR: data terminal ready, DTR pin will be low
RxE: receiver enable
SBPRK: send break character, TxD pin will be low
ER: error reset
RTS: request to send, CTS pin will be low
IR: internal reset
EH: enter hunt mode (1=enable search for SYN character)
 11-347

❑ 8251 status register

SYNDE TxEMPT RxRD TxRD status

DSR T FE OE PE Y Y Y register

TxRDY: transmit ready

RxRDY: receiver ready
TxEMPTY: transmitter empty
PE: parity error
OE: overrun error
FE: framing error
SYNDET: sync. character detected
DSR: data set ready
 348

ANALOG TO DIGITAL (A/D) INTERFACE

 349

ADC 0808/0809
⌘The analog to digital converter chips 0808 and
0809 are 8-bit CMOS,successive
approximation converters.
⌘Successive approximation technique is one of
the fast techniques for analog to digital
conversion. The conversion delay is 100 µs at
a clock frequency of 640 kHz.
 350

BLOCK DIAGRAM ADC 0808/0809

351
 352

Interfacing ADC 0808 with 8086

353
 354

DIGITAL TO ANALOG (D/A) INTERFACE

 355

INTERFACING DIGITAL TO ANALOG

ONVERTERS
The digital to analog converters convert
binary numbers into their analog equivalent
voltages or currents.
Techniques are employed for digital to analog
conversion.
⌘i. Weighted resistor network
⌘ii. R-2R ladder network
⌘iii. Current output D/A converter
 356

⌘ The DAC find applications in areas like digitally controlled

gains, motor speed control, programmable gain amplifiers,
digital voltmeters, panel meters, etc.
⌘ In a compact disk audio player for example a 14 or16-bit D/A
converter is used to convert the binary data read off the disk
by a laser to an analog audio signal.
Characteristics :
1. Resolution: It is a change in analog output for one LSB
change in digital input.
It is given by(1/2^n )*Vref. If n=8 (i.e.8-bit DAC)
1/256*5V=39.06mV
2. Settling time: It is the time required for the DAC to settle
for a full scale code change.
 357

DAC 0800 8-bit Digital to Analog converter

Features:
i. DAC0800 is a monolithic 8-bit DAC manufactured by
National semiconductor.
ii. It has settling time around 100ms
iii. It can operate on a range of power supply voltage i.e.
from 4.5V to +18V. Usually the supply V+ is 5V or +12V.
The V- pin can be kept at a minimum of -12V.
iv. Resolution of the DAC is 39.06mV
 358

Pin Diagram of DAC 0800

 359

Interfacing of DAC0800 with 8086

 360

TIMER/COUNTER
INTEL 8253/8254
 361

Pin diagram
⌘RD: read signal 362

⌘WR: write signal

⌘CS: chip select signal
⌘A0, A1: address lines
⌘Clock :This is the clock input for the counter.
The counter is 16 bits.
⌘Out :This single output line is the signal that
is the final programmed output of the device.
⌘Gate :This input can act as a gate for the clock
input line, or it can act as a start pulse,
363
 364

Control Word Register :This internal register is used to write

information
8254 Programming

11-365
 8254 Modes
Gate is low the
count will be Mode 0: An events counter enabled with G.
paused

Gate is high
Will continue
counting

Mode 1: One-shot mode. s Counter will be reloaded

After gate high.

Gate is
High output
will be high

366
Mode 2: Counter generates a series of pulses 1 clock
pulse wide

cycle is repeated until

reprogrammed or G pin
set to 0

Mode 3: Generates a continuous square-wave with G set to 1

If count is even, 50% duty cycle

otherwise OUT is high 1 cycle 367
longer
 Mode 4: Software triggered one-shot.

In the last counting

Will be stop
(not repeated)

Mode 5: Hardware triggered one-shot. G controls similar to Mode 1.

In the last count
Out will be low

368
 369

Keyboard/Display
Controller
INTEL 8279
 370

Introduction
The INTEL 8279 is specially developed
for interfacing keyboard and display
devices to 8085/8086 microprocessor based
system
 371

Features of 8279
⌘Simultaneous keyboard and display
operations
⌘Scanned keyboard mode
⌘Scanned sensor mode
⌘8-character keyboard FIFO
⌘1 6-character display
 372

Pin Diagram
 373

4 sections
⌘Keyboard section
⌘Display section
⌘Scan section
⌘CPU interface section
374
375
 376

Keyboard section
⌘The keyboard section consists of 8 return
lines RL0 - RL7 that can be used to form
the columns of a keyboard matrix.
⌘It has two additional input : shift and
control/strobe. The keys are automatically
debounced.
⌘The two operating modes of keyboard
section are 2-key lockout and N-key
rollover.
⌘In the 2-key lockout mode, if two keys are 377

pressed simultaneously, only the first key is

recognized.
⌘In the N-key rollover mode simultaneous
keys are recognized and their codes are
stored in FIFO.
⌘The keyboard section also have an 8 x 8
FIFO (First In First Out) RAM.
⌘The FIFO can store eight key codes in the scan
keyboard mode. The status of the shift key and
control key are also stored along with key code.
The 8279 generate an interrupt signal (IRQ)when
there is an entry in FIFO.
 378

Display section

⌘The display section has eight output lines

divided into two groups A0-A3 and B0-B3.
⌘The output lines can be used either as a
single group of eight lines or as two groups
of four lines, in conjunction with the scan
lines for a multiplexed display.
⌘The output lines are connected to the
anodes through driver transistor in case of
common cathode 7-segment LEDs.
 379

⌘The cathodes are connected to scan lines

through driver transistors.

⌘The display can be blanked by BD (low)

line.

⌘The display section consists of 16 x 8

display RAM. The CPU can read from or
write into any location of the display RAM.
 380

Scan section
⌘The scan section has a scan counter and four scan
lines, SL0 to SL3.
⌘In decoded scan mode, the output of scan lines will
be similar to a 2-to-4 decoder.
⌘ In encoded scan mode, the output of scan lines
will be binary count, and so an external decoder
should be used to convert the binary count to
decoded output.
⌘The scan lines are common for keyboard and
display.
 381

CPU interface section

⌘The CPU interface section takes care of
data transfer between 8279 and the
processor.
⌘This section has eight bidirectional data
lines DB0 to DB7 for data transfer between
8279 and CPU.
⌘It requires two internal address A =0 for
selecting data buffer and A = 1 for selecting
control register of8279.
 382

⌘The control signals WR (low), RD (low), CS

(low) and A0 are used for read/write to
8279.
⌘ It has an interrupt request line IRQ, for
interrupt driven data transfer with
processor.
⌘The 8279 require an internal clock
frequency of 100 kHz. This can be obtained
by dividing the input clock by an internal
prescaler.
 383

Command Words of 8279

All the command words or status words are written or
read with A0 = 1 and CS = 0 to or from 8279.

a) Keyboard Display Mode Set : The format of the command word to select different
modes of operation of 8279 is given below with its bit definitions.

D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 D D K K K
 384

SENSOR MATRIX

SENSOR MATRIX
 385

B) Programmable clock :

⮚The clock for operation of 8279 is obtained by dividing

the external clock input signal by a programmable
constant called prescaler.
⮚ PPPPP is a 5-bit binary constant.
⮚The input frequency is divided by a decimal constant
ranging from 2 to 31, decided by the bits of an internal
prescaler, PPPPP.
D7 D6 D5 D4 D3 D2 D1 D0

0 0 1 P P P P P
 386
c) Read FIFO / Sensor RAM : The format of this command is given
below.
D7 D6 D5 D4 D3 D2 D1 D0
0 1 0 AI X A A A

AI – Auto Increment Flag

AAA – Address pointer to 8 bit FIFO RAM
X- Don’t care
✔This word is written to set up 8279 for reading FIFO/ sensor
RAM.
✔In scanned keyboard mode, AI and AAA bits are of no use. The
8279 will automatically drive data bus for each subsequent read, in
the same sequence, in which the data was entered.
✔In sensor matrix mode, the bits AAA select one of the 8 rows of
RAM.
✔If AI flag is set, each successive read will be from the subsequent
RAM location.
 387

d) Read Display RAM :

This command enables a programmer to read the display RAM data.
D7 D6 D5 D4 D3 D2 D1 D0
0 1 1 AI A A A A

❖The CPU writes this command word to 8279 to prepare it for

display RAM read operation.
❖AI is auto increment flag and AAAA, the 4-bit address points
to the 16-byte display RAM that is to be read.
❖If AI=1, the address will be automatically, incremented after
each read or write to the Display RAM.
❖The same address counter is used for reading and writing.
 388

d) Write Display RAM :

This command enables a programmer to write the display RAM data.
D7 D6 D5 D4 D3 D2 D1 D0
1 0 0 AI A A A A

AI – Auto increment Flag.

AAAA – 4 bit address for 16-bit display RAM to be
written.
e) Display Write Inhibit/Blanking :

D7 D6 D5 D4 D3 D2 D1 D0
1 0 1 X IW IW BL BL

IW - inhibit write flag

BL - blank display bit flags
 389

g) Clear Display RAM :

D7 D6 D5 D4 D3 D2 D1 D0
1 1 0 CD2 CD1 CD0 CF CA

CD2 CD1 CD0

0X - All zeros ( x don’t care ) AB=00

ENABLES CLEAR DISPLAY 10 - A3-A0 =2 (0010) and B3-B0=00 (0000)
WHEN CD2=1 11 - All ones (AB =FF), i.e. clear RAM
• CD2 must be 1 for enabling the clear display command.
• If CD2 = 0, the clear display command is invoked by setting
CA(CLEAR ALL) =1 and maintaining CD1, CD0 bits exactly
same as above.
• If CF(CLEAR FIFO RAM STATUS) =1, FIFO status is cleared
and IRQ line is pulled down and the sensor RAM pointer is set to
row 0.
•If CA=1, this combines the effect of CD and CF bits.
 390

h) End Interrupt / Error mode Set :

D7 D6 D5 D4 D3 D2 D1 D0
1 1 1 E X X X 1

E- Error mode
X- don’t care

⮚For the sensor matrix mode, this command lowers the

IRQ line and enables further writing into the RAM.
⮚Otherwise, if a change in sensor value is detected, IRQ
goes high that inhibits writing in the sensor RAM.
⮚ For N-Key roll over mode, if the E bit is programmed to
be ‘1’, the 8279 operates in special Error mode
 391

INTERRUPT
CONTROLLER
INTEL 8259
 392

⌘If we are working with an 8086, we have a

problem here because the 8086 has only two
interrupt inputs, NMI and INTR.
⌘ If we save NMI for a power failure interrupt,
this leaves only one interrupt for all the other
applications. For applications where we have
interrupts from multiple source, we use an
external device called a priority interrupt
controller ( PIC ) to the interrupt signals into
a single interrupt input on the processor.
393
 394

Architecture and Signal Descriptions of

8259
⌘Interrupt Request Register (RR): The
interrupts at IRQ input lines are handled by
Interrupt Request internally. IRR stores all the
interrupt request in it in order to serve them
one by one on the priority basis.
⌘In-Service Register (ISR): This stores all the
interrupt requests those are being served, i.e.
ISR keeps a track of the requests being served.
⌘Priority Resolver : This unit determines the 395

priorities of the interrupt requests appearing

simultaneously. The highest priority is selected and
stored into the corresponding bit of ISR during INTA
pulse. The IR0 has the highest priority while the IR7
has the lowest one, normally in fixed priority mode.
The priorities however may be altered by
programming the 8259A in rotating priority mode.
⌘Interrupt Mask Register (IMR) : This
register stores the bits required to mask the
interrupt inputs. IMR operates on IRR at the
direction of the Priority Resolver.
⌘Interrupt Control Logic: This block 396

manages the interrupt and interrupt

acknowledge signals to be sent to the CPU for
serving one of the eight interrupt requests.
This also accepts the interrupt acknowledge
(INTA) signal from CPU that causes the
8259A to release vector address on to the data
bus.
⌘Data Bus Buffer : This tristate bidirectional
buffer interfaces internal 8259A bus to the
microprocessor system data bus. Control
words, status and vector information pass
through data buffer during read or write
 397

⌘Read/Write Control Logic: This circuit

accepts and decodes commands from the CPU.
This block also allows the status of the 8259A
to be transferred on to the data bus.
⌘Cascade Buffer/Comparator: This block stores
and compares the ID’s all the 8259A used in system.
The three I/O pins CASO-2 are outputs when the
8259A is used as a master. The same pins act as inputs
when the 8259A is in slave mode. The 8259A in master
mode sends the ID of the interrupting slave device on
these lines. The slave thus selected, will send its
preprogrammed vector address on
the data bus during the next INTA pulse.
 8237DMA CONTROLLER

398
 Introduction:
⚫ Direct Memory Access (DMA) is a method of allowing data
to be moved from one location to another in a computer
without intervention from the central processor (CPU).
⚫It is also a fast way of transferring data within (and
sometimes between) computer.
⚫The DMA I/O technique provides direct access to the
memory while the microprocessor is temporarily disabled.
⚫The DMA controller temporarily borrows the address bus,
data bus and control bus from the microprocessor and
transfers the data directly from the external devices to a
series of memory locations (and vice versa).

399
 The 8237 DMA controller
• Supplies memory and I/O with control signals and addresses during DMA
transfer
• 4-channels (expandable)
– 0: DRAM refresh
– 1: Free
– 2: Floppy disk controller
– 3: Free
• 1.6MByte/sec transfer rate
• 64 KByte section of memory address capability with single programming
• “fly-by” controller (data does not pass through the DMA-only memory to I/O
transfer capability)
• Initialization involves writing into each channel:
• i) The address of the first byte of the block of data that must be transferred (called
the base address).
• ii) The number of bytes to be transferred (called the word count).

400
 8237 pins
• CLK: System clock
• CS΄: Chip select (decoder output)
• RESET: Clears registers, sets mask register
• READY: 0 for inserting wait states
• HLDA: Signals that the μp has relinquished buses
• DREQ3 – DREQ0: DMA request input for each channel
• DB7-DB0: Data bus pins
• IOR΄: Bidirectional pin used during programming
and during a DMA write cycle
• IOW΄: Bidirectional pin used during programming
and during a DMA read cycle
• EOP΄: End of process is a bidirectional signal used as input to terminate a DMA process or
as output to signal the end of the DMA transfer
• A3-A0: Address pins for selecting internal registers
• A7-A4: Outputs that provide part of the DMA transfer address
• HRQ: DMA request output
• DACK3-DACK0: DMA acknowledge for each channel.
• AEN: Address enable signal
• ADSTB: Address strobe
• MEMR΄: Memory read output used in DMA read cycle
• MEMW΄: Memory write output used in DMA write cycle

401
8237 block diagram

402
 Block Diagram Description

▪ It containing Five main Blocks.

1. Data bus buffer
2. Read/Control logic
3. Control logic block
4. Priority resolver
5. DMA channels.
403
DATA BUS BUFFER:
▪ It contain tristate ,8 bit bi-directional buffer.
▪ Slave mode ,it transfer data between
microprocessor and internal data bus.
▪ Master mode ,the outputs A8-A15 bits of
memory address on data lines
(Unidirectional).
READ/CONTROL LOGIC:
▪ It control all internal Read/Write operation.
▪ Slave mode ,it accepts address bits and control
signal from microprocessor.
▪ Master mode ,it generate address bits and control
signal.
404
Control logic block
▪ It contains ,
1. Control logic
2. Mode set register and
3. Status Register.
CONTROL LOGIC:
▪ Master mode ,It control the sequence of DMA
operation during all DMA cycles.
▪ It generates address and control signals.
▪ It increments 16 bit address and decrement 14 bit
counter registers.
▪ It activate a HRQ signal on DMA channel Request.
▪ Slave ,mode it is disabled.
405
DMA controller details

406
 Programming and
applications Case
studies
1.Traffic Light control
2.LED display
3.LCD display
4.Keyboard display interface
407 5.Alarm Controller
 1. TRAFFIC
LIGHT
CONTROL
408
 ⚫Traffic lights, which may also be known as stoplights,
traffic lamps, traffic signals, signal lights, robots or
semaphore, are signaling devices positioned at road
intersections, pedestrian crossings and other locations
to control competing flows of traffic.
⚫INTERFACING TRAFFIC LIGHT WITH 8086
The Traffic light controller section consists of 12
Nos. point led’s arranged by 4Lanes in Traffic light
interface card. Each lane has Go(Green),
Listen(Yellow) and Stop(Red) LED is being placed.

409
 LAN Direction 8086 LINES MODULES
PA.0 GO
SOUTH PA.1 LISTEN
PA.2 STOP
PA.3 GO
EAST PA.4 LISTEN
PA.5 STOP
PA.6 GO
NORTH PA.7 LISTEN
PB.0 STOP
PB.1 GO
WEST PB.2 LISTEN
PB.3 STOP
13-16 No Connection
17,189 Supply from
PWR
18,20 microcontroller
410
 CIRCUIT DIAGRAM TO INTERFACE TRAFFIC LIGHT WITH 8086

411
 8086 ALP:
1100: START: MOV BX, 1200H
MOV CX, 0008H
MOV AL,[BX]
MOV DX, CONTROL PORT
OUT DX, AL
INC BX
NEXT: MOV AL,[BX]
MOV DX, PORT A
OUT DX,AL
CALL DELAY
INC BX
LOOP NEXT
JMP START
DELAY: PUSH CX
MOV CX,0005H
REPEAT: MOV DX,0FFFFH
LOOP2: DEC DX
JNZ LOOP2
LOOP REPEAT
POP CX
412 RET
 Lookup Table
⚫1200                       80H
⚫1201                        21H,09H,10H,00H (SOUTH WAY)
⚫1205                       0CH,09H,80H,00H (EAST WAY)
⚫1209                       64H,08H,00H,04H (NOURTH WAY)
⚫120D                      24H,03H,02H,00H   (WEST WAY)
⚫1211                       END

413
 2. LED
DISPLAY

414
 Light Emitting Diodes (LED) is the most commonly used
components, usually for displaying pins digital states. Typical
uses of LEDs include alarm devices, timers and confirmation
of user input such as a mouse click or keystroke.
INTERFACING LED
Anode is connected through a resistor to GND & the Cathode
is connected to the Microprocessor pin. So when the Port
Pin is HIGH the LED is OFF & when the Port Pin is LOW
the LED is turned ON.

415
 PIN ASSIGNMENT WITH 8086

416
 INTERFACE LED WITH 8255

417
 8086 ALP LED interface
1100: START: MOV AL, 80
MOV DX, FF36
OUT DX, AL
BEGIN: MOV AL, 00
MOV DX, FF30
OUT DX, AL
CALL DELAY
MOV AL, FF
OUT DX, AL
CALL DELAY
JMP BEGIN
DELAY: MOV CX, FFFF
PO:      DEC CX
JNE PO
418
RET
 3. LCD
DISPLAY

419
420
 HARDWARE CONFIGURATION OF
LCD WITH 8051/8086/8085

421
 LCD INTERFACING WITH 8086
TRAINER KIT
⚫ GPIO- I (8255) J1 Connector
PORTS ADDRESS
Control port FF26
PORT A FF20
PORT B FF22
PORT C FF24 

⚫GPIO- I (8255) J4 Connector

PORTS ADDRESS
Control port FF36
PORT A FF30
PORT B FF32
PORT C FF34 

422
423
 LCD INTERFACING WITH
Used in UNIT 5 also 8051 TRAINER

KIT
⚫ GPIO- I (8255) J1 Connector
PORTS ADDRESS
Control port 4003
PORT A 4000
PORT B 4001
PORT C 4002 

424
425
 4. Keyboard display interface

426
 HARDWARE DESCRIPTION OF 8279 INTERFACE CARD
Keyboard and display is configured in the encoded mode. In the
encoded mode, a binary count sequence is put on the scan lines
SL0-SL3. These lines must be externally decoded to provide the
scan lines for keyboard and display. A 3 to 8 decoder 74LS138 is
provided for this purpose. The S0-S1 output lines of this decoder
are connected to the two rows of the keyboard. And QA0 to QA7
is connected to 7 Segment Display

427
 428

PIN DIAGRAM OF 8279 PIN DIAGRAMOF 74LS138

Presented by C.GOKUL,AP/EEE , Velalar College of Engg & Tech,

 429

Detecting a Matrix Keyboard Key press

430
 431
MVI A, 00H Initialize keyboard/display in encoded
OUT 81H scan keyboard 2 key lockout mode
MVI A, 34H
OUT 81H Initialize prescaler count
MVI A, 0BH Load mask pattern to enable RST 7.5
SIM mask other interrupts
EI Enable Interrupt
HERE: JMP HERE Wait for the interrupt
Interrupt service routine
MVI A, 40H Initialize 8279 in read FIFO RAM mode
OUT 81H
IN 80H Get keycode
MVI H, 62H Initialize memory pointer to point
MOV L, A 7-Segment code
MVI A, 80H : Initialize 8279 in write display RAM mode
OUT 81H
MOV A, M : Get the 7 segment code
OUT 80H : Write 7-segment code in display RAM
EI : Enable interrupt
RET : Return to main program
 432

5. ALARM
CONTROLLER
Relevant
Material
Not exact
 433

HARDWARE DESCRIPTION OF RELAY

& BUZZER INTERFACE
 434

To interface Relay and Buzzer with 8086 Trainer Kit

and To ON/OFF Relay and Buzzer card

⌘GPIO- I J1 Connecter
PORTS ADDRESS
Control port FF26
PORT A FF20
PORT B FF22
PORT C FF24 

⌘GPIO- II J1 Connecter
PORTS ADDRESS
Control port FF36
PORT A FF30
PORT B FF32
PORT C FF34 
 TEXT BOOK References
Main Book:
1. Microprocessors and Interfacing, Programming and Hardware by Doughlas V.Hall
Other Authors:
2. Microcomputer Systems: The 8086 / 8088 Family -Architecture,
Programming and Design by Yu-Cheng Liu, Glenn A.Gibson
3. INTEL Microprocessors 8086/8088, 80186/80188, 80286, 80386, 80486, Pentium,
Prentium ProProcessor, Pentium II, III, 4 by Barry B. Bery
4. Advanced microprocessor and peripherals by A K RAY
LOCAL AUTHOR:

5.8086 Microprocessor by Nagoor Kani

ONLINE MATERILALS:

www.vtulearning.com

435
 Documents References
• 8086 SYSTEM BUS STRUCTURE by Prof.L.PETER STANLEY BEBINGTON ( PROFESSOR AND
DEAN(ACADEMIC),VCET,Erode)
• I/O Interfacing by Prof.P.JAYACHANDAR , ASSOCIATE PROFESSOR and DEAN(SA),VCET,Erode
• 8086 Microprocessor by Dr. M. Gopikrishna ,Assistant Professor of Physics,Maharajas
College ,Ernakulam
• 8086 architecture By Er. Swapnil Kaware
• 8086 presentations by Gursharan Singh Tatla (Eazynotes.com)
• Interfacing 8255 by Anuja Bhakuni in Technology
• Microprocessor and-interfacing by Akshay Makadiya
• Interfacing is for microprocessor by R-THANDAIAH PRABU M.E., Lecturer – ECE
• Microprocessor - Ramesh Gaonkar
• 8086 micro processor prasadpawaskar 
• 8086 class notes-Y.N.M by MURTHY Y.N 
• Introduction to 8086 Microprocessor by Rajvir Singh
• 8086 micro processor by Poojith Chowdhary
• 8086 ASSEMBLY LANGUAGE PROGRAMMING Cutajar & Cutajar
• Intel microprocessor history by Ramzi_Alqrainy

436
 Website References
• http://80864beginner.com/
• www.eazynotes.com
• www.slideshare.net
• www.scribd.com
• www.docstoc.com
• www.slideworld.com
• www.nptel.ac.in
• http://opencourses.emu.edu.tr/
• http://engineeringppt.blogspot.in/
• http://www.pptsearchengine.net/
• www.4shared.com
• http://8085projects.info/

437
 NPTEL Lecture Materials References

• Microprocessor and Peripheral Devices by Dr.

Pramod Agarwal , IIT Roorkee
Link: http://nptel.ac.in/courses/108107029/
 
• Microprocessors and Microcontrollers by Prof.
Krishna Kumar IISc Bangalore
link: http://nptel.ac.in/courses/106108100/

438
 439

Microprocessors
⌘CPU for Computers
⌘No RAM, ROM, I/O on CPU chip itself
⌘Example: Intel's x86, Motorola’s 680x0
 440

Microcontroller
⌘A smaller computer
⌘On-chip RAM, ROM, I/O ports...
⌘Example: Motorola’s 6811, Intel’s 8051, Zilog’s
Z8 and PIC
 441

Microprocessor vs. Microcontroller

Microprocessor Microcontroller

⌘ CPU is stand-alone, RAM, ⌘ CPU, RAM, ROM, I/O and timer

are all on a single chip
ROM, I/O, timer are
separate ⌘ Fix amount of on-chip ROM,
RAM, I/O ports
⌘ Designer can decide on the
amount of ROM, RAM and ⌘ For applications in which cost,
I/O ports. power and space are critical

⌘ Not Expansive
⌘ Expansive
⌘ Single-purpose
⌘ General-purpose
 442

Microcontrollers Applications
⌘ Home
※ Appliances, intercom, telephones, security systems, garage door
openers, answering machines, fax machines, home computers,
TVs, cable TV tuner, VCR, camcorder, remote controls, video
games, cellular phones, musical instruments, sewing machines,
lighting control, paging, camera, pinball machines, toys, exercise
equipment etc.

Office
※ Telephones, computers, security systems, fax machines,
microwave, copier, laser printer, color printer, paging etc.

⌘ Auto
※ Trip computer, engine control, air bag, ABS, instrumentation,
security system, transmission control, entertainment, climate
control, cellular phone, keyless entry
443
 444

EC6504 Microprocessors and Microcontrollers

Dept: CSE,IT,ECE,MECH

UNIT-4

8051
MICROCONTROLLER
8051 CPU Operation
1. Features
2. Pin Diagram
3. Block Diagram

445
 8051 Microcontroller
• Intel introduced 8051, developed in the year 1981.

• The 8051 is an 8-bit processor

– The CPU can work on only 8 bits of data at a time

• The 8051 became widely popular after allowing

other manufactures to make and market any flavor
of the 8051.

446
 8051 Family
• The 8051 is a subset of the 8052
• The 8031 is a ROM-less 8051
– Add external ROM to it
– You lose two ports, and leave only 2 ports for I/O operations

447
 8051 Features
• 64KB Program Memory address space
• 64KB Data Memory address space
• 4K bytes of on-chip Program Memory
• 128 bytes of on-chip Data RAM
• 32 bidirectional and individually addressable I/0 lines
• Two 16-bit timer/counters
• 6-source/5-vector interrupt structure with two priority
levels
• On-chip clock oscillator

448
 Pin Description of the 8051
• 8051 family members (e.g., 8751, 89C51, 89C52,
DS89C4x0)
– Have 40 pins dedicated for various functions such as I/O, RD,
WR, address, data, and interrupts.
• DIP(dual in-line package),
• Some companies provide a 20-pin version of the 8051
with a reduced number of I/O ports for less demanding
applications

449
Pin Diagram of the 8051

450
 XTAL1 and XTAL2
• The 8051 has an on-chip oscillator but requires an
external clock to run it
– A quartz crystal oscillator is connected to inputs XTAL1 (pin19)
and XTAL2 (pin18)
– The quartz crystal oscillator also needs two capacitors of 30 pF
value

451
 XTAL1 and XTAL2 …..
• If you use a frequency source other than a crystal
oscillator, such as a TTL oscillator:
– It will be connected to XTAL1
– XTAL2 is left unconnected

452
 XTAL1 and XTAL2 …..
• The speed of 8051 refers to the maximum oscillator
frequency connected to XTAL.

• We can observe the frequency on the XTAL2 pin using

the oscilloscope.

453
 RST
• RESET pin is an input and is active high (normally low)
• Upon applying a high pulse to this pin, the microcontroller will
reset and terminate all activities

454
 EA’
• EA’, “external access’’, is an input pin and
must be connected to Vcc or GND

• Normally EA pin is connected to Vcc

• EA pin must be connected to GND to

indicate that the code or data is stored
externally.

455
 PSEN’ and ALE
• PSEN, “program store enable’’, is an
output pin
• This pin is connected to the OE pin of the
external memory.
• For External Code Memory, PSEN’ = 0

• For External Data Memory, PSEN’ = 1

• ALE pin is used for demultiplexing the

address and data.

456
 I/O Port Pins
• The four 8-bit I/O ports P0, P1, P2
and P3 each uses 8 pins.

457
 Port 0
• Port 0 is also designated as AD0-AD7.

• When connecting an 8051 to an external

memory, port 0 provides both address
and data.
• The 8051 multiplexes address and data
through port 0 to save pins.

• ALE indicates if P0 has address or data.

– When ALE=0, it provides data D0-D7
– When ALE=1, it has address A0-A7

458
 Port 1 and Port 2
• In 8051-based systems with no external
memory connection:
– Both P1 and P2 are used as simple I/O.
• In 8051-based systems with external
memory connections:
– Port 2 must be used along with P0 to provide
the 16-bit address for the external memory.
– P0 provides the lower 8 bits via A0 – A7.
– P2 is used for the upper 8 bits of the 16-bit
address, designated as A8 – A15, and it cannot
be used for I/O.

459
 Port 3
• Port 3 can be used as input or output.

• Port 3 has the additional function of

providing some extremely important
signals

460
 Pin Description Summary
PIN TYPE NAME AND FUNCTION
Vss I Ground: 0 V reference.
Vcc I Power Supply: This is the power supply voltage for normal,
idle, and power-down operation.
P0.0 - P0.7 I/O Port 0: Port 0 is an open-drain, bi-directional I/O port. Port
0 is also the multiplexed low-order address and data
bus during accesses to external program and data
memory.
P1.0 - P1.7 I/O Port 1: Port I is an 8-bit bi-directional I/O port.

P2.0 - P2.7 I/O Port 2: Port 2 is an 8-bit bidirectional I/O. Port 2 emits the
high order address byte during fetches from external
program memory and during accesses to external data
memory that use 16 bit addresses.
P3.0 - P3.7 I/O Port 3: Port 3 is an 8 bit bidirectional I/O port. Port 3 also
serves special features as explained.

461
 Pin Description Summary
PIN TYPE NAME AND FUNCTION
RST I Reset: A high on this pin for two machine cycles while the
oscillator is running, resets the device.
ALE O Address Latch Enable: Output pulse for latching the low byte
of the address during an access to external memory.
PSEN* O Program Store Enable: The read strobe to external program
memory. When executing code from the external program
memory, PSEN* is activated twice each machine cycle,
except that two PSEN* activations are skipped during
each access to external data memory.
EA*/VPP I External Access Enable/Programming Supply Voltage: Vpp
pin also receives the programming supply voltage Vpp
during Flash programming. (applies for 89c5x MCU's)

462
General Block Diagram of 8051

Interrupt 4K 128 Timer 0

Control ROM B
Timer 1
RAM

CPU

Bus Serial
OSC 4 I/O Ports
Control Port

TXD RXD
P0 P1 P2 P3 463
Detailed Block Diagram

464
 8051
Memory
Space
465
 8051 Memory Structure

External

External
60K

64K 64K

SFR

EXT INT 4K
128
EA = 0 EA = 1

Program Memory Data Memory

466
 Internal RAM Structure

Direct
Addressing
Only
SFR [ Special Function
Direct & Registers]
Indirect
Addressing
128 Byte Internal RAM

467
 Special
Function
Register [SFR]
468
Special Function Registers [SFR]

Presented by C.GOKUL,AP/EEE , Velalar College of Engg &

469
 SFR Registers & their Addresses
MOV 0E0H,#55H ;is the same as
MOV A,#55H ;which means load 55H into A (A=55H)

MOV 0F0H,#25H ;is the same as

MOV B,#25H ;which means load 25H into B (B=25H)

MOV 0E0H,R2 ;is the same as

MOV A,R2 ;which means copy R2 into A

MOV 0F0H,R0 ;is the same as

MOV B,R0 ;which means copy R0 into B

470
SFR Addresses ( 1 of 2 )

471
SFR Addresses ( 2 of 2 )

472
Example

473
 Program Status Word [PSW]

C AC F0 RS1 RS0 OV F1 P
Carry Parity
Auxiliary Carry User Flag 1

User Flag 0 Register Bank Select Overflow

474
8051 instructions that affects flag

475
 128 Byte RAM
• There are 128 bytes of RAM in the 8051.
– Assigned addresses 00 to 7FH General Purpose
• The 128 bytes are divided into 3 different Area

groups as follows:
BIT Addressable
1. A total of 32 bytes from locations 00 to 1F Area
hex are set aside for register banks and the 128 BYTE
INTERNAL
stack. RegRAM
Bank 3
2. A total of 16 bytes from locations 20H to 2FH
are set aside for bit-addressable read/write Reg Bank 2
Register
memory. Banks
Reg Bank 1
3. A total of 80 bytes from locations 30H to 7FH
Reg Bank 0
are used for read and write storage, called
scratch pad.
476
8051 RAM with addresses

477
 8051 Register Bank Structure

Bank 3 R0 R1 R2 R3 R4 R5 R6 R7
Bank 2 R0 R1 R2 R3 R4 R5 R6 R7
Bank 1 R0 R1 R2 R3 R4 R5 R6 R7
Bank 0 R0 R1 R2 R3 R4 R5 R6 R7

478
8051 Register Banks with address

479
8051 Programming Model

480
 8051 Stack
• The stack is a section of RAM used by the CPU to store
information temporarily.
– This information could be data or an address

• The register used to access the stack is called the SP

(stack pointer) register
– The stack pointer in the 8051 is only 8 bit wide, which means
that it can take value of 00 to FFH

481
 8051 Stack
• The storing of a CPU register in the stack is called a PUSH
– SP is pointing to the last used location of the stack
– As we push data onto the stack, the SP is incremented by one
– This is different from many microprocessors

• Loading the contents of the stack back into a CPU

register is called a POP
– With every pop, the top byte of the stack is copied to the
register specified by the instruction and the stack pointer is
decremented once

482
INSTRUCTION
SET OF
8051
483
 8051 Instruction Set
• The instructions are grouped into 5 groups
– Arithmetic
– Logic
– Data Transfer
– Boolean
– Branching

484
 1. Arithmetic Instructions
• ADD
– 8-bit addition between the accumulator (A) and a
second operand.
• The result is always in the accumulator.
• The CY flag is set/reset appropriately.

• ADDC
– 8-bit addition between the accumulator, a second
operand and the previous value of the CY flag.

485
 ADD Instruction
• ADD A, source ;ADD the source operand to
the accumulator
• MOV A, #03H ;load 03H into A
MOV B,#02H ;load 02H into B
ADD A,B ;add B register to accumulator
;(A = A + B)= 05

486
SUBB
– Subtract with Borrow.
– A ← A - <operand> - CY.
– The result is always saved in the
accumulator.
– The CY flag is set/reset appropriately.

487
 SUBB Instruction
• SUBB A, source ;ADD the source operand to
the accumulator
• MOV A, #03H ;load 03H into A
MOV B,#02H ;load 02H into B
SUBB A,B ;add B register to accumulator

;(A = A - B)= 01

488
• INC
– Increment the operand by one. Ex: INC DPTR
• The operand can be a register, a direct address, an
indirect address, the data pointer.

• DEC
– Decrement the operand by one. Ex: DEC B
• The operand can be a register, a direct address, an
indirect address.

• MUL AB / DIV AB
– Multiply A by B and place result in A:B.
– Divide A by B and place result in A:B.

489
 Multiplication of Numbers
MUL AB ; A × B, place 16-bit result in B and A

MOV A,#05 ;load 05H to reg. A

MOV B,#03 ;load 03H in reg. B
MUL AB ;05 * 03 = 000F where B = 00 and A = 0F

Table 6-1:Unsigned Multiplication Summary (MUL AB)

Multiplication Operand 1 Operand 2 Result

byte × byte A B A=low byte,

B=high byte

490
 Division of Numbers
MOV A,#05 ;load 05H to reg. A
MOV B,#03 ;load 03H in reg. B
DIV AB ;05/03 =>Quotient = 01,Reminder = 02

where B = 02 and A = 01

Table 6-2:Unsigned Division Summary (DIV AB)

Division Numerator Denominator Quotient Remainder
byte / byte A B A B

491
•ADD A,@Rn A = A+ memory pointed to Rn
•DA A Decimal Adjust A {BCD addition}

•ADDC A,@Rn
•SUBB A,@Rn
•INC @Ri

492
 2. Logical
instructions

493
• ANL D,S
-Performs logical AND of destination & source
-Destination : A/memory;
-Source : data/register/memory
- Eg: ANL A,#0FH ANL A,R5
• ORL D,S
-Performs logical OR of destination & source
-Destination : A/memory;
-Source : data/register/memory
- Eg: ORL A,#28H ORL A,@R0

494
•XRL D,S
-Performs logical XOR of destination & source
-Destination : A/memory;
-Source : data/register/memory
- Eg: XRL A,#28H XRL A,@R0
• CPL A
-Compliment accumulator
-gives 1’s compliment of accumulator data
• SWAP A
-Exchange the upper & lower nibbles of accumulator

495
• RL A
-Rotate data of accumulator towards left without
carry
• RLC A
- Rotate data of accumulator towards left with carry
• RR A
-Rotate data of accumulator towards right without
carry
• RRC A
- Rotate data of accumulator towards right with
carry

496
3. Data Transfer
Instructions

497
 MOV Instruction
• MOV destination, source ; copy source to destination.

• MOV A,#55H ;load value 55H into reg. A

MOV R0,A ;copy contents of A into R0
;(now A=R0=55H)
MOV R1,A ;copy contents of A into R1
;(now A=R0=R1=55H)
MOV R2,A ;copy contents of A into R2
;(now A=R0=R1=R2=55H)
MOV R3,#95H ;load value 95H into R3
;(now R3=95H)
MOV A,R3 ;copy contents of R3 into A
;now A=R3=95H
498
• MOVX
– Data transfer between the accumulator and
a byte from external data memory.
• MOVX A, @Ri
• MOVX A, @DPTR
• MOVX @Ri, A
• MOVX @DPTR, A

Presented by C.GOKUL,AP/EEE , Velalar College of Engg & Tech, Erode

499
• PUSH / POP
– Push and Pop a data byte onto the stack.
– The data byte is identified by a direct
address from the internal RAM locations.

•PUSH DPL
•POP 40H

500
• XCH
– Exchange accumulator and a byte variable
• XCH A, Rn
• XCH A, direct
• XCH A, @Ri

501
4.Boolean variable
instructions

502
CLR:
• The operation clears the specified bit indicated in
the instruction
• Ex: CLR C clear the carry
SETB:
• The operation sets the specified bit to 1.
CPL:
• The operation complements the specified bit
indicated in the instruction

503
• ANL C,<Source-bit>

-Performs AND bit addressed with the carry bit.

- Eg: ANL C,P2.7 AND carry flag with bit 7 of P2

• ORL C,<Source-bit>

-Performs OR bit addressed with the carry bit.

- Eg: ORL C,P2.1 OR carry flag with bit 1 of P2

504
• XORL C,<Source-bit>

-Performs XOR bit addressed with the carry bit.

- Eg: XOL C,P2.1 OR carry flag with bit 1 of P2

•MOV P2.3,C
•MOV C,P3.3
•MOV P2.0,C
505
5. Branching
instructions

506
• Program branching instructions are
used to control the flow of actions in
a program
• Some instructions provide decision
making capabilities and transfer
control to other parts of the program.
– e.g. conditional and unconditional
branches

507
 Jump Instructions
• All conditional jumps are short jumps
– Target address within -128 to +127 of PC

• LJMP (long jump): 3-byte instruction

– 2-byte target address: 0000 to FFFFH
– Original 8051 has only 4KB on-chip ROM

• SJMP (short jump): 2-byte instruction

– 1-byte relative address: -128 to +127

508
 Call Instructions
• LCALL (long call): 3-byte instruction
– 2-byte address
– Target address within 64K-byte range

• ACALL (absolute call): 2-byte instruction

– 11-bit address
– Target address within 2K-byte range

509
• The 8051 provides 2 forms for the return
instruction:
– Return from subroutine – RET
– Return from ISR – RETI

510
511
 8051
Addressing
Modes
512
 8051 Addressing Modes
• The CPU can access data in various ways, which are
called addressing modes

1. Immediate
2. Register
3. Direct
4. Register indirect
5. External Direct

513
 1. Immediate Addressing Mode
• The source operand is a constant.
• The immediate data must be preceded by the pound sign, “#”
• Can load information into any registers, including 16-bit DPTR
register
– DPTR can also be accessed as two 8-bit registers, the high byte DPH and
low byte DPL

514
 2. Register Addressing Mode
• Use registers to hold the data to be manipulated.

• The source and destination registers must match in size.

MOV DPTR,A will give an error

• The movement of data between Rn registers is not allowed

MOV R4,R7 is invalid
515
 3. Direct Addressing Mode
• It is most often used the direct addressing mode to
access RAM locations 30 – 7FH.
• The entire 128 bytes of RAM can be accessed.

• Contrast this with immediate addressing mode, there is

no “#” sign in the operand.

516
 Stack and Direct Addressing Mode
• Only direct addressing mode is allowed for pushing or
popping the stack.

• PUSH A is invalid.

• Pushing the accumulator onto the stack must be coded

as PUSH 0E0H.

517
 4. Register Indirect Addressing Mode
• A register is used as a pointer to the data.
• Only register R0 and R1 are used for this purpose.
• R2 – R7 cannot be used to hold the address of an
operand located in RAM.
• When R0 and R1 hold the addresses of RAM locations,
they must be preceded by the “@” sign.

518
 Register Indirect Addressing Mode
• Write a program to copy the value 55H into RAM memory locations 40H
to 41H using (a) direct addressing mode, (b) register indirect addressing
mode without a loop, and (c) with a loop.

519
 Register Indirect Addressing Mode
• The advantage is that it makes accessing data dynamic
rather than static as in direct addressing mode.
• Looping is not possible in direct addressing mode.

• Write a program to clear 16 RAM locations starting at

RAM address 60H.

520
 5. External Direct
• External Memory is accessed.

• There are only two commands that use External Direct

addressing mode:
– MOVX A, @DPTR
MOVX @DPTR, A

• DPTR must first be loaded with the address of external

memory.

521
 8051
Assembly
Language
Programming(ALP)
522
ADDITION OF TWO 8 bit Numbers
ADDRESS LABEL MNEMONICS

9100 START CLR C

MOV R0, #00
MOV A,#05
MOV B,#03
ADD A,B
MOV DPTR,#9200
JNC AHEAD
INC R0
AHEAD MOV X @DPTR,A
INC DPTR
MOV A,R0
MOV X @DPTR,A
HERE SJMP HERE

523
SUBTRACTION OF TWO 8 bit Numbers
ADDRESS LABEL MNEMONICS
9100 START CLR C
MOV R0, #00
MOV A,#05
MOV B,#03
SUBB A,B
MOV DPTR,#9200
JNC AHEAD
INC R0

AHEAD MOV X @DPTR,A

INC DPTR
MOV A,R0
MOV X @DPTR,A

HERE SJMP HERE

524
 Multiplication Concept
MUL AB ; A × B, place 16-bit result in B and A

MOV A,#25H ;load 25H to reg. A

MOV B,#65H ;load 65H in reg. B
MUL AB ;25H * 65H = E99 where B = 0EH and A = 99H

Table 6-1:Unsigned Multiplication Summary (MUL AB)

Multiplication Operand 1 Operand 2 Result

byte × byte A B A=low byte,

B=high byte

525
 Division Concept
DIV AB ; divide A by B
• MOV A,#95H ;load 95 into A
• MOV B,#10H ;load 10 into B
• DIV AB ;now A = 09 (quotient) and B = 05 (remainder)

Table 6-2:Unsigned Division Summary (DIV AB)

Division Numerator Denominator Quotient Remainder
byte / byte A B A B

526
 DIVISION OF TWO 8 bit
MULTIPLICATION OF TWO
Numbers
8 bit Numbers
Address Label Mnemonics Address Label Mnemonics

9000
9000
START MOV A,#05 START MOV A,#05

MOV F0,#03 MOV F0,#03

MUL AB DIV AB

MOV DPTR,#9200 MOV DPTR,#9200

MOVX @ DPTR,A MOVX @ DPTR,A

INC DPTR
INC DPTR

MOV A,F0
MOV A,F0
MOVX @DPTR,A
MOVX @DPTR,A
HERE SJMP HERE
HERE SJMP HERE
527
 Average of Five(or N) 8 bit Numbers
MOV 40H, #05H store I st number in location 40H
MOV 41H, #04H
MOV 42H, #03H
MOV 43H, #02H
MOV 44H, #01H
MOV R0, #40H store I st number address 40H in R0
MOV R5, #05H store the number 05H in R5
MOV B,R5 store the number 05H in B
CLR A Clear Acc
LOOP: ADD A,@R0
INC R0
DJNZ R5,LOOP
DIV AB
MOV 55H,A Save the quotient in location 55H
END
528
 Checking an input bit
JNB (jump if no bit) ; JB (jump if bit = 1)

529
Switch Register Banks

530
Pushing onto Stack

531
Popping from Stack

532
Looping

533
Loop inside a Loop (Nested Loop)

534
Conditional Jump Example

535
Conditional Jump Example

536
 537

EC6504 Microprocessors and Microcontrollers

Dept: CSE,IT,ECE,MECH

UNIT-5
INTERFACING
MICROCONTROLLER

Presented by
C.GOKUL,AP/EEE
 8051
TIMERS
538
 8051 Timer/Counter
OS
÷12
C
TLx THx TFx
(8 Bit) (8 Bit) (1 Bit)

INTERRUPT

539
 TMOD Register

GATE:
When set, timer/counter x is enabled, if INTx pin is high
and TRx is set.
When cleared, timer/counter x is enabled, if TRx bit set.

C/T*:
When set, counter operation (input from Tx input pin).
When cleared, timer operation (input from internal clock).

540
 TMOD Register

The TMOD byte is not bit addressable.

541
TCON Register

542
 8051 Timer Modes
8051 TIMERS

Timer 0 Timer 1

Mode 0 Mode 0

Mode 1 Mode 1

Mode 2 Mode 2

Mode 3

543
 TIMER 0
OSC ÷12

TL0 TH0 TF0

INTERRUPT

544
 TIMER 0 – Mode 0
13 Bit Timer / Counter
OS ÷1
C 2
TL0 TH0 INTERRUPT
TF0
(5 Bit) (8 Bit)

Maximum Count = 1FFFh (0001111111111111)

545
 TIMER 0 – Mode 1
16 Bit Timer / Counter
OS ÷1
C 2
TL0 TH0 INTERRUPT
TF0
(8 Bit) (8 Bit)

Maximum Count = FFFFh (1111111111111111)

546
 TIMER 0 – Mode 2
8 Bit Timer / Counter with AUTORELOAD

OS ÷1
C 2
TL0 TH0 INTERRUPT
TF0
(8 Bit) (8 Bit)

Reload

TH0
(8 Bit)

Maximum Count = FFh (11111111)

547
 TIMER 0 – Mode 3
Two - 8 Bit Timer / Counter
OS ÷1
C 2
TL0 INTERRUPT
TF0
(8 Bit)

OSC ÷12 TH0 INTERRUPT

TF1
(8 Bit)

548
 TIMER 1
OSC ÷12

TL1 TH1 TF1

INTERRUP
T

549
 TIMER 1 – Mode 0
13 Bit Timer / Counter
OS ÷1
C 2
TL1 TH1 INTERRUPT
TF1
(5 Bit) (8 Bit)

Maximum Count = 1FFFh (0001111111111111)

550
 TIMER 1 – Mode 1
16 Bit Timer / Counter
OS ÷1
C 2
TL1 TH1 INTERRUPT
TF1
(8 Bit) (8 Bit)

Maximum Count = FFFFh (1111111111111111)

551
 TIMER 1 – Mode 2
8 Bit Timer / Counter with AUTORELOAD

OS ÷1
C 2
TL1 TH1 INTERRUPT
TF1
(8 Bit) (8 Bit)

Reload

TH1
(8 Bit)

Maximum Count = FFh (11111111)

552
 Programming Timers
• Example: Indicate which mode and which timer are
selected for each of the following.
(a) MOV TMOD, #01H (b) MOV TMOD, #20H (c) MOV
TMOD, #12H

• Solution: We convert the value from hex to binary.

(a) TMOD = 00000001, mode 1 of timer 0 is selected.
(b) TMOD = 00100000, mode 2 of timer 1 is selected.
(c) TMOD = 00010010, mode 2 of timer 0, and mode 1 of timer 1

are selected.

553
 Programming Timers
• Find the timer’s clock frequency and its period for
various 8051-based system, with the crystal frequency
11.0592 MHz when C/T bit of TMOD is 0.

• Solution:

1/12 × 11.0529 MHz = 921.6 MHz;

T = 1/921.6 kHz = 1.085 us

554
 555

Presented by C.GOKUL,AP/EEE , Velalar College of Engg & Tech,

8051
Serial
Port 556
 Basics of Serial Communication
• Computers transfer data in two ways:
– Parallel: Often 8 or more lines (wire conductors) are used to
transfer data to a device that is only a few feet away.

– Serial: To transfer to a device located many meters away, the

serial method is used. The data is sent one bit at a time.

557
 Basics of Serial Communication
• Serial data communication uses two methods
– Synchronous method transfers a block of data at a time

– Asynchronous method transfers a single byte at a time

• There are special IC’s made by many manufacturers for

serial communications.
– UART (universal asynchronous Receiver transmitter)

– USART (universal synchronous-asynchronous Receiver-

transmitter)

558
 Asynchronous – Start & Stop Bit
• Asynchronous serial data communication is widely used
for character-oriented transmissions
– Each character is placed in between start and stop bits, this is
called framing.
– Block-oriented data transfers use the synchronous method.

• The start bit is always one bit, but the stop bit can be
one or two bits

• The start bit is always a 0 (low) and the stop bit(s) is 1

(high)

559
Asynchronous – Start & Stop Bit

560
 Data Transfer Rate
• The rate of data transfer in serial data communication is
stated in bps (bits per second).

• Another widely used terminology for bps is baud rate.

– It is modem terminology and is defined as the number of
signal changes per second
– In modems, there are occasions when a single change of signal
transfers several bits of data

• As far as the conductor wire is concerned, the baud rate

and bps are the same.

561
 8051 Serial Port
• Synchronous and Asynchronous
• SCON Register is used to Control
• Data Transfer through TXd & RXd pins
• Some time - Clock through TXd Pin
• Four Modes of Operation:

Mode 0 :Synchronous Serial Communication

Mode 1 :8-Bit UART with Timer Data Rate
Mode 2 :9-Bit UART with Set Data Rate
Mode 3 :9-Bit UART with Timer Data Rate

562
Registers related to Serial
Communication

1. SBUF Register

2. SCON Register

3. PCON Register

563
 SBUF Register
• SBUF is an 8-bit register used solely for serial communication.
• For a byte data to be transferred via the TxD line, it must be
placed in the SBUF register.
• The moment a byte is written into SBUF, it is framed with the
start and stop bits and transferred serially via the TxD line.
• SBUF holds the byte of data when it is received by 8051 RxD
line.
• When the bits are received serially via RxD, the 8051 deframes
it by eliminating the stop and start bits, making a byte out of
the data received, and then placing it in SBUF.

564
 SBUF Register
• Sample Program:

565
 SCON Register

SM0 SM1 SM2 REN TB8 RB8 TI RI

Set when a Cha-

ractor received
Set to Enable
Serial Data
reception Set when Stop bit Txed

Enable Multiprocessor 9th Data Bit 9th Data Bit

Communication Mode Sent in Mode 2,3 Received in Mode 2,3

566
 8051 Serial Port – Mode 0
The Serial Port in Mode-0 has the following features:

1. Serial data enters and exits through RXD

2. TXD outputs the clock

3. 8 bits are transmitted / received

4. The baud rate is fixed at (1/12) of the oscillator frequency

567
 8051 Serial Port – Mode 1
The Serial Port in Mode-1 has the following features:

1. Serial data enters through RXD

2. Serial data exits through TXD
3. On receive, the stop bit goes into RB8 in SCON
4. 10 bits are transmitted / received
1. Start bit (0)
2. Data bits (8)
3. Stop Bit (1)
5. Baud rate is determined by the Timer 1 over flow rate.

568
 8051 Serial Port – Mode 2
The Serial Port in Mode-2 has the following features:

1. Serial data enters through RXD

2. Serial data exits through TXD
3. 9th data bit (TB8) can be assign value 0 or 1
4. On receive, the 9th data bit goes into RB8 in SCON
5. 11 bits are transmitted / received
1.Start bit (0)
2.Data bits (9)
3.Stop Bit (1)
6. Baud rate is programmable

569
 8051 Serial Port – Mode 3
The Serial Port in Mode-3 has the following features:

1. Serial data enters through RXD

2. Serial data exits through TXD
3. 9th data bit (TB8) can be assign value 0 or 1
4. On receive, the 9th data bit goes into RB8 in SCON
5. 11 bits are transmitted / received
1.Start bit (0)
2.Data bits (9)
3.Stop Bit (1)
6. Baud rate is determined by Timer 1 overflow rate.

570
 Programming Serial Data Transmission
1. TMOD register is loaded with the value 20H, indicating the use of timer
1 in mode 2 (8-bit auto-reload) to set baud rate.
2. The TH1 is loaded with one of the values to set baud rate for serial data
transfer.
3. The SCON register is loaded with the value 50H, indicating serial mode
1, where an 8- bit data is framed with start and stop bits.
4. TR1 is set to 1 to start timer 1
5. TI is cleared by CLR TI instruction
6. The character byte to be transferred serially is written into SBUF
register.
7. The TI flag bit is monitored with the use of instruction JNB TI, xx to see
if the character has been transferred completely.
8. To transfer the next byte, go to step 5
571
 Programming Serial Data Reception
1. TMOD register is loaded with the value 20H, indicating the use of timer 1
in mode 2 (8-bit auto-reload) to set baud rate.
2. TH1 is loaded to set baud rate
3. The SCON register is loaded with the value 50H, indicating serial mode 1,
where an 8- bit data is framed with start and stop bits.
4. TR1 is set to 1 to start timer 1
5. RI is cleared by CLR RI instruction
6. The RI flag bit is monitored with the use of instruction JNB RI, xx to see if
an entire character has been received yet
7. When RI is raised, SBUF has the byte, its contents are moved into a safe
place.
8. To receive the next character, go to step 5.

572
 Doubling Baud Rate
• There are two ways to increase the baud rate of data
transfer
1. By using a higher frequency crystal
2. By changing a bit in the PCON register

• PCON register is an 8-bit register.

• When 8051 is powered up, SMOD is zero

• We can set it to high by software and thereby double the baud rate.

573
Doubling Baud Rate (cont…)

574
 8051
Interrupts
575
 INTERRUPTS
• An interrupt is an external or internal event that
interrupts the microcontroller to inform it that a device
needs its service

• A single microcontroller can serve several devices by two

ways:
1. Interrupt
2. Polling

576
 Interrupt Vs Polling
1. Interrupts
– Whenever any device needs its service, the device notifies the
microcontroller by sending it an interrupt signal.
– Upon receiving an interrupt signal, the microcontroller
interrupts whatever it is doing and serves the device.
– The program which is associated with the interrupt is called the
interrupt service routine (ISR) or interrupt handler.
2. Polling
– The microcontroller continuously monitors the status of a
given device.
– When the conditions met, it performs the service.
– After that, it moves on to monitor the next device until every
one is serviced.
577
 Interrupt Vs Polling
• The polling method is not efficient, since it wastes much of
the microcontroller’s time by polling devices that do not
need service.
• The advantage of interrupts is that the microcontroller can
serve many devices (not all at the same time).
• Each devices can get the attention of the microcontroller
based on the assigned priority.
• For the polling method, it is not possible to assign priority
since it checks all devices in a round-robin fashion.
• The microcontroller can also ignore (mask) a device request
for service in Interrupt.
578
 Steps in Executing an Interrupt
1. It finishes the instruction it is executing and saves the address of
the next instruction (PC) on the stack.
2. It also saves the current status of all the interrupts internally (i.e:
not on the stack).
3. It jumps to a fixed location in memory, called the interrupt vector
table, that holds the address of the ISR.
4. The microcontroller gets the address of the ISR from the
interrupt vector table and jumps to it.
5. It starts to execute the interrupt service subroutine until it
reaches the last instruction of the subroutine which is RETI
(return from interrupt).
6. Upon executing the RETI instruction, the microcontroller returns
to the place where it was interrupted.
579
 Six Interrupts in 8051
Six interrupts are allocated as follows:
1. Reset – power-up reset.

2. Two interrupts are set aside for the timers.

– one for timer 0 and one for timer 1

3. Two interrupts are set aside for hardware external

interrupts.
– P3.2 and P3.3 are for the external hardware interrupts INT0
(or EX1), and INT1 (or EX2)

4. Serial communication has a single interrupt that

belongs to both receive and transfer.
580
 What events can trigger Interrupts?
• We can configure the 8051 so that any of the following
events will cause an interrupt:

– Timer 0 Overflow.
– Timer 1 Overflow.
– Reception/Transmission of Serial Character.
– External Event 0.
– External Event 1.

• We can configure the 8051 so that when Timer 0

Overflows or when a character is sent/received, the
appropriate interrupt handler routines are called.
581
 8051 Interrupt Vectors

Presented by C.GOKUL,AP/EEE , Velalar College of Engg & Tech, Erode

582
 8051 Interrupt related Registers
• The various registers associated with the use of
interrupts are:
– TCON - Edge and Type bits for External Interrupts 0/1

– SCON - RI and TI interrupt flags for RS232

– IE - Enable interrupt sources

– IP - Specify priority of interrupts

583
 Enabling and Disabling an Interrupt
• Upon reset, all interrupts are disabled (masked),
meaning that none will be responded to by the
microcontroller if they are activated.

• The interrupts must be enabled by software in order for

the microcontroller to respond to them.

• There is a register called IE (interrupt enable) that is

responsible for enabling (unmasking) and disabling
(masking) the interrupts.

584
 Interrupt Enable (IE) Register

--

• EA : Global enable/disable.
• --- : Reserved for additional interrupt hardware.

MOV IE,#08h
• ES : Enable Serial port interrupt.
or • ET1 : Enable Timer 1 control bit.
SETB ET1
• EX1 : Enable External 1 interrupt.
• ET0 : Enable Timer 0 control bit.
• EX0 : Enable External 0 interrupt.

585
 Enabling and Disabling an Interrupt
• Example: Show the instructions to (a) enable the serial interrupt,
timer 0 interrupt, and external hardware interrupt 1 and (b)
disable (mask) the timer 0 interrupt, then (c) show how to disable
all the interrupts with a single instruction.
• Solution:
– (a) MOV IE,#10010110B ;enable serial, timer 0, EX1
• Another way to perform the same manipulation is:
– SETB IE.7 ;EA=1, global enable
– SETB IE.4 ;enable serial interrupt
– SETB IE.1 ;enable Timer 0 interrupt
– SETB IE.2 ;enable EX1
– (b) CLR IE.1 ;mask (disable) timer 0 interrupt only
– (c) CLR IE.7 ;disable all interrupts
586
 Interrupt Priority
• When the 8051 is powered up, the priorities are assigned according
to the following.

• In reality, the priority scheme is nothing but an internal polling

sequence in which the 8051 polls the interrupts in the sequence
listed and responds accordingly.

587
 Interrupt Priority
• We can alter the sequence of interrupt priority by assigning a
higher priority to any one of the interrupts by programming a
register called IP (interrupt priority).
• To give a higher priority to any of the interrupts, we make the
corresponding bit in the IP register high.

588
 Interrupt Priority (IP) Register

PS PT1 PX1 PT0

Reserved
PX0

Serial Port
INT 0 Pin
Timer 1 Pin

INT 1 Pin Timer 0 Pin

Priority bit=1 assigns high priority

Priority bit=0 assigns low priority

589
 590

KEYBOARD
INTERFACING
 KEYBOARD INTERFACING
• Keyboards are organized in a matrix of rows
and columns
The CPU accesses both rows and columns
through ports .
• ƒTherefore, with two 8-bit ports, an 8 x 8
matrix of keys can be connected to a
microprocessor
When a key is pressed, a row and a
column make a contact

591
• Otherwise, there is no connection
between rows and columns
• ‰In IBM PC keyboards, a single
microcontroller takes care of hardware
and software interfacing
• A 4x4 matrix connected to two ports
The rows are connected to an
output port and the columns are
connected to an input port

592
4x4 matrix

593
594
595
• Identify the row and column of the pressed key for
each of the following.
(a) D3 – D0 = 1110 for the row, D3 – D0 = 1011
for the column
(b) D3 – D0 = 1101 for the row, D3 – D0 = 0111
for the column
Solution:
(a) The row belongs to D0 and the column
belongs to D2; therefore, key number 2 was
pressed.
(b) The row belongs to D1 and the column
belongs to D3; therefore, key number 7 was
pressed.
596
597
598
Stepper Motor
Interfacing

599
 Stepper Motor Interfacing
• Stepper motor is a widely used device that
translates electrical pulses into mechanical movement.
• Stepper motor is used in applications such as; disk
drives, dot matrix printer, robotics etc
• It has a permanent magnet rotor called the shaft which is
surrounded by a stator. Commonly used stepper motors
have four stator windings
• Such motors are called as four-phase or unipolar stepper
motor.

600
601
602
 Step angle:
• Step angle is defined as the minimum degree of rotation
with a single step.
• No of steps per revolution = 360° / step angle
• Steps per second = (rpm x steps per revolution) / 60
• Example: step angle = 2°
• No of steps per revolution = 180

603
A switch is connected to pin P2.7. Write an ALP to monitor the
status of the SW. If SW = 0, motor moves clockwise and if
SW = 1, motor moves anticlockwise

⚫ SETB P2.7
⚫ MOV A, #66H
⚫ MOV P1,A
⚫ TURN: JNB P2.7, CW
⚫ RL A
⚫ ACALL DELAY
⚫ MOV P1,A
⚫ SJMP TURN
⚫ CW: RR A
⚫ ACALL DELAY
⚫ MOV P1,A
⚫ SJMP TURN
604
 Full step

605
LCD Interfacing
{before discussed in Unit 3 LCD
interfacing using 8086}

Slide number 127,128 in

Unit 3

606
 Already discussed in UNIT 3 also

607
 HARDWARE CONFIGURATION OF
LCD WITH 8051/8086/8085

608
 LCD INTERFACING WITH 8051 TRAINER
KIT
⚫ GPIO- I (8255) J1 Connector
PORTS ADDRESS
Control port 4003
PORT A 4000
PORT B 4001
PORT C 4002 

609
610
A/D Interfacing
{before discussed in Unit 3 A/D
interfacing using 8086}

611
 Interfacing ADC to 8051
ADC0804 is an 8 bit successive approximation analogue to digital
converter from National semiconductors. The features of ADC0804 are
 differential analogue voltage inputs, 0-5V input voltage range, no zero
adjustment, built in clock generator, reference voltage can be externally
adjusted to convert smaller analogue voltage span to 8 bit resolution etc.

612
 Steps for converting the analogue input  and reading the
output from ADC0804

• Make CS=0 and send a low to high pulse to WR pin to

start the conversion.
• Now keep checking the INTR pin.  INTR will be 1 if
conversion is not finished and INTR will be 0 if
conversion is finished.
• If conversion is not finished (INTR=1) , poll until it is
finished.
• If conversion is finished (INTR=0), go to the next step.
• Make CS=0 and send a high to low pulse to RD pin to
read the data from the ADC.
613
614
The circuit initiates the ADC to convert a given analogue input , then
accepts the corresponding digital data and displays it on the LED
array connected at P0. For example, if the analogue input voltage Vin
is 5V then all LEDs will glow indicating 11111111 in binary which is
the equivalent of 255 in decimal. AT89s51 is the microcontroller used
here. Data out pins (D0 to D7) of the ADC0804 are connected to the
port pins P1.0 to P1.7 respectively. LEDs D1 to D8 are connected to
the port pins P0.0 to P0.7 respectively. Resistors R1 to R8 are current
limiting resistors. In simple words P1 of the microcontroller is the
input port and P0 is the output port. Control signals for the ADC
(INTR, WR, RD and CS) are available at port pins P3.4 to P3.7
respectively. Resistor R9 and capacitor C1 are associated with the
internal clock circuitry of the ADC. Preset resistor R10 forms a voltage
divider which can be used to apply a particular input analogue
voltage to the ADC. Push button S1, resistor R11  and capacitor C4
forms a debouncing reset mechanism. Crystal X1 and capacitors
C2,C3 are associated with the clock circuitry of the microcontroller.

615
Program:
MOV P1,#11111111B // initiates P1 as the input port
MAIN: CLR P3.7 // makes CS=0
SETB P3.6 // makes RD high
CLR P3.5 // makes WR low
SETB P3.5 // low to high pulse to WR for starting
conversion
WAIT: JB P3.4,WAIT // polls until INTR=0
CLR P3.7 // ensures CS=0
CLR P3.6 // high to low pulse to RD for reading the
data from ADC
MOV A,P1 // moves the digital data to accumulator CPL A
// complements the digital data
MOV P0,A // outputs the data to P0 for the LEDs SJMP MAIN
// jumps back to the MAIN program END

616
Presented by C.GOKUL,AP/EEE , Velalar College of Engg & Tech, Erode
D/A Interfacing
{before discussed in Unit 3 D/A
interfacing using 8086}

617
 Digital-to-analog (DAC) converter
• The digital-to-analog converter (DAC) is a device widely used to convert
digital pulses to analog signals.
Two methods of creating a DAC:
Binary weighted and R/2R ladder.
The vast majority of integrated circuit DACs, including the MC1408
(DAC0808) used in this section, use the R/2R method since it can achieve a
much higher degree of precision. The first criterion for judging a DAC is its
resolution, which is a function of the number of binary inputs. The
common ones are 8, 10, and 12 bits. The number of data bit inputs
decides the resolution of the DAC since the number of analog output
levels is equal to 2″, where n is the number of data bit inputs. Therefore,
an 8-input DAC such as the DAC0808 provides 256 discrete voltage (or
current) levels of output.
Similarly, the 12-bit DAC provides 4096 discrete voltage levels. There
are also 16-bit DACs, but they are more expensive.
618
8051 Connection to DAC808

619
program to send data to the DAC to generate
a stair-step ramp

620
 SENSOR
INTERFACING
take temperature sensor for example

621
 8051 WITH TEMPERATURE SENSOR

622
623
 EXTERNAL
MEMORY
INTERFACING
624
 Access to External Memory
• Port 0 acts as a multiplexed address/data bus. Sending
the low byte of the program counter (PCL) as an
address.
• Port 2 sends the program counter high byte (PCH)
directly to the external memory.
• The signal ALE operates as in the 8051 to allow an
external latch to store the PCL byte while the multiplexed
bus is made ready to receive the code byte from the
external memory.
• Port 0 then switches function and becomes the data bus
receiving the byte from memory.

625
 626
Presented by C.GOKUL,AP/EEE , Velalar College of Engg & Tech, Erode
 Books References
⚫Mohamed Ali Mazidi, Janice Gillispie Mazidi, Rolin
McKinlay, “The 8051 Microcontroller and Embedded
Systems: Using Assembly and C”
⚫Programming and Interfacing the 8051 Microcontroller
by Sencer Yeralan ,Ashutosh Ahluwalia
⚫The 8051 Microcontroller by by I. Scott MacKenzie
⚫Programming & Customizing the 8051 Microcontroller
by Michael Predko
⚫Microcontrollers by RajKamal

627
 Documents References
• 8051 microcontroller by Suresh P. Nair[ME, (PhD)] MIEEE Professor&Head Department of Electronics and
Communication Engineering Royal College of Engineering and Technology
• 8051 Microcontroller by Dr. M. Gopikrishna ,Assistant Professor of Physics,Maharajas College ,Ernakulam
• 8051 Microcontroller By Er. Swapnil Kaware
• 8051 MICROCONTROLLER by Prathyusha Institute of Technology & Management in Education
• 8051 MICROCONTROLLER by Prathyusha Institute of Technology & Management in Education
• www.pantechsolutions.net/
• Embedded systems, 8051 microcontroller by Amandeep Alag in Education
• 8051 microcontroller features by Tech_MX in Technology
• 8051 microcontroller by Gaurav Verma in Engineering
• 8051 (microcontroller)class1 by Nitin Ahire in Education
• 8051 microcontroller by Bibek Kattel in Education
• 8051 microcontroller by Jhemi22 in Education
• 8051 microcontrollers by Chih-Hsiang Tang in Technology
• Embedded systems, 8051 microcontroller by Amandeep Alag
• Embedded C programming based on 8051 microcontroller by Gaurav Verma
• Microcontroller 8051 features & application
• MICROCONTROLLER-8051 Features & Applications Dr. Y .Narasimha Murthy Ph.D., Sri Saibaba National
College
• 8086 ASSEMBLY LANGUAGE PROGRAMMING Cutajar & Cutajar
• Intel microprocessor history by Ramzi_Alqrainy
628
 Website References
http://amcmp.blogspot.in/2012/06/8051-micro-controller.html
http://www.mikroe.com/chapters/view/65/chapter-2-8051-microcontroller-architecture/
https://www.pantechsolutions.net/project-kits/user-guide-for-lcd-interface-card                   LCD DIsplay

http://www.slideshare.net/pantechsolutions/interfacing-stepper-motor-with-8051                stepper motor

https://www.pantechsolutions.net/microcontroller-boards/adc-0809-interfacing-with-8086-ps2-lab-kit    ADC interface

https://www.pantechsolutions.net/microcontroller-boards/dac-0800-interfacing-with-8086-ps2-lab-kit     DAC interface

https://www.pantechsolutions.net/microcontroller-boards/led-interfacing-with-8086-ps2-lab-kit                    LED Interface

• www.vtulearning.com
• www.eazynotes.com
• www.slideshare.net
• www.scribd.com
• www.docstoc.com
• www.slideworld.com
• www.nptel.ac.in
• http://opencourses.emu.edu.tr/
• http://engineeringppt.blogspot.in/
• http://www.pptsearchengine.net/
• www.4shared.com
• http://8085projects.info/

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 NPTEL Lecture Materials References

• Microprocessors and Microcontrollers by Prof.

Krishna Kumar IISc Bangalore
link: http://nptel.ac.in/courses/106108100/

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