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Latches and Flipflops: Presented By: Pankaj Pratim Hazarika Etc 5 Semester

1) Sequential circuits are logic circuits that have both input variables and memory, in the form of flip-flops. 2) Flip-flops are basic memory cells that have two stable states (0 and 1) and are commonly used to store and transfer digital data in registers. 3) Common types of flip-flops include the S-R latch, S-R flip-flop, J-K flip-flop, and D flip-flop, each with different triggering mechanisms to change states.

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97 views11 pages

Latches and Flipflops: Presented By: Pankaj Pratim Hazarika Etc 5 Semester

1) Sequential circuits are logic circuits that have both input variables and memory, in the form of flip-flops. 2) Flip-flops are basic memory cells that have two stable states (0 and 1) and are commonly used to store and transfer digital data in registers. 3) Common types of flip-flops include the S-R latch, S-R flip-flop, J-K flip-flop, and D flip-flop, each with different triggering mechanisms to change states.

Uploaded by

Pankaj Pratim Hazarika
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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LATCHES AND FLIPFLOPS

Presented by:
PANKAJ PRATIM HAZARIKA
ETC 5TH SEMESTER
CONTENT
• Sequential circuit
• Flip-flop definition
• S-R Latch
• S-R Flip-flop
• J-K Flip-flop
• D Flip-flop
SEQUENTIAL CIRCUITS

 DEFINATION:
A Sequential Circuit is a combinational logic circuit that consists of input variable(X), logic
gates(combinational circuits) and the output variable(Z).
FLIP-FLOP( A one bit memory cell )

 The basic memory circuit is known as FLIP-FLOP. It has two stable states (0 and
1)
 It can be obtained by using NAND or NOR gates.
 Flip-flops are heavily used for Digital data storage and transfer and are commonly
used in banks called “registers”
SR Latch
S R Q(n+1)
 0 0 Invalid
SR latch is a circuit with two
cross-coupled NAND gates 0 1 1
 It consists of two inputs named S 1 0 0
for Set and R for Reset. 1 1 Hold
 It has two useful states, when
output Q=1 and Q´=0 and latch is
said to be in Set State. When Q=0
and Q´=1, it is in Reset State.
Working of SR latch
Nand gate logic
A B Output
0 0 1
0 1 1
1 0 1
1 1 0

S R Q(n+1)
0 0 Invalid
0 1 1
1 0 0
1 1 Hold
S-R Flip-flop

 SR flip-flop is a gated set-reset flip-


flop. The S and R inputs control the
state of the flip-flop when the clock
pulse goes from LOW to HIGH. The
flip-flop will not change until the clock
pulse is on a rising edge.
Working of S-R Flip-flop
Clock S R Q(n+1)
Not × × Qn
trigg
Trigg 0 0 Hold
” 0 1 0-Reset
” 1 0 1-Set
” 1 1 Invalid

S R Q(n+1)
0 0 Invalid
0 1 1
1 0 0
1 1 Hold
J-K Flip-flop
A J-K flip-flop is nothing more
than an S-R flip-flop with an
added layer of feedback. This
feedback selectively enables
one of the two set/reset inputs
so that they cannot both carry
an active signal to the
multivibrator circuit, thus
eliminating the invalid condition.
Working of JK flipflop

J K Qn+1
0 0 Hold
0 1 0
1 0 1
1 1 Toggle

Toggle condition:
Case 1, Q=1, Qn+1=0
Case 2, Q=0, Qn+1=1
D Flip-flop
A D (or Delay) Flip Flop is a
digital electronic circuit used to
delay the change of state of its
output signal (Q) until the next
rising edge of a clock timing
input signal occurs.

D Q Qn+1
0 0 0
0 1 0
1 0 1
1 1 1

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