Combinational Circuits

Logical Circuits
Combinational circuit
 Consists of logical gates whose outputs at any time are
determined from only the present combination of inputs

Sequential circuit
 Employ storage elements in addition to logic gates. Their
outputs are a function of the inputs and the state of the
storage elements (a function of previous inputs).
Combinational Circuits (Cont.)
A combinational circuit also can be described by m
Boolean functions, one for each output variable. Each
output function is expressed in terms of the n input
variables.
Analysis Procedure
The analysis of a combinational circuit requires that
we determine the function that the circuit
implements.
First step, make sure that the circuit is combinational
and not sequential
No feedbacks, or memory elements
Obtain the Boolean functions or the Truth table
Analysis Procedure
Example
3 binary inputs: A, B, C
2 binary outputs: F1, F2
Analysis Procedure
Get

Then

then
Analysis Procedure
Procedure for obtaining the truth table directly from
the logic diagram without going through the
derivations of the Boolean functions.
Design Procedure
Design Procedure
Design Procedure
Code Conversion Example
Input BCD
Output Excess-3 Code
Design Procedure
K-Maps
Design Procedure
Logic Gates
Design

Procedure
Logic Diagram
Binary Adder-Subtractor
Sum (S), Carry (C)
Half adder
A combinational circuit that performs the addition of
two bits.
Full adder
A combinational circuit that performs the addition of
three bits (two significant bits and a previous carry).
In this chapter, the half adder design is carried out
first, from which we develop the full adder.
Connecting n full adder in cascade produces a binary
adder for two n-bit numbers.
Half Adder
Full Adder
S could be also implemented with two half adders and
one OR gate
Binary Adder

0
Binary Adder (Cont.)
If the four-bit binary adder is designed by the
classical method.
9 inputs (4As + 4Bs + C0)
Truth table needs 29 = 512 entries
However, using the iterative method of cascading a
standard function, it is possible to obtain a simple and
straightforward implementation
Carry Propagation
The longest propagation delay time in an adder is the
time it takes the carry to propagate through the full
adders.
If there are four full adders in the adder, the output
carry C4 would have 2×4=8 gate levels from C0 to C4.
For an n-bit adder, there are 2n gate levels for the
carry to propagate from input to output.
The carry propagation time is an important attribute
of the adder because it limits the speed with which
two numbers are added.
Carry Propagation (Cont.)
Since all other arithmetic operations are implemented
by successive additions, the time consumed during
the addition process is critical.
An obvious solution for reducing the carry
propagation delay time is to employ faster gates with
reduced delays.
However, physical circuits have a limit to their
capability.
Another solution is to increase the complexity of the
equipment in such a way that the carry delay time is
reduced.
The most widely used technique employs the principle
of carry lookahead logic.
Carry Lookahead Logic
Pi and Gi
 Let

 The output sum and carry can be expressed as

 Gi is called a carry generate, and it produces a carry of 1 when

both Ai and Bi are 1, regardless Ci
 Pi is called a carry propagate, because it determines whether
a carry into stage i will propagate into stage i+1.
C3 does not have to wait for
C2 and C1 to propagate,
C3 is propagated at the same
time as C1 and C2
This gain in speed of operation
is achieved at the expense of
additional hardware
complexity.
4-bit adder
with carry lookahead

Output S1 through S3 have

equal propagation delay
times.
Binary Subtractor
A-B can be done by taking the 2’s complement of B
and adding it to A.
The 2’s complement can be obtained by taking the 1’s
complement and adding 1 to the least significant pair
of bits.
The 1’s complement can be implemented with
inverters, and a 1 can be added to the sum through the
input carry.
The circuit for subtracting A-B consists of an adder
with inverters placed between each data input B and
the corresponding input of the full adder. The input
carry C0 must be equal to 1 when subtraction is
performed.
Binary Subtractor (Cont.)
The addition and subtraction operations can be
combined into one circuit with one common binary
adder by including an exclusive-OR gate with each
full adder.
The mode input M controls the operation. When M=0,
the circuit is an adder, and when M=1, the circuit
becomes a subtractor.
Overflow
When two numbers with n digits each are added and
the sum is a number occupying n+1 digits, we say that
an overflow occurred.
Detection of overflow
depend on whether the numbers are signed or unsigned
 When two unsigned numbers are added,
overflow is detected from the end carry out of the most
significant position
 When two signed numbers are added,

the leftmost bit represents the sign and negative numbers are
in the 2’s complement form, the carry does not indicate an
overflow
Overflow (Cont.)
 Overflow may occur if the two numbers added are both positive or
both negative
 Cannot occur if one number is positive and the other is negative

example, two 8 bits signed numbers (+127 ~ -128)

 Overflow condition can be detected by observing

 The carry into the sign bit position and
 The carry out of the sign bit position

if the two carries are not equal, an overflow has occurred

Overflow Detection
Decimal Adder
Computers or calculators that perform arithmetic operations
directly in the decimal number system represent decimal
numbers in binary coded form.
An adder for such a computer must employ arithmetic circuits
that accept coded decimal numbers and present results in the
same code.
A decimal adder requires a minimum of 9 inputs and 5 outputs.
Since each input digit does not exceed 9, the output sum cannot
be greater than 9+9+1=19.
Suppose we apply two BCD digits to a four-bit binary adder.
The adder will form the sum in binary and produce a result that
ranges from 0 to 19.
Decimal

Adder (Cont.)
When the binary sum is greater than 1001, the addition of binary 0110
to the binary sum converts it to the correct BCD representation and
also produces an output carry as required.
It is obvious that a correction is needed when K=1.
The other six combinations from 1010 through 1111 that
need a correction have a 1 in position Z8.
To distinguish them from binary 1000 and 1001, which
also have a 1 in position Z8, we specify further that
either Z4 or Z2 must have a 1.
Binary Multiplier
Two 2-bit multiplier
More bits multiplier in
a similar fashion
J multiplier bits
K multiplicand bits
needs J x K AND gates
J – 1 K-bit adders
to produce a product
of J + K bits
 Magnitude Comparator
 Compares two numbers and determines their relative magnitudes
 3 binary variables to indicate A>B, A=B or A<B
 The circuit for comparing two n-bit numbers has 22n entries in the
truth table and becomes too cumbersome.
 However, it possesses a certain amount of regularity and can
designed by means of an algorithm.

 Exclusive-NOR

 The unequal outputs can use the same gates that are needed to
generate the equal output.
Four-bit magnitude comparator
Decoder
Convert n inputs to a maximum of 2n unique output
n-to-m-line decoder, m ≦ 2n
 3-to-8 decoder
seven output 0, one output 1
Decoders constructed with NAND gates
Include enable inputs to control the circuit operation
Example, one output 0, other output 1
 Demultiplexer
A decoder with enable input can function as a
demultiplexer
Demultiplexer receives a signal from a line and directs
it to one of 2n possible output lines
the selection of a specific output is controlled by the bit
combination of n selection lines
 1-to-4-line demultiplexer
E is the data input line
A, B are the selection input lines
e.g., AB=10, output D2 is the same as the E
A decoder with an enable input is referred to as a
decoder-demultiplexer
Decoders with enable inputs can be connected to form
a larger decoder
e.g., two 3-to-8-line decoders → 4-to-16-line decoder
In general, enable inputs are a convenient feature for
interconnecting two or more standard components for
the purpose of combining them into a similar function
with more inputs and outputs.
 Combinational Logic Implementation
Decoder provides the 2n minterms of n inputs variables
Any Boolean function can be expressed in sum of
minterms
Any combinational circuit with n inputs and m outputs
can be implemented with an n-to-2n-line decoder and
m OR gates
A function with a long list of minterms requires an OR
gate with a large number of inputs.
A function having a list of k minterms can be expressed
in its complemented form F’ with 2n-k minterms.
If the number of minterms in the function is greater
than 2n/2, then F’ can be expressed with fewer
minterms.
In such a case, it is advantageous to use a NOR gate to
sum the minterms of F’. The output of the NOR gate
complements this sum and generates the normal
output F.
If NAND gates are used for the decoder, as in Figure
4.19, then the external gates must be NAND gates
instead of OR gates. This is because a two-level NAND
gate circuit implements a sum-of-minterms function
and is equivalent to a two-level AND-OR circuit.
Full Adder
 Encoder
 Inverse operation of a decoder
 2n (or fewer) inputs and n outputs
 Example, octal-to-binary encoder (only one input is 1)
 Has the limitation that only one input can be active at any
given time. If two inputs are active simultaneously, the
output produces an undefined combination.
 To resolve this ambiguity, encoder circuits must establish an input
priority to ensure that only one input is encoded.
 Another ambiguity in the octal-to-binary encoder is that an
output with all 0’s is generated when all the inputs are 0; but
this output is the same as when D0 is equal to 1.
 This discrepancy can be resolved by providing one more output to
indicate whether at least one input is equal to 1.
 Priority Encoder
V, valid input
The higher the subscript number, the higher the
priority of the input
Multiplexers
Select binary data from one of many inputs and directs
it to a single output
Selection of a particular input is controlled by a set of
selection lines. Normally, there are 2n input lines and n
selection lines.
Example, 2-to-1-line multiplexer
4-to-1-line multiplexer
Quadruple 2-to-1-line Multiplexer
Provide multiple-bit selection logic
Boolean Function Implementation
A multiplexer is essentially a decoder that includes the
OR gate within the unit.
Using a multiplexer with n-1 selection inputs to
implement a boolean function of n variables.
The first n-1 variables of the function are connected to
the selection inputs of the multiplexer and the
remaining single variable of the function is used for the
data inputs.
Example

Use x, y to be selection inputs, z, z’, 0, 1 to be data inputs

Example,