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    Floorplan Summary:: Checks Before Floorplan: Floorplan Steps: Constraints: Floorplan Check List

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    Sai Kumar
    The document discusses floorplanning, placement, and clock tree synthesis (CTS) summaries. Some key steps for each are: Floorplanning includes defining block sizes and shapes, voltage creation, IO placement, adding placement blockages, and adding physical cells. Placement includes coarse placement, legalization, detailed placement, and scan chain reordering. CTS involves routing clock networks to minimize skew based on inputs like the netlist and timing constraints. Checks are done throughout to ensure legalization, timing requirements, congestion controls and other metrics are met.

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    Floorplan Summary:: Checks Before Floorplan: Floorplan Steps: Constraints: Floorplan Check List

    Uploaded by

    Sai Kumar
    2K views5 pages
    The document discusses floorplanning, placement, and clock tree synthesis (CTS) summaries. Some key steps for each are: Floorplanning includes defining block sizes and shapes, voltage creation, IO placement, adding placement blockages, and adding physical cells. Placement includes coarse placement, legalization, detailed placement, and scan chain reordering. CTS involves routing clock networks to minimize skew based on inputs like the netlist and timing constraints. Checks are done throughout to ensure legalization, timing requirements, congestion controls and other metrics are met.

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    The document discusses floorplanning, placement, and clock tree synthesis (CTS) summaries. Some key steps for each are: Floorplanning includes defining block sizes and shapes, voltage creation, IO placement, adding placement blockages, and adding physical cells. Placement includes coarse placement, legalization, detailed placement, and scan chain reordering. CTS involves routing clock networks to minimize skew based on inputs like the netlist and timing constraints. Checks are done throughout to ensure legalization, timing requirements, congestion controls and other metrics are met.

    Copyright:

    © All Rights Reserved
    Download as PPTX, PDF, TXT or read online from Scribd
    Download as pptx, pdf, or txt
    2K views5 pages

    Floorplan Summary:: Checks Before Floorplan: Floorplan Steps: Constraints: Floorplan Check List

    Uploaded by

    Sai Kumar
    The document discusses floorplanning, placement, and clock tree synthesis (CTS) summaries. Some key steps for each are: Floorplanning includes defining block sizes and shapes, voltage creation, IO placement, adding placement blockages, and adding physical cells. Placement includes coarse placement, legalization, detailed placement, and scan chain reordering. CTS involves routing clock networks to minimize skew based on inputs like the netlist and timing constraints. Checks are done throughout to ensure legalization, timing requirements, congestion controls and other metrics are met.

    Copyright:

    © All Rights Reserved
    Download as PPTX, PDF, TXT or read online from Scribd
    Download as pptx, pdf, or txt
    of 5

    Floorplan Summary:

    Checks Before Floorplan:


    Netlist Checks: (floating pins and nets , multi-driven nets , combinational loops ,unconstrained pins, mismatch
    pin-count  between instances and references.
    Floorplan Steps:
    Define Size and shape of block -> Voltage Creation ->IO placement ->Add placement blockage -> Adding Power
    switch -> Add Physical cells -> placing and qualifying pushdown cells ->creating bounds and regions
    Constraints : 
    Project.tcl (QRC Tech File, Core files ,Setup_lib.tcl , Setup analysis view ,Setup mmmc.tcl )
    User_setting.tcl ( Tap cell , physical setting ,set max transition , Voltage area setting ,Placement blockage setting)
    Floorplan Check list:
    Lib_checks, FT_clock_check, Even Site roe ,First row MX, Sram Spacing ,Sram Finfetgrid , Hard blockage
    spacing ,Tcic drc , Violation of endcap , MAPS error.
    PLACEMENT SUMMARY
    Placement Inputs: (netlist, logical and physical library ,Floorplan def, Design constraints, Timing
    constraints , Scan def ,Technology file )
    Placement Flow: 
    Coarse Placement: Rough placement where tool place randomly all the cells in the design , the overlaps and
    illeagal positions are ignored.
    Legalization: The tool assigns legal location to all the cells and eliminates all the overlaps.
    Detailed Placement: Iterative incremental optimization 
    Scan-Chain Reordering : Inserting DFT scan-chain reordering  to improve  congestion and Timing.
    HFNS: High Fanouts are buffered automatically by the tool 
    Tie cell addition: To avoid gate-oxide damage , the tie cells connects Std cells directly to Power and Ground.
    Placement Targets:
    Congestion-Driven Placement 
    Timing-Driven Placement
    Power-Driven Placement
    PLACEMENT SUMMARY 
    Placement Blockages: (hard ,soft and partial)
    Fixes after Placement:
    Legality Issue : Performs Refine Placement to check all the logics are legally placed and no overlaps. 
    DRV FIx: Fixing max-transition along data path
    Cell Delay : Depends on input transition and output load .
    Checks after Placement:
    Check Legalization
    Check pg connections for all the cells
    Check congestion ,Density screens and pin density over maps to make sure they are under control.
    Check Min/max- Tran/cap violations
    Check whether all Don't-touch cells/nets are preserved.
    Check the total utilization of the design
    CTS SUMMARY
    Inputs of CTS :
    Technology file (.tf) ,Netlist, SDC ,Library files (.lib & .lef) ,TLU+ file ,Placement DEF file 
    Clock specification file which contains Insertion delay, skew, clock transition, clock cells, NDR, CTS tree type, CTS
    exceptions, list of buffers/inverters etc...
    Checks need to be done before CTS Check :
    • Legality Check 
    • Timing QOR (Setup should be under control) 
    • Timing DRVs 
    • High Fanout nets (like scan enable/any static signal) 
    • Congestion (running CTS on congestion design / design with congestion hotspot can create more congestion and
    other issues (Noise/IR) ) 
    Types of clock tree structures (to minimize the skew). 
    1. H-Tree
    2. X-Tree
    3. Method of Mean and Median
    4. Geometric Matching Algorithms
    5. Pi Configuration
    6. RC-Tree
    CTS SUMMARY
    CTS Routing Rules ​
    • Shielding ​(Techniques in order to avoid crosstalk.We can prevent crosstalk by shielding clock nets with ground wires)
    • Non Default Rules (NDR):The user-defined Routing rules apart from the default Routing Rule
    • NDRs make the Clock Routes less sensitive to CrossTalk or EM effects
    • Double/ Triple Width for avoiding Electromigration
    • Double/ Triple Spacing for avoiding Crosstalk
    • NDRs will improve Insertion Delay
    • Clock Source (The pin that a clock fans out from. (e.g., PLL))
    • Clock Sink (All pins that receive the clock signal (FF, latch))
    • Clock Tree (The root of a circuit graph for buffering)
    • Skew Group (A subset of clock sinks to consider for skew balancing/analysis. By default, all the sinks of a clock tree are in the same
    skew group)
    • Stop Pins (A leaf pin of a clock tree.)
    • Ignore Pins 
    • Ignore pins are pins on the clock net that will not be considered a sink in any skew group.
    • The clock net will be buffered up to the ignore pin but not beyond it.
    • Exclude Pins 
    • Exclude pins are similar to ignore pins, but the clock net will not be buffered up to an exclude pin.
    • Through Pins 
    • Through pins are pins, which would otherwise be considered stop pins, but we want the clock to propagate through them (for buffering
    and adding pins to the skew group).

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