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DIGITAL LOGIC DESIGN

( CE_118 )

CHAPTER 2:
Storage Components
(part_1)
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Storage components
 Storage components store data and perform some
simple operations.
 Storage components include:
o registers
o counters
o register files
o queues
o stacks
 Combinatorial and storage components are used for
construction of:
o datapaths
o controllers
 Main subsystems of modern processors and other
microchips.
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Registers
 Registers are bit wise extensions of flip-flops.
 Registers store one data word.

Qi= Ii when Clk=

Graphic symbol

Register schematic
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Registers with asynchronous set and reset

 Asynchronous setting and resetting is independent of clock
signal.
 Asynchronous inputs are used to initialize the register.

Graphic symbol

Register schematic

Operation table
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Register with parallel load

 Parallel load register can hold data indefinitely.
 It can also load new data when load signal is 1.

Graphic symbol Operation table

Register
schematic
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Serial-in, parallel-out Shift register (shift-right)

 Serial-in, parallel-out register converts serial data stream
into parallel data stream.

Graphic symbol Operation table

Mux 2-to-1

Register
schematic
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Shift register with parallel load (SRwPL)

Graphic symbol Operation table

Mux 4-to-1

D0=S1’S0’Q0+ S1’S0I0
+S1S0’IR +S1S0 Q1

Di=S1’S0’Qi+ S1’S0 Ii
+S1S0’Qi-1 +S1S0Qi+1
(1 ≤ i ≤ 2)

D3=S1’S0’Q3+ S1’S0I3
+S1S0’Q2 +S1S0 IL
Register schematic
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4-bit binary counter

 Counters increment (decrement) their content when enabled

Operation table HA truth table

Graphic symbol

Up- or
Down-counter???

Di = Qi⊕Ci
Ci+1 = QiCi
counter schematic
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4-bit up/down binary counter

Graphic symbol Operation table

HAS truth table

Logic schematic
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4-bit up/down binary counter with parallel load

This counter is sometimes called presettable counter

Graphic symbol

Operation table

Logic schematic
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BCD counters
Up sequence: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0, ......
Down sequence: 0, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0, 9, ......

BCD up-counter
BCD up/down-counter

Up counter loads 0 when counter content is 9 (1001)

Up/down counter loads 0 when counter content is 9 (1001) and direction bit D=0
Up/down counter loads 9 when counter content is 0 (0000) and direction bit D=1
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Asynchronous counters
 Each FF in synchronous counters changes its output at
the same time.

 FFs’ output in asynchronous counters change values

at different times.

 Advantage of asynchronous counters is simple and low

cost (less gates).

 Weakness of asynchronous counters is longer delays in

comparison with synchronous counters.
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4-bit asynchronous up counter

Graphic symbol

Logic schematic
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4-bit asynchronous up counter

Timing diagram
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Propagation Delay in Ripple Counters

 Ripple counters are simple—requiring the fewest
components to produce a given operation
o Cumulative propagation delay can cause problems
at high frequencies

 The counter will perform accurately when the period of clock

cycle must be longer than the total propagation delay of it.
o For proper operation: Tclock  N x tpd
Tclock: the period of clock cycle
N: the number of FFs
Tpd: the proparation delay of a FF ( )

o Maximum frequency: Fmax = 1 / (N x tpd)

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Propagation Delay in Ripple Counters

The CBA = 100

does not occur
• T=1000ns • T=100ns
• tpd=50ns • tpd=50ns

 T  3 x tpd  T < 3 x tpd

Counter operates properly Counter operates wrongly
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8-bit mixed-mode up counter

 Mixed-mode counter consists of:
o (1) asynchronous counters connected synchronous slices.

Asynchronous counter with 4-bit synchronous slices

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8-bit mixed-mode up counter (cont.)

Mixed-mode counter consists of:
o (2) synchronous counters connected asynchronously.

Synchronous counter with 4-bit asynchronous slices

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Register-file
 Register-file is used as fast temporary storage

Graphic symbol

Register-file cell

Logic schematic
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Register-file with 1 write port and 2 read ports

This register-file is used for reading two operands and
writing one result in each clock cycle.

Graphic symbol

Register-file cell

Logic schematic
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Random Access Memory (RAM)

Memory address
and content

CS: Chip Select

RWS: Read/Write Select

0: Read, 1: Write

Graphic symbol Graphic symbol

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RAM organization
Ram memory cells can be static or dynamic.
Static RAM’s do not lose data with time.
Dynamic RAM’s must be refreshed.

Memory cell

Memory schematic
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RAM timing

Read-cycle timing

Write-cycle timing
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16K x 32 RAM design with 16K x 8 RAMs

(to obtain wider bit widths)
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64K x 8 RAM design with 16K x 8 RAMs

(to obtain a larger memory)
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Push-down stack principle

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4-Word push-down stack

Operation table
Control table Output table

Push=Shift right
Pop=Shift left

Sửa trong sách

chỗ tin hiệu Set
của Counter

Stack schematic SRwPL: Shift Register with Parallel Load

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Push-down stack implemented with a 1K RAM

Symbolic design

Operation table

Push: Data  RAM (TOP); Increment Top, Top-1

Pop: RAM (Top-1)  Data; Decrement Top, Top-1
Stack is full when Top=1023
Stack is empty when Top=0
Control table
Location with address 1023 is never loaded
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FIFO queue principles

Queue content Queue content

before 45 is after 45 is stored
stored Queue content
after 23 is read
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4-word FIFO queue

Operation table Control table

Queue schematic
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FIFO queue implemented with a 1K RAM

Control table

Symbolic design

Operation table

Schematic
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Bài tập – Thanh ghi

 Cho giản đồ xung sau, vẽ giản đồ xung output của FF - D
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Bài tập – Thanh ghi & Thanh Ghi dịch

Thiết kế 1 thanh ghi 4 bit có 2 tín hiệu nạp dùng để điều
khiển việc nạp dữ liệu từ 2 nguồn khác nhau
Thiết kế thanh ghi 16 bit có khả năng làm 2 chức năng
sau:
o Nạp dữ liệu mới
o Hoán đổi byte trọng số thấp và byte trong số cao (8 bit thấp lên 8
bit cao).
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Bài tập – Bộ Đếm

Thiết kế mạch đếm nhị phân chỉ đếm lên:
o Số chẵn: 0, 2, 4, 6, 8, 0, ….
o Số lẻ: 1, 3, 5, 7, 1, …
Thiết kế các cổng luận lý sao cho mạch đếm đếm đến
các giá trị sau:
o7
o 14
o 15
Thiết kế mạch đếm chỉ đếm các số sau: 1, 5, 9, 11, 13,
15, 1, ….
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Bài tập –Bộ Đếm

Thiết kế mạch đếm 0 – 9 bất đồng bộ 4 bit sử dụng:
o FF J-K.
Thiết kế mạch đếm 0 – 99 bất đồng bộ.
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Bài tập – Thiết kế bộ nhớ

Thiết kế bộ nhớ:
o 256K × 8 RAM sử dụng thanh RAM 256K × 1 RAM
o 256K × 8 RAM sử dụng thanh RAM 64K × 8 RAM