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Name: P. Revathi
Department: ECE
Designation: Asst. Professor
Title: Behavioural Level Modelling

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 Behavioural Level Modelling
Operations and Assignments, Functional Bifurcation, Procedural constructs: Initial, Always, Assignments with
delays, Wait, Multiple always blocks Designs at Behavioural level, Blocking and Non-blocking assignments, Case
statement, Simulation flow, Conditional statements, and loops- if, if-else, repeat, for, while, forever, parallel
blocks, force-release, Event, System Tasks, and Functions, File based tasks and Functions, Compiler directives,
User-Defined Functions, Tasks and Primitives-Introduction, Function, Tasks, User- Defined Primitives (UDP)
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Continuous assignment structures, Delays, and Continuous assignments, Assignment to Vectors, Operators,
Practical Components
1. Perform Behavioural model for multiplexer and demultiplexer
2. Perform Behavioural model for 8 to 3 priority encoders
3. Perform Behavioural model for 4-bit counter and shift register
4. Perform the simulation of parity bit generation using functions and tasks
5. Performa two-bit binary addition using functions and tasks
6. Perform the simulation of half adder and display the stimulus, response of system tasks-$monitor,$display,
$monitoron, $monitorof, $stop, $finish

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 BEHAVIORAL MODELING

• Design descriptions at data flow level and gate level are close to the circuit
• An increase in gate count may still be accommodated, if it is due to an increase in vector size one has to work
at a different dimension – the circuit can have a million gates.
• The increase in vector size may still be accommodated at the data flow level (e.g., 32- or 64-bit systems), since
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it calls only for scaling of a smaller design.

• But increase in terms of functional complexity makes the approach almost intractable for many designs.
• Behavioral level modeling constitutes design description at an abstract level.
• One can visualize the circuit in terms of its key modular functions and their behavior
• The description is carried out essentially with constructs similar to those in “C” language
• The design itself is similar to programming in “C”. The constructs available in behavioral modeling aim at the
system level description.
• Here direct description of the design is not a primary consideration in the Verilog standard

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 OPERATIONS AND ASSIGNMENTS
• OPERATIONS AND ASSIGNMENTS:

• The design description at the behavioral level is done through a sequence of assignments.
• These are called ‘procedural assignments’
• The procedure assignment is characterized by the following:
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1. The assignment is done through the “=” symbol (or the “<=” symbol) as was the case with the continuous
assignment earlier.
2. An operation is carried out and the result assigned through the “=” operator to an operand specified on the left
side of the “=” sign – for example, N = ~N;
• Here the content of reg N is complemented and assigned to the reg N itself.
• The assignment is essentially an updating activity.
3. The operation on the right can involve operands and operators. The operands can be of different types – logical
variables, numbers – real or integer and so on.

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 OPERATIONS AND ASSIGNMENTS

• The operands on the right side can be of the net or variable type. They can be scalars or vectors.
• It is necessary to maintain consistency of the operands in the operation expression – e.g., N = m / l;
• Here m and l have to be same types of quantities – specifically a reg, integer, time, real, real time, or
memory type of data – declared in advance.
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• The operand to the left of the “=” operator has to be of the variable (e.g., reg) type. It has to be specifically
declared accordingly. It can be a scalar, a vector, a part vector, or a concatenated vector.
• Procedural assignments are very much like sequential statements in C.
• Normally they are carried out one at a time sequentially. As soon as a specified operation on the right is carried
out, the result is assigned to the quantity on the left –
• for example
• N = m + l;
• N1 = N * N;
• The above form a set of two procedures placed within an always block

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 FUNCTIONAL BIFURCATION

• Design description at the behavioral level is done in terms of procedures of two types;

• one involves functional description and interlinks of functional units. It is carried out through a series of

blocks under an “always” banner

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• The second concerns simulation – its starting point, steering the simulation flow, observing the process

variables, and stopping of the simulation process;

• All these can be carried out under the “always” banner, an “initial” banner, or their combinations.

• However, each always and each initial block initiates an activity flow during simulation

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 Structure of a typical procedural block
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 begin – end Construct
• If a procedural block has only one assignment to be carried out, it
can be specified as below:
• initial #2 a=0;
• The above statement assigns the value 0 to variable a at the
simulation time of 2 ns.
• It is possibly the simplest initial block. More often more than one
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procedural assignment is to be carried out in an initial block.

• All such assignments are grouped together between “begin” and
“end” declarations.
• Functionally, the construct is similar to the begin–end construct
in Pascal or the { } construct in C language.
The following are to be noted here
1. Every begin declaration must have its associated end
declaration. Nesting of begin-end blocks
2. begin – end constructs can be nested as many times as desired.
3. For clarity in description and to avoid mistakes, nested begin –
end blocks are separated suitably

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 Name of the Block
• Any block can be assigned a name, but it is not mandatory.
• Only the blocks which are to be identified and referred by the simulator need be named.
• The names assigned to different blocks have to be different.
• Names chosen should conform to the rules for the selection of names to variables
• Assigning names to blocks serves different purposes:
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• Registers declared within a block are local to it and are not available outside.
• However, during simulation they can be accessed for simulation, etc., by proper dereferencing
• Named blocks can be disabled selectively when desired

Local Variables
• Variables used exclusively within a block can be declared within it.
• Such a variable need not be declared outside, in the module encompassing the block.
• Such local declarations conserve memory and offer other benefits too.
• Regs declared and used within a block are static by nature.
• They retain their values at the time of leaving the block.
• The values are modified only at the next entry to the block.

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 INITIAL CONSTRUCT

• A set of procedural assignments within an initial construct are executed only once – and, that too, at the times
specified for the respective assignments.
• The initial process characterized by the following:
• In any assignment statement the left-hand side has to be a storage type of element (and not a net). It can be a
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reg, integer, or real type of variable. The right-hand side can be a storage type of variable (reg, integer, or
real type of variable) or a net.
• for continuous assignment can be used for procedural assignments as well. The context decides whether the
assignment is of a continuous type or procedural type.
• In the latter case it is present within an always or an initial construct.
• All the procedural assignments appear within a begin–end block explained earlier.
• All the procedural assignments are executed sequentially – in the same order as they appear in the design
description. The waveforms of a and b conforming to the assignments
• Initially (at time t = 0 ns), a and b are set equal to zero.

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 INITIAL CONSTRUCT
module nil;
reg a, b;
initial
begin
a = 1'b0;
b = 1'b0;
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$display ("display: a = %b, b = %b", a, b);

#2 a = 1'b1;
A typical initial block #3 b = 1'b1;
#1 a = 1'b0;
#100 $stop;
end
initial
$monitor("monitor: a = %b, b = %b", a, b);
output endmodule
# display : a = 0 ,b = 0 A typical module with an initial block
# monitor : a = 0 ,b = 0
# monitor : a = 1 ,b = 0
# monitor : a = 1 ,b = 1
# monitor : a = 0 ,b = 1
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 INITIAL CONSTRUCT
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Multiple Initial Blocks

A module can have as many initial blocks as desired.
All of them are activated at the start of simulation.
The time delays specified in one initial block are exclusive of those in any other block

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 Module with multiple initial blocks

module nil1;
initial
reg a, b;
begin
a = 1'b0;
b = 1'b0; output
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$display ($time,"display: a = %b, b = %b", a, b); # display : a = 0 , b = 0

#2 a = 1'b1; # monitor : a = 0 , b = 0
#3 b = 1'b1; # monitor : a = 0 , b = 1
#1 a = 1'b0; # monitor : a = 1 , b = 1
end # monitor : a = 1 , b = 0
initial #100$stop; # monitor : a = 1 , b = 1
initial $monitor ($time, “monitor: a = %b, b = %b", a, # monitor : a = 0 , b = 1
b);
initial
begin
#2 b = 1'b1;
end
endmodule

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 ALWAYS CONSTRUCT

• The always process signifies activities to be executed on an “always basis.”

• Its essential characteristics are:
• Any behavioral level design description is done using an always block.
• The process has to be flagged off by an event or a change in a net or a reg. Otherwise it ends in a
stalemate.
• The process can have one assignment statement or multiple assignment statements.
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• In the latter case all the assignments are grouped together within a “begin – end” construct.
• Normally the statements are executed sequentially in the order they appear.
• Event Control
• The always block is executed repeatedly and endlessly. It is necessary to specify a condition or a
set of conditions, which will steer the system to the execution of the block.
• Alternately such a flagging-off can be done by specifying an event preceded by the symbol “@”.
• The event can be a change in the variable specified in either direction or a change in a specified
direction.
For example,
• @(negedge clk) : executes the following block at the negative edge of the reg (variable) clk.
• @(posedge clk) : executes the following block at the positive edge of the reg (variable) clk.
• @clk : executes the following block at both the edges of clk.

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 Event Control

• @(prt or clr) : the block is executed whenever either of the variables prt or clr undergoes a change.
• @(posedge clk1 or negedge clk2) : With the event, the block is executed in two cases – whenever
the clock clk1 changes from 0 to 1 state or the clock clk2 changes from 1 to 0. One can specify more
elaborate events by OR'ing individual ones.
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• The events can be changes in reg, integer, real or a signal on a net.

• No algebra or logic operation is permitted as an event.
• The OR'ing signifies “execute the block if any one of the events takes place.”
• The edge transition on each event is to be specified separately
• Difference between the following:
• (posedge clk1 or clk2): means “execute the block following if clk1 goes to 1 state or clk2 changes
state (whether 0 to 1 or 1 to 0).”
• (posedge clk1 or posedge clk2): means “execute the block following if clk1 goes to 1 state or clk2
goes to 1 state.”

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 Event Control

• The “posedge” transition for a signal on a net can be of three different types:

• 0 to1

• 0 to x or z
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• x or z to 1

• The “negedge” transition for a signal on a net can be of three different types:-

• 1 to 0

• 1 to x or z

• x or z to 0

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 up counter module

module counterup(a,clk,N); module tst_counterup;//TEST_BENCH

input clk; reg clk;
input[3:0]N; reg[3:0]N;
output[3:0]a; wire[3:0]a;
reg[3:0]a; counterup c1(a,clk,N);
initial a=4'b0000; initial
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always@(negedge clk) begin

a=(a==N)?4'b0000:a+1'b1; clk = 0;
endmodule N = 4'b1011;
end
always #2 clk=~clk;
initial $monitor($time,"a=%b,clk=%b,N=
%b",a,clk,N);
endmodule

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 BEHAVIORAL MODELING
Clocked Flip-Flop
module tst_dffbeh();//test-bench
module dff(do,di,clk); reg di,clk;
output do; wire do;
input di,clk; dff d1(do,di,clk);
reg do; initial
initial begin
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do=1'b0; clk=0;
always@(negedge clk) do=di; di=1'b0;
endmodule end
always #3clk=~clk;
always #5 di=~di;
initial
$monitor($time,"clk=%b,di=%b,do=%b",clk,di,do);
initial #35 $stop;
endmodule

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 Output
# 0clk=0,di=0,do=0
# 3clk=1,di=0,do=0
# 5clk=1,di=1,do=0
# 6clk=0,di=1,do=1
# 9clk=1,di=1,do=1
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# 10clk=1,di=0,do=1
# 12clk=0,di=0,do=0
# 15clk=1,di=1,do=0
# 18clk=0,di=1,do=1
# 20clk=0,di=0,do=1
# 21clk=1,di=0,do=1
# 24clk=0,di=0,do=0
# 25clk=0,di=1,do=0
# 27clk=1,di=1,do=0
# 30clk=0,di=0,do=0
# 33clk=1,di=0,do=0

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 ASSIGNMENTS WITH DELAYS

always #3 b = a;
module del1;
reg a,b;
always #3 b=a;
Initial
begin
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a = 1’b1;
b = 1’b0;
#1 a = 1’b0;
#3 a = 1’b1;
#1 a = 1’b0;
#2 a = 1’b1;
#3 a = 1’b0;
end
initial $monitor($time, " a = %d, b = %d", a, b);
initial #20 $finish;
endmodule

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 ASSIGNMENTS WITH DELAYS

module del2;
reg a,b;
always @(a) #2 b=a;
Initial
begin
a = 1’b1;
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b = 1’b0;
#1 a = 1’b0;
#3 a = 1’b1;
#1 a = 1’b0;
#2 a = 1’b1;
#3 a = 1’b0;
end
initial $monitor($time, " a = %d, b = %d", a, b);
initial #20 $finish;
endmodule

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 Intra-assignment Delays

A = # dl expression;
A module to illustrate delayed assignment

module del4;
Integer a, b;
always b = #2 a; Partial output with the simulation of the module
Initial
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begin
a = 0; b = 0;
#2 a =1;
#2 a =2;
#2 a =3;
#2 a =4;
#2 a = 5;
#2 a =6; #2
a =7;
#2 a =8;
end
initial $monitor($time, " a = %d, b = %d", a, b);
initial #20 $finish;
endmodule

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 ASSIGNMENTS WITH DELAYS

A module to illustrate combinations of delays

Module del_dem4;
Integer a,b,c,d,n; Output obtained with the simulation of the module
Always
begin
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#2 b = a;
c = #1 a;
d = a;
end
initial
begin
a = 0; b = 0; c = 0; d = 0;
#1 a = 1; #2 a = 2; #2 a = 3; #2 a = 4;
#2 a = 5; #2 a = 6; #2 a = 7; #2 a = 8; #2 a = 9;
#2 a = 10;
end
initial $monitor ($time, " a = %d, b = %d, c =
%d, d = %d", a, b, c, d);
endmodule

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 Delay Assignments

• In all the illustrations above, delay was specified as a number.

• It may be a variable or a constant expression.
• In case it is an expression, it is evaluated, and execution delayed by the number of time steps.
• If the number evaluates to a negative quantity, the same is interpreted as a 2’s complement value.
• In the statement
• always #b a = a + 1;
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• a and b are variables.

• The execution incrementing a is scheduled at b ns.
• If b changes, the execution time also changes accordingly.
• Another example consider the procedural assignment
• always #(b + c) a = a + 1;
• Here a, b, and c are variables. The algebraic addition of variables b and c is to be done.
• The scheduler schedules the incrementing of a and reassigning the incremented values back to a with a time
delay of (b + c) ns.
• As an additional example consider the assignment below with an intra-assignment delay.
• always #(a + b) a = #(b + c) a +1;
• Here the simulator evaluates (a + b) during simulation. After a lapse of (a + b) ns, execution of the statement
is taken up; (a + 1) is evaluated and assigned as the new value of a – but the assignment is delayed by (b + c)
ns

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 Zero Delay

• A delay of 0 ns does not really cause any delay.

• Often it is used to avoid indecision in the precedence of execution of assignments

• wait CONSTRUCT
• The wait construct makes the simulator wait for the specified expression to be true before proceeding with
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the following assignment or group of assignments.

• wait (alpha) assignment1;

• alpha can be a variable, the value on a net, or an expression involving them. If alpha is an expression, it is
evaluated; if true, assignment1 is carried out. One can also have a group of assignments within a block in
place of assignment1.
• The activity is level-sensitive in nature, in contrast to the edge-sensitive nature of event specified through @.
• Specifically, the procedural assignment @clk a = b; assigns the value of b to a when clk changes; if the value
of b changes when clk is steady, the value of a remains unaltered.

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 A counter module to illustrate the use of wait construct.

module ctr_wt(a,clk,N,En); //TEST_BENCH

input clk,En; module tst_ctr_wt;
input[3:0]N; reg clk,En;
output[3:0]a; reg[3:0]N;
reg[3:0]a; wire[3:0]a;
initial a=4'b1111; ctr_wt c1(a,clk,N,En);
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always initial
begin begin
wait(En) clk=0;N=4'b1111;En=1'b0;#5 En=1'b1;#20 En=1'b0;
@(negedge clk) end
a=(a==N)?4'b0000:a+1'b1; always
end #2 clk=~clk;
endmodule initial #35 $stop;
initial $monitor($time,"clk=%h,En=%b,N=%b,a=
%b",clk,En,N,a,);
endmodule

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 A counter module to illustrate the use of wait construct.

//output

# 0clk=0,En=0,N=1111,a=1111
# 2clk=1,En=0,N=1111,a=1111
# 4clk=0,En=0,N=1111,a=1111
# 5clk=0,En=1,N=1111,a=1111
# 6clk=1,En=1,N=1111,a=1111
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# 8clk=0,En=1,N=1111,a=0000
# 10clk=1,En=1,N=1111,a=0000
# 12clk=0,En=1,N=1111,a=0001
# 14clk=1,En=1,N=1111,a=0001
# 16clk=0,En=1,N=1111,a=0010
# 18clk=1,En=1,N=1111,a=0010
# 20clk=0,En=1,N=1111,a=0011
# 22clk=1,En=1,N=1111,a=0011
# 24clk=0,En=1,N=1111,a=0100
# 25clk=0,En=0,N=1111,a=0100
# 26clk=1,En=0,N=1111,a=0100
# 28clk=0,En=0,N=1111,a=0101
# 30clk=1,En=0,N=1111,a=0101
# 32clk=0,En=0,N=1111,a=0101
# 34clk=1,En=0,N=1111,a=0101

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 DESIGNS AT BEHAVIORAL LEVEL

A-O-I An A-O-I gate module at the behavioral level and its test bench

module tst_aoibeh;
reg [1:0]a,b; /* specicific values will be assigned to
module aoibeh(o,a,b); a1,a2,b1, and b2 and these connected
to input ports of the gate insatntiations;
output o; hence these variables are declared as reg */
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input[1:0]a,b; wire o;
reg o,a1,b1,o1; initial
always@(a[1] or a[0]or b[1]or b[0]) begin
a[0]=1'b0;a[1] =1'b0;b[0]=1'b0;b[1] =1'b0;
begin #3 a[0] =1'b1;
a1=&a; #3 a[1] =1'b1;
b1=&b; #3 b[0] =1'b1;
#3 b[1] =1'b0;
o1=a1||b1; #3 a[0] =1'b1;
o=~o1; #3 a[1] =1'b0;
end #3 b[0] =1'b0;
endmodule end
initial #100 $stop;//the simulation ends after running
for 100 tu's.
initial $monitor($time, "o =%b,a[0]=%b,a[1]=%b, b[0] =
%b ,b[1] = %b ",o,a[0],a[1],b[0],b[1]);
aoibeh gg(o,a,b);
endmodule

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 A-O-I

# 0 o = 1,a[0]=0,a[1]=0,b[0]=0,b[1]=0
# 3 o = 1,a[0]=1,a[1]=0,b[0]=0,b[1]=0
# 6 o = 0,a[0]=1,a[1]=1,b[0]=0,b[1]=0
# 9 o = 0,a[0]=1,a[1]=1,b[0]=1,b[1]=0
#18 o = 1,a[0]=1,a[1]=0,b[0]=1,b[1]=0
#21 o = 1,a[0]=1,a[1]=0,b[0]=0,b[1]=0
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Simulation results of the module

Synthesized circuit of the A-O-I module

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 BLOCKING AND NONBLOCKING ASSIGNMENTS

• All assignment within an initial or an always block considered so far are done through an equality (“=”)
operator.
• These are executed sequentially – that is, one statement is executed, and only then the following one is
executed.
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• Such assignments block the execution of the following lot of assignments at any time step.
• Hence they are called “blocking assignments
• where assignments are to be affected concurrently (as with the continuous assignments considered in the
preceding chapter). A facility called the “nonblocking assignment” is available for such situations.
• The symbol “<=” signifies a non-blocking assignment.
• The same symbol signifies the “less than or equal to” operator in the context of an operation
• The context decides the role of the symbol.
• The main characteristic of a nonblocking assignment is that its execution is concurrent with that of the
following assignment or activity

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 BLOCKING AND NONBLOCKING ASSIGNMENTS

A <= 2'b00; A <= 2'b00;

B <= 2'b01; #2 B <= 2'b01;
C <= 2'b11; #1 C <= 2'b11;
A group of A group of nonblocking
nonblocking assignments with time
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assignments. delays

A = 2'b00; A = 2'b00;
B = 2'b01; B = 2'b01;
A <= B; A = B;
B <= A; B = A;
Swapping variable values Another group of blocking
through nonblocking assignments
assignments

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 module involving blocking and nonblocking assignments

initial
begin
A= 1'b0;
B= 1'b1;
C = 1'b0;
end
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always @(posedge clk)

begin
A <= B;
@(negedge clk) C <= B &(~c);
#2 B< = C;
end

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 A time delay in an evaluation An intra-assignment delay
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A time delay in a nonblocking assignment. An intra-assignment delay in a nonblocking assignment

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 THE case STATEMENT

• The case statement is an elegant and simple construct for multiple branching in a module.
• The keywords case, endcase, and default are associated with the case construct
• A statement or a group of statements is executed if and only if there is an exact – bit by bit – match between
the evaluated expression and the specified
ref1, ref2, etc.
• For any of the matches, one can have a block of statements defined for execution. The block should appear
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within the begin-end construct.

• There can be only one default statement or default block. It can appear anywhere in the case statement.
• One can have multiple signal combination values specified for the same statement for execution. Commas
separate all of them.

Case (expression)
Ref1 : statement1;
Ref2 : statement2;
Ref3 : statement3;
.. .
...
default: statementd;
endcase
Structure of the case statement
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 2-to-4 decoder using the case statement

module dec2_4beh(o,i); //test bench

output[3:0]o; module tst_dec2_4beh();
input[1:0]i; wire [3:0]o; output
reg[3:0]o; reg[1:0] i;
# 0 output o = 0000 , input i = 00
always@(i) //reg en;
begin dec2_4beh dec(o,i); # 2 output o = 0001 , input i = 01
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case(i) initial # 4 output o = 0010 , input i = 10

2'b00:o=4'h0; begin # 6 output o = 0100 , input i = 11
2'b01:o=4'h1; i =2'b00; # error
2'b10:o=4'h2; #2i =2'b01; # 10 output o = 0000 , input i =
2'b11:o=4'h4; #2i =2'b10; 0x
default: #2i =2'b11;
begin #2i =2'b11;
$display ("error"); #2i =2'b0x;
o=4'h0; end
end initial $monitor ($time , " output o = %b ,
endcase input i
end = %b " , o ,i);
endmodule endmodule

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 ALU module

module alubeh(c,a,b,f); module tst_alubeh;//test-bench

output[3:0]c; reg[3:0]a,b;
input [3:0]a,b; reg[1:0]f;
input[1:0]f; wire[3:0]c;
reg[3:0]c; alubeh aa(c,a,b,f);
always@(a or b or f) initial
begin begin
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case(f) f=2'b00;a=2'b00;b=2'b00;
2'b00: c=a+b; end
2'b01: c=a-b; always
2'b10: c=a&b; begin
2'b11: c=a|b; #2 f=2'b00;a=4'b0011;b=4'b0000;
end case #2 f=2'b01;a=4'b0001;b=4'b0011;
end #2 f=2'b10;a=4'b1100;b=4'b1101;
endmodule #2 f=2'b11;a=4'b1100;b=4'b1101;
end
initial $monitor($time,"f=%b,a=%b,b=%b,c=%b",f,a,b,c);
initial #10 $stop;
endmodule

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 0f=00,a=0000,b=0000,c=0000
#2f=00,a=0011,b=0000,c=0011
#4f=01,a=0001,b=0011,c=1110
#6f=10,a=1100,b=1101,c=1100
#8f=11,a=1100,b=1101,c=1101
#10f=00,a=0011,b=0000,c=0011
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37
 Casex and Casez

• The case statement executes a multiway branching where every bit of the case expression contributes to the
branching decision.
• The statement has two variants
• where some of the bits of the case expression can be selectively treated as don’t cares – that is, ignored.
Casez allows z to be treated as a don’t care. “?” character also can be used in place of z.
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• casex treats x or z as a don’t care.

• An illustrative example using casez construct follows

38
 2-bit priority encoder using the casez statement;

module pri_enc(a,b); module pri_enc_tst;//test-bench 0input b = zzz0 ,a = 01

output[1:0]a; reg [3:0]b; 2input b = zzz1 ,a = 00
input[3:0]b; wire[1:0]a; 6input b = zz10 ,a = 01
reg[1:0]a; pri_enc pp(a,b); 8input b = z100 ,a = 10
always@(b) initial b=4'bzzz0; 10input b = 1000 ,a = 11
casez(b) always 12input b = zzz1 ,a = 00
4'bzzz1:a=2'b00; begin 16input b = zz10 ,a = 01
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4'bzz10:a=2'b01; #2 b=4'bzzz1; 18input b = z100 ,a = 10

4'bz100:a=2'b10; #2 b=4'bzzz1; 20input b = 1000 ,a = 11
4'b1000:a=2'b11; #2 b=4'bzz10; 22input b = zzz1 ,a = 00
endcase #2 b=4'bz100; 26input b = zz10 ,a = 01
endmodule #2 b=4'b1000; 28input b = z100 ,a = 10
end 30input b = 1000 ,a = 11
initial $monitor($time, "input b =%b,a =%b 32input b = zzz1 ,a = 00
",b,a); 36input b = zz10 ,a = 01
initial #40 $stop; 38input b = z100 ,a = 10
endmodule
.

39
 if AND if-else CONSTRUCTS

• The if construct checks a specific condition and decides execution based on the result. After execution of
assignment1, the condition specified is checked.
• If it is satisfied, assignment2 is executed; if not, it is skipped.
• In either case the execution continues through assignment3, assignment4, etc.
• Execution of assignment2 alone is dependent on the condition number of assignments associated with the
if condition is more than 1, the whole set of them can be grouped within a begin-end block
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...
assignment1;
if (condition)
assignment2; Flowchart of the if loop
assignment3;
assignment4;
...
Use of if construct

40
 if AND if-else CONSTRUCTS

Reg[7:0] a;
Reg c;
always@(posedge clk)
begin
c = a[0];
a = a>>1'b1; // Since the vacated bit of a is filled with a zero, it
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need be
if( c ) a[7] = c;// set only if a[0] =1
end

Ring counter description using the if construct

41
 if AND if-else CONSTRUCTS

..
assignment1;
if(condition)
begin // Alternative 1
assignment2;
assignment3;
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end
else
begin //alternative 2
assignment4;
assignment5;
end
assignment6;
...
...
Flowchart of execution of the if-else loop
Use of the if–else construct

42
 2-to-4 demux module using the if-else-if construct

module demux(a,b,s);
output [3:0]a;
//tst_bench
input b; module tst_demux();
input[1:0]s; reg b;
reg[3:0]a;
always@(b or s)
reg[1:0]s;
begin wire[3:0]a;
if(s==2'b00) demux d1(a,b,s);
begin
initial
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a[2'b0]=b;
a[3:1]=3'bZZZ; b=1'b0;
end always
else if(s==2'b01)
begin
begin
a[2'd1]=b; #2 s=2'b00;b=1'b1;
{a[3],a[2],a[0]}=3'bZZZ; #2 s=2'b00;b=1'b0;
end
else if(s==2'b10)
#2 s=2'b01;b=1'b0;
begin #2 s=2'b10;b=1'b1;
a[2'd2]=b; #2 s=2'b11;b=1'b0;
{a[3],a[1],a[0]}=3'bZZZ;
end
end
else initial
begin $monitor("t=%0d, s=%b,b=%b,output =%b",
a[2'd3]=b;
a[2:0]=3'bZZZ;
$time,s,b,a);
end initial #30 $stop;
end endmodule
endmodule

43
 2-to-4 demux module using the if-else-if construct

//output
# t=0, s=xx,b=0,output a=0zzz
# t=2, s=00,b=1,output a=zzz1
# t=4, s=00,b=0,output a=zzz0
# t=6, s=01,b=0,output a=zz0z
# t=8, s=10,b=1,output a=z1zz
# t=10, s=11,b=0,output a=0zzz
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synthesized circuit of the 2-to-4 demux module

44
 assign– deassign CONSTRUCT

• A behavior block is activated by the event at the beginning.

• A proper operation demands that all variables with assignments within the block are to be included in
• the sensitivity list.
• The assign – deassign constructs allow continuous assignments within a behavioral block
• always@(posedge clk) a = b;
• By way of execution, at the positive edge of clk the value of b is assigned to variable a, and a remains frozen
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at that value until the next positive edge of clk.

• Changes in b in the interval are ignored.
• As an alternative, consider the block always@(posedge clk) assign c = d;
• Here at the positive edge of clk, c is assigned the value of d in a continuous manner; subsequent changes in d
are directly reflected as changes in variable c:
• The assignment here is akin to a direct (one way ) electrical connection to c from d established at the positive
edge of clk.
• Again consider an enhanced version of the above block as
• always
• begin
• @(posedge clk) assign c = d;
• @(negedge clk) deassign c;
• end

45
 2 to 4 Demux through Procedural Continuous Assignment

//an alternate realization of the demux using the module tst_demux1();

assign construct reg b;
module demux1(a0,a1,a2,a3,b,s); reg[1:0]s;
output a0,a1,a2,a3; demux1 d2(a0,a1,a2,a3,b,s);
input b; initial begin b=1'b0;s=2'b0; end
input [1:0]s; always
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reg a0,a1,a2,a3; begin

always@(s) #1 s=s+1'b1;
if(s==2'b00) $display("t=%0d, s=%b, b=%b, {a0,a1,a2,a3}
assign {a0,a1,a2,a3}={b,3'oz}; =%b",$time,s,b,{a0,a1,a2,a3});
else if(s==2'b01) #1b=~b;
assign {a0,a1,a2,a3}={1'bz,b,2'bz}; $display("t=%0d, s=%b, b=%b, {a0,a1,a2,a3}
else if(s==2'b10) =%b",$time,s,b,{a0,a1,a2,a3});
assign {a0,a1,a2,a3}={2'bz,b,1'bz}; end
else if(s==2'b11) initial #14 $stop;
assign {a0,a1,a2,a3}={3'oz,b}; endmodule
endmodule

46
 2 to 4 Demux through Procedural Continuous Assignment

//output
# t=1, s=01, b=0, {a0,a1,a2,a3} =0zzz
# t=2, s=01, b=1, {a0,a1,a2,a3} =z0zz
# t=3, s=10, b=1, {a0,a1,a2,a3} =z1zz
# t=4, s=10, b=0, {a0,a1,a2,a3} =zz1z
# t=5, s=11, b=0, {a0,a1,a2,a3} =zz0z
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# t=6, s=11, b=1, {a0,a1,a2,a3} =zzz0

# t=7, s=00, b=1, {a0,a1,a2,a3} =zzz1
# t=8, s=00, b=0, {a0,a1,a2,a3} =1zzz
# t=9, s=01, b=0, {a0,a1,a2,a3} =0zzz
# t=10, s=01, b=1, {a0,a1,a2,a3} =z0zz
# t=11, s=10, b=1, {a0,a1,a2,a3} =z1zz
# t=12, s=10, b=0, {a0,a1,a2,a3} =zz1z
# t=13, s=11, b=0, {a0,a1,a2,a3} =zz0z

47
 D Flip-Flop through assign – deassign Constructs

module dffassign(q,qb,di,clk,clr,pr);
output q,qb;
input di,clk,clr,pr;
reg q;
assign qb=~q;
always@(clr or pr)
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begin
if(clr)assign q = 1'b0;//asynchronous clear and
if(pr) assign q = 1'b1;// preset of FF overrides
else deassign q;// the synchronous behaviour
end
always@(posedge clk)
q = di;//synchronous (clocked)value assigned to q
endmodule

48
 D Flip-Flop through assign – deassign Constructs

//test-bench //output
module dffassign_tst(); # t=0, clk=0, clr=1, pr=0, di=0, q=0
reg di,clk,clr,pr; # t=2, clk=1, clr=0, pr=0, di=0, q=0
wire q,qb; # t=4, clk=0, clr=0, pr=0, di=1, q=0
dffassign dd(q,qb,di,clk,clr,pr); # t=6, clk=1, clr=0, pr=0, di=1, q=1
initial # t=8, clk=0, clr=0, pr=0, di=0, q=1
begin # t=10, clk=1, clr=0, pr=0, di=0, q=0
clr=1'b1;pr=1'b0;clk=1'b0;di=1'b0; # t=12, clk=0, clr=0, pr=0, di=1, q=0
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end # t=14, clk=1, clr=0, pr=0, di=1, q=1

always # t=16, clk=0, clr=0, pr=1, di=0, q=1
begin # t=18, clk=1, clr=0, pr=1, di=0, q=1
#2 clk=~clk;clr=1'b0; # t=20, clk=0, clr=0, pr=0, di=1, q=1
end # t=22, clk=1, clr=0, pr=0, di=1, q=1
always # t=24, clk=0, clr=0, pr=0, di=0, q=1
# 4 di =~di; # t=26, clk=1, clr=0, pr=0, di=0, q=0
always # t=28, clk=0, clr=0, pr=0, di=1, q=0
#16 pr=1'b1; # t=30, clk=1, clr=0, pr=0, di=1, q=1
always # t=32, clk=0, clr=0, pr=1, di=0, q=1
#20 pr =1'b0; # t=34, clk=1, clr=0, pr=1, di=0, q=1
initial $monitor("t=%0d, clk=%b, clr=%b, pr=%b, # t=36, clk=0, clr=0, pr=1, di=1, q=1
di=%b, q=%b ", $time,clk,clr,pr,di,q); # t=38, clk=1, clr=0, pr=1, di=1, q=1
initial #46 $stop; # t=40, clk=0, clr=0, pr=0, di=0, q=1
endmodule # t=42, clk=1, clr=0, pr=0, di=0, q=0
# t=44, clk=0, clr=0, pr=0, di=1, q=0

49
 repeat CONSTRUCT

The repeat construct is used to repeat a specified block a specified number of times.

...
…
always
repeat (a)
begin
begin
repeat(n-1'b1)
assignment1;
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begin
assignment2;
@(posedge clk)
… begin
end out = m(mar);
… mar = mar + 1'b1;
Structure of a repeat block end
end
end

A block in a module to output n successive bytes using the repeat construct.

50
 repeat construct

module trial_8b;
reg[7:0] m[15:0];
integer i; # t=32, i=7, m[i]=56
reg clk; # t=36, i=6, m[i]=48
always
begin # t=40, i=5, m[i]=40
repeat(8) # t=44, i=4, m[i]=32
begin
# t=48, i=3, m[i]=24
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@(negedge clk)
m[i]=i*8; # t=52, i=2, m[i]=16
i=i+1;
End # t=56, i=1, m[i]=8
repeat(8) # t=60, i=0, m[i]=0
begin
@(negedge clk)
i=i-1;
$display("t=%0d, i=%0d, m[i]=%0d", $time,i,m[i]); Results of simulating the test bench
end
end
initial
begin
clk = 1'b0;
i=0;
#70 $stop;
end
always #2 clk=~clk;
endmodule

51
 for LOOP

The for loop in Verilog is quite similar to the for loop in C

Structure of the for loop Flowchart of execution of the for loop

....
for(assignment1; expression; assignment 2)
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statement;
...

1. Execute assignment1.
2. Evaluate expression.
3. If the expression evaluates to the true state (1), carry out
statement. Go to step 5.
4. If expression evaluates to the false state (0), exit the loop.
5. Execute assignment2. Go to step 2

52
 for construct to load a memory block

module trial_8a;
reg[7:0] m[15:0];
integer i;
reg clk; //Simulation results
always # t=32, i=0, m[i]=0
begin # t=36, i=1, m[i]=8
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for(i=0;i<8;i=i+1) # t=40, i=2, m[i]=16

@(negedge clk) # t=44, i=3, m[i]=24
m[i]=i*8; # t=48, i=4, m[i]=32
for(i=0;i<8;i=i+1) # t=52, i=5, m[i]=40
@(negedge clk) # t=56, i=6, m[i]=48
$display("t=%0d, i=%0d, m[i]=%0d", $time,i,m[i]); # t=60, i=7, m[i]=56
end
initial clk = 1'b0;
always #2 clk=~clk;
initial #70 $stop;
endmodule

53
 An adder module using the for loop

module addfor(s,co,a,b,cin,en); //testbench

output[7:0]s; module tst_addfor();
output co; wire [7:0]s;
input[7:0]a,b; wire co;
reg [7:0]a,b;
input en,cin; reg en,cin;
reg[8:0]c; addfor add(s,co,a,b,cin,en);
reg co; always #2 en=~en;
reg[7:0]s;
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initial
integer i; begin
always@( posedge en ) #0 en=1'b0;
#1 cin=1'b0;a=8'h01;b=8'h00;
begin #2 cin=1'b0;a=8'h01;b=8'h00;
c[0] =cin; #2 cin=1'b0;a=8'h01;b=8'h01;
for(i=0;i<=7;i=i+1) #2 cin=1'b0;a=8'h01;b=8'h01;
begin #2 cin=1'b1;a=8'h01;b=8'h02;
{c[i+1],s[i]}=(a[i]+b[i]+c[i]); #2 en=1'b1;cin=1'b1;a=8'h01;b=8'h03;
end #2 cin=1'b0;a=8'h01;b=8'h09;
#2 cin=1'b1;a=8'h01;b=8'h09;
co=c[8]; #2 cin=1'b0;a=8'hff;b=8'hff;
end #2 cin=1'b1;a=8'hff;b=8'hff;
endmodule #2 cin=1'b1;a=8'hff;b=8'hff;
end
initial $monitor( "t=%0d, en = %b, cin = %b, a = %0h, b
= %0h, s = %0h, co = %b ",$time,en,cin,a,b,s,co);
initial #30 $stop;
endmodule

54
 An adder module using the for loop

Results of simulating the test bench

# t=0, en = 0, cin = x, a = x, b = x, s = x, co = x
# t=1, en = 0, cin = 0, a = 1, b = 0, s = x, co = x
# t=2, en = 1, cin = 0, a = 1, b = 0, s = 1, co = 0
# t=4, en = 0, cin = 0, a = 1, b = 0, s = 1, co = 0
# t=5, en = 0, cin = 0, a = 1, b = 1, s = 1, co = 0
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# t=6, en = 1, cin = 0, a = 1, b = 1, s = 2, co = 0
# t=8, en = 0, cin = 0, a = 1, b = 1, s = 2, co = 0
# t=9, en = 0, cin = 1, a = 1, b = 2, s = 2, co = 0
# t=10, en = 1, cin = 1, a = 1, b = 2, s = 4, co = 0
# t=11, en = 1, cin = 1, a = 1, b = 3, s = 4, co = 0
# t=12, en = 0, cin = 1, a = 1, b = 3, s = 4, co = 0
# t=13, en = 0, cin = 0, a = 1, b = 9, s = 4, co = 0
# t=14, en = 1, cin = 0, a = 1, b = 9, s = a, co = 0
# t=15, en = 1, cin = 1, a = 1, b = 9, s = a, co = 0
# t=16, en = 0, cin = 1, a = 1, b = 9, s = a, co = 0
# t=17, en = 0, cin = 0, a = ff, b = ff, s = a, co = 0
# t=18, en = 1, cin = 0, a = ff, b = ff, s = fe, co = 1
# t=19, en = 1, cin = 1, a = ff, b = ff, s = fe, co = 1
# t=20, en = 0, cin = 1, a = ff, b = ff, s = fe, co = 1
# t=22, en = 1, cin = 1, a = ff, b = ff, s = ff, co = 1
# t=24, en = 0, cin = 1, a = ff, b = ff, s = ff, co = 1
# t=26, en = 1, cin = 1, a = ff, b = ff, s = ff, co = 1
# t=28, en = 0, cin = 1, a = ff, b = ff, s = ff, co = 1

55
 THE disable CONSTRUCT

 There can be situations where one has to break out of a block or loop.
 The disable statement terminates a named block or task.
 Control is transferred to the statement immediately following the block.
 Conditional termination of a loop, interrupt servicing, etc., are typical contexts for its use.
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 Often the disabling is carried out from within the block itself.
 The disable construct is functionally similar to the break in C

56
 An OR gate module to demonstrate the use of the disable construct

module or_gate(b,a,en); //test-bench

module tst_or_gate();
input [3:0]a; reg[3:0]a;
input en; reg en;
output b; wire b;
reg b; or_gate gg(b,a,en);
initial
integer i;
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begin
always@(posedge en) a = 4'h0;
begin:OR_gate en = 1'b0;
end
b=1'b0; initial begin
for(i=0;i<=3;i=i+1) #2 en=1'b1; #2 a =4'h1; #2 en=1'b0;
if(a[i]==1'b1) #2 en=1'b1; #2 a =4'h2; #2 en=1'b0;
begin #2 en=1'b1; #2 a =4'h0; #2 en=1'b0;
#2 en=1'b1; #2 a =4'h3; #2 en=1'b0;
b=1'b1; #2 en=1'b1; #2 a= 4'h4; #2 en=1'b0;
disable OR_gate; #2 en=1'b1; #2 a=4'hf;
end end
initial $monitor("t=%0d, en = %b, a = %b, b =
end %b",$time,en,a,b);
endmodule initial #60 $stop;
endmodule

57
 An OR gate module to demonstrate the use of the disable construct

//OUTPUT
# t=0, en = 0, a = 0000, b = x
# t=2, en = 1, a = 0000, b = 0
# t=4, en = 1, a = 0001, b = 0
# t=6, en = 0, a = 0001, b = 0
# t=8, en = 1, a = 0001, b = 1
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# t=10, en = 1, a = 0010, b = 1
# t=12, en = 0, a = 0010, b = 1
# t=14, en = 1, a = 0010, b = 1
# t=16, en = 1, a = 0000, b = 1
# t=18, en = 0, a = 0000, b = 1
# t=20, en = 1, a = 0000, b = 0
# t=22, en = 1, a = 0011, b = 0
# t=24, en = 0, a = 0011, b = 0 Synthesized circuit of the OR gate module
# t=26, en = 1, a = 0011, b = 1
# t=28, en = 1, a = 0100, b = 1
# t=30, en = 0, a = 0100, b = 1
# t=32, en = 1, a = 0100, b = 1
# t=34, en = 1, a = 1111, b = 1

58
 while LOOP

while (expression) statement ;

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Flowchart for the execution of the while loop

59
 A module to illustrate the use of while construct

module while2(b,n,en,clk); module tst_while2();

input[7:0]n; reg[7:0]n;
input clk,en; reg en,clk;
output b; wire b;
reg[7:0]a; while2 ww(b,n,en,clk);
reg b; initial
always@(posedge en) begin
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begin n = 8'h10;clk = 1'b1;en = 1'b0;

a=n; #3 en = 1'b1;
while(|a) #60 en = 1'b0;
begin end
b=1'b1; initial $monitor( " t= %0d, output b = %b ,ww.a = %0d
@(posedge clk) ,en = %b ,clk = %b ",$time,b,ww.a,en,clk);
a=a-1’b1; always
end #2 clk =~clk;
b=1'b0; initial #80 $stop;
end endmodule
initial b=1'b0;
endmodule

60
 A module to illustrate the use of while construct

// OUTPUT t= 38, output b = 1 ,ww.a = 7 ,en = 1 ,clk = 0

t= 0, output b = 0 ,ww.a = x ,en = 0 ,clk = 1 t= 40, output b = 1 ,ww.a = 6 ,en = 1 ,clk = 1
t= 2, output b = 0 ,ww.a = x ,en = 0 ,clk = 0 t= 42, output b = 1 ,ww.a = 6 ,en = 1 ,clk = 0
t= 3, output b = 1 ,ww.a = 16 ,en = 1 ,clk = 0 t= 44, output b = 1 ,ww.a = 5 ,en = 1 ,clk = 1
t= 4, output b = 1 ,ww.a = 15 ,en = 1 ,clk = 1 t= 46, output b = 1 ,ww.a = 5 ,en = 1 ,clk = 0
t= 6, output b = 1 ,ww.a = 15 ,en = 1 ,clk = 0 t= 48, output b = 1 ,ww.a = 4 ,en = 1 ,clk = 1
t= 8, output b = 1 ,ww.a = 14 ,en = 1 ,clk = 1 t= 50, output b = 1 ,ww.a = 4 ,en = 1 ,clk = 0
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t= 10, output b = 1 ,ww.a = 14 ,en = 1 ,clk = 0 t= 52, output b = 1 ,ww.a = 3 ,en = 1 ,clk = 1
t= 12, output b = 1 ,ww.a = 13 ,en = 1 ,clk = 1 t= 54, output b = 1 ,ww.a = 3 ,en = 1 ,clk = 0
t= 14, output b = 1 ,ww.a = 13 ,en = 1 ,clk = 0 t= 56, output b = 1 ,ww.a = 2 ,en = 1 ,clk = 1
t= 16, output b = 1 ,ww.a = 12 ,en = 1 ,clk = 1 t= 58, output b = 1 ,ww.a = 2 ,en = 1 ,clk = 0
t= 18, output b = 1 ,ww.a = 12 ,en = 1 ,clk = 0 t= 60, output b = 1 ,ww.a = 1 ,en = 1 ,clk = 1
t= 20, output b = 1 ,ww.a = 11 ,en = 1 ,clk = 1 t= 62, output b = 1 ,ww.a = 1 ,en = 1 ,clk = 0
t= 22, output b = 1 ,ww.a = 11 ,en = 1 ,clk = 0 t= 63, output b = 1 ,ww.a = 1 ,en = 0 ,clk = 0
t= 24, output b = 1 ,ww.a = 10 ,en = 1 ,clk = 1 t= 64, output b = 0 ,ww.a = 0 ,en = 0 ,clk = 1
t= 26, output b = 1 ,ww.a = 10 ,en = 1 ,clk = 0 t= 66, output b = 0 ,ww.a = 0 ,en = 0 ,clk = 0
t= 28, output b = 1 ,ww.a = 9 ,en = 1 ,clk = 1 t= 68, output b = 0 ,ww.a = 0 ,en = 0 ,clk = 1
t= 30, output b = 1 ,ww.a = 9 ,en = 1 ,clk = 0 t= 70, output b = 0 ,ww.a = 0 ,en = 0 ,clk = 0
t= 32, output b = 1 ,ww.a = 8 ,en = 1 ,clk = 1 t= 72, output b = 0 ,ww.a = 0 ,en = 0 ,clk = 1
t= 34, output b = 1 ,ww.a = 8 ,en = 1 ,clk = 0 t= 74, output b = 0 ,ww.a = 0 ,en = 0 ,clk = 0
t= 36, output b = 1 ,ww.a = 7 ,en = 1 ,clk = 1 t= 76, output b = 0 ,ww.a = 0 ,en = 0 ,clk = 1
t= 78, output b = 0 ,ww.a = 0 ,en = 0 ,clk = 0

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 forever LOOP

Repeated execution of a block in an endless manner is best done with the forever loop

module clk;
reg clk, en;
always @(posedge en)
forever#2 clk=~clk;
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initial
begin
clk=1'b0; en=1'b0;#1 clk=1'b1; #4 en=1'b1;#30 $stop;
end
initial $monitor("clk=%b, t=%0d, en=%b ", clk,$time,en);
endmodule

A module to generate a clock waveform using the forever construct

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 PARALLEL BLOCKS

• All the procedural assignments within a begin–end block are executedsequentially.

• The fork–join block is an alternate one where all the assignments are carried out concurrently
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(a) A module with a begin–end block and the simulation results (b) A module with a fork–join block and the simulation results.

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 An example of a fork–join block within a begin–end block

module fk_jn_c; //Simulation results

integer a; # a=x, t=0
initial # a=5, t=5
begin # a=0, t=6
#5 a=5; # a=1, t=7
fork # a=2, t=8
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#1 a=0; # a=3, t=9

#2 a=1;
#3 a=2;
#4 a=3;
#5 $stop;
join
end
initial $monitor ("a=%0d, t=%0d",a,$time);
endmodule

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 Force–release CONSTRUCT

force a = 1'b0;
forces the variable a to take the value 0.
force b = c&d;
forces the variable b to the value obtained by evaluating the
expression c&d.
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Use of the force–release construct in a test bench

...
force a = 1'b0;
force b = c&d;
assignment1;
assignment2;
...
release a;
release b;
...

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 An OR gate module and its test bench to illustrate the use of force– release construct

module or_fr_rl(a,b,c);
module orfr_tst;
input b,c;
reg b,c;wire a;
output a;
initial
wire a,b,c;
begin b=1'b0;
assign a= b|c;
c=1’b0;
initial begin
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#20 $stop;
#1 $display("display:time=%0d, b=%b, c=%b, a=%b", $time,b,c,a);
end
#6 force b=1'b1;
always #3 c = ~c;
#1 $display("display:time=%0d, b=%b, c=%b, a=%b", $time,b,c,a);
or_fr_rl dd(a,b,c);
#6 release b;
endmodule
#1 $display("display:time=%0d, b=%b, c=%b, a=%b", $time,b,c,a);
end
endmodule

# display:time=1, b=0, c=0, a=0

# display:time=8, b=1, c=0, a=1
# display:time=15, b=0, c=0, a=0

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 Use of the event construct in a module A module to illustrate the event construct:

.. module rec(a,ddi,clk);
event change; output[8:1]a;
... input ddi,clk;
always reg[8:1] a;
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... integer j,jj;

. . . 􀁯 change; event buf_ful;
... always for (j=0;j<20;j=j+1) begin
.always@change #0 jj=0;
... repeat(8)@(negedge clk) begin
jj=jj+1;
a[jj]=ddi;
//$display("b=%b",a[jj]);
end
#0 ->buf_ful;
end
endmodule

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 A module to illustrate the event construct

module rec_tst;
reg clk,di; # t=32, aa=01, a=01
integer n,i; # t=64, aa=72, a=72
reg[8:1] aa; # t=96, aa=e3, a=e3
wire [8:1] a;
always #2 clk = ~clk; # t=128, aa=54, a=54
rec rrcc(a,di,clk); # t=160, aa=c5, a=c5
always @(rrcc.buf_ful) # t=192, aa=36, a=36
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$display("t=%0d, aa=%h, a=%h",$time,aa,a);

initial
# t=224, aa=a7, a=a7
for (n=1;n<3000;n=n+113) # t=256, aa=18, a=18
begin # t=288, aa=89, a=89
aa=n;i=0; # t=320, aa=fa, a=fa
repeat(8)@(posedge clk)
begin # t=352, aa=6b, a=6b
i=i+1; # t=384, aa=dc, a=dc
di=aa[i];
//$write("bb=%b",aa[i]);
end
#3 i=0;
end //Why '#3'?
initial clk=1’b0;
initial #400 $stop;
endmodule

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 GMR Institute of Technology

Thank You

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