ECE 515

Design of 3D Integrated Systems

Lecture 20:
Overview of DRAM Design

 3T DRAM

Note: some of the figures in this slide set are adapted from the slide set
of “ Digital Integrated Circuits” by Rabaey et. al., Copyright 2003
1
 3-Transistor DRAM Cell
BL1 BL2
•The cell stores data on
WWL
WWL the gate of the storage
RWL
transistor. Separate read
RWL and control lines are
used.
X •Multiple read-ports may
X M3 VDD-VT be added easily, by
M2 adding read transistors.
M1 BL1 VDD In addition, separate or
CS merged read and write
BL2 V data busses may be used.
VDD-VT

⚕This cell and the other dynamic cells have to be refreshed to

retain the contents of the memory (Refresh cycle: 1-4 msec)
•No constraints on device ratios
㎕Reads are non-destructive
•Value stored at node X when writing a “1”= VWWL - Vtn
Source: http://research.cs.tamu.edu/eda/people/sagar/research/iddqmadeeasy.pdf
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 Charge Sharing in 3T DRAM
 Charge sharing when write “1”

3
 Properties of the 3T-cell
 Reading the 3T-cell contents is non-destructive, i.e.
the data value stored in the cell is not affected by a
read. This is because the operation of this cell does
not rely on charge sharing. For this reason, the 3T-
cell is robust and reliable.

 The value stored on the storage node X when writing

a “1” equal VWWL- VTN. This threshold loss reduces the
current flowing through M2 during a read operation
and increase the read access time. To prevent this,
some design bootstrap the word line voltage, i.e.
raise VWWL to a value higher than VDD.

4
 6T SRAM vs. 3T DRAM

Source: http://www.ece.tamu.edu/~sunil/courses/ee454/notes/9-memory.pdf
5
 3T-DRAM Layout
BL1 BL2
BL2 BL1 GND
WWL
RWL RWL
M3

M3 M2
X
M2
M1
CS WWL
M1

• The total area of the cell is 576λ2 as compared to the 1092 λ2 of the
SRAM cell. In addition further reduction in size can be obtained when
sharing buses with neighboring cells.
• Area reduction mainly due to elimination of contacts and devices.
6
 DRAM Cell Observations

 In the SRAM cell, a heavy area penalty resulted from

cross-coupled inverters. DRAM slowly loses the charge
stored in the cell, but saves significant cell area.
 Since charge will be lost by decay, we need to refresh
the charge periodically (typically every few milli-seconds)
 A refresh operation comprises a read followed by a write.
A refresh is done by reading the stored value, inverting it,
and writing the inverted value back into the cell.
 When writing a “1” into a DRAM cell, a threshold voltage
is lost. This charge loss can be circumvented by
bootstrapping the word lines to a higher value than VDD

7
 DRAM Cell Observations

 1T DRAM requires a sense amplifier for each bit line, due

to charge redistribution read-out.

 DRAM memory cells are single ended in contrast to

SRAM cells.

The read-out of the 1T DRAM cell is destructive; read and

refresh operations are necessary for correct operation.

 Unlike 3T cell, 1T cell requires presence of an extra

capacitance that must be explicitly included in the design.

8
 Sense Amplifier
Idea: Use Sense Amplifier

small
transition s.a.

input output
functions:
 Amplification - essential for 1T DRAM, where the signal
swing would otherwise be restricted to approximately
250 mV
 performance speed-up - compensates for the restricted
fan-out driving capability of the memory cell by
accelerating the bit line transition
 power reduction - reducing signal swing on the bit lines
can eliminate a substantial part of the power dissipation
related to charging and discharging the bit lines. 9
 Sense Amplifier Operation
V BL V (1)

Bit line voltage

during Read-out.
V
PRE
DV(1)

Imposed by the
sensing amplifier
V(0)
Sense amp activated t
Word line activated

• The read-out is destructive, i.e the amount of charges stored in

the cell is modified during the read operation.
• After a read operation, the charge must be restored.
• Read and refresh operations are intertwined in 1T DRAM.

10
 Sensing Parameters in DRAM
• Signal quality degrades gradually
with an increase in density: 1000
– DRAM cell capacitance degraded CD(1F)
V smax (mv)
from 70fF to 30fF (16K)
– Voltage levels have decreased
Q S(1C)
(below 1V is being the norm). 100
C S(1F)
– Conseq: The signal charge stored
on the capa has dropped.
– At the same time, higher
integration generates more noise. 10
– Word to bit line coupling was V DD (V)
already an issue in 80s: closer line Q S = C S V DD / 2
spacing…… V smax = Q S / (C S + C D )
– Also higher speed: increased
switching noise for every new 4K 64K 1M 16M 256M 4G 64G
generation Memory Capacity (bits / chip)

CD Vsmax, Qs and Cs are: bit line cap, Sense signal, cell charge and cell cap 11
 Noise Sources in 1T DRAM
• Source of noises:
– Word-line-to bit-line coupling: When wl selected, charge is injected into
the bit line due to CWBL
– Bit-line-to-bit line coupling: BL run side by side.
– Leakage: cause voltage drop due to p-n junction and subthreshold.
– Soft errors caused by alpha particle
BL substrate Adjacent BL
• Solutions: CWBL
– Smart design turning a -particles
noise into a common
mode signal, WL
– Design Techniques for
reduced leakage. leakage
CS
– Errors corrected through
redundancy and error electrode
correction encoding +
protection against alpha
radiation Ccross
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 Leakage Current in 1T DRAM
• Assume that both WL and BL voltages are 0V, the initial cell voltage is close to Vdd. Consider only the sub-threshold leakage
component.
– Leakage path: Vx  BL

– Which cell storage data determines the data retention time of this DRAM cell, “Vdd” or “0”?

Vdd
BL
WL
Pull down leakage is larger than pull up leakage

Vx
M1

CS

C BL

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 Differential Sensing in DRAM
• Traditionally, DRAM use a reference bit-line to enable differential sensing.
• Benefit: reject common mode noise

Source: bears.ece.ucsb.edu/class/ece224a/Lecture12dram.ppt
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 Differential Sensing in DRAM
Sense amplifier & precharge

• Single twisted bit-line

• Coupling noise on the middle pair is common mode, rejected by sense amp
• Triple twisted bit-line
• Coupling noise on all bit-line pairs are common mode, rejected by sense amp

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 Alpha-particles (or Neutrons)
a -particle
WL V
DD
BL
SiO
2
n1 1 2
1 2
2
1 2
1 2
1 2
1
1 Particle ~ 1 Million Carriers
• Electrons and holes generated by a striking particle diffuse through the
substrate.
• Electrons that reach the edge of the depletion region before
recombining are swept into the storage node by electrical field.
• If enough electrons are collected a “1” stored can change to “0”

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17
 Soft Errors in DRAM
• Non-recurrent and non-
permanent errors
• As feature size
decreases, the charge
stored at each node
decreases (due to
lower node capacitance
and lower Vdd)
• Thus, Qcritical (the charge
necessary to cause a
bit flip) decreases
leading to an increase
in the soft error rate.

Source: http://www.cse.psu.edu/~kxc104/class/cmpen411/15s/lec/C411L23MemoryCore.pdf
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 Redundancy
Row
Redundant Address
rows
Fuse
:
Bank
Redundant
columns
Memory Row Decoder
Array

Column Decoder Column Address

• As the structure is regular, redundant hardware is easily realized

• Defective bit lines in a memory can therefore be replaced by redundant
ones, and the same hold for the word lines.
• Can be achieved by programming a fuse bank once defaults have been
detected.
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Q1: The storage capacitor in a DRAM has a value of C S =
75fF. The circuitry restricts the capacitor voltage to a
value of Vmax = 2.5 V. When the access transistor is off,
the leakage current of the cell is estimated to be 5nA.
a) How many electrons can be stored on Cs?
b) How many fundamental charge units q leave the cell in
0.1 second due to leakage current?
c) Calculate the time needed to completely discharge the
storage capacitor through leakage current.

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Q2: Consider a DRAM cell that has a storage Cs=75fF, Vdd=3.0V,
and Vth=0.65V. The leakage current from the storage capacitor is
estimated to be 500pA. The capacitor has a voltage Vmax across
it when the word line is brought low at time t=0.
a) Calculate the time it takes to discharge the capacitor to 1.0V.
b) Assuming the leakage current is constant for all values of storage
capacitor voltage and that the minimum readable stored voltage is
1V, plot the DRAM hold time as a function of leakage current.
c) From your plot, estimate the maximum leakage allowed for a
hold time of 1msec.
d) Assuming that Vs = 2.5V, what is the maximum bit-line
capacitance, Cbit, that will provide a logic high output to be read
with at least 0.25V on the bit line?

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