Digital Design & Synthesis

Basics of Digital Design

Author: Kyle Gilsdorf Contact Info: [email protected] Website: https://myasucourses.asu.edu

Today, we are going to talk about the following concepts:

Basics of Digital Design (Combinational Elements) AND, OR NOT BOOLEAN algebra (Synchronous Elements) Latches Examples of how timing works Clocks Synchronous Latch Design (Flip-Flop) Positive, Edge, and Level Triggers (schematic representation) Timing Diagrams for Flip-Flops Introduction to Setup/Hold Concepts Discrete & TTL Components AND, OR, NOT, and Flop

Basics of Digital Design Review of Logic Gates [AND]

Lets assume that:

Digital Design & Synthesis

True has the value of 1 or +5 Volts False has the value of 0 or +0 Volts Using transistors we can create a component that performs the AND operation using voltage to represent the logical values. An AND gate is represented in schematic form as seen below:

A B

Transistor Analogy
+5V

C = A & B
AND Logical Operator/Gate
A T T F F (1) (1) (0) (0) B T F T F (1) (0) (1) (0) C T F F F = A & B (1) (0) (0) (0)
+

Switch Analogy
0 1 0 1 Lamp (out)

10K A

10K B out

On = 1 Off = 0 10K

Analogies taken from P. Scherz

Basics of Digital Design Review of Logic Gates [OR]

Lets assume that:

Digital Design & Synthesis

True has the value of 1 or +5 Volts False has the value of 0 or +0 Volts Using transistors we can create a component that performs the OR operation using voltage to represent the logical values. An OR gate is represented in schematic form as seen below: Transistor Analogy A + B

A B

C
10K

+5V

OR Logical Operator/Gate
A T (1) T (1) F (0) F (0) B T (1) F (0) T (1) F (0) C = A + B T (1) T (1) T (1) F (0)
+

Switch Analogy
0 0 1 1 Lamp (out)

A 10K B out 10K

On = 1 Off = 0

3
Analogies taken from P. Scherz

Basics of Digital Design Review of Logic Gates [NOT]

NOT Logical operator/gate X Y = X

Digital Design & Synthesis

Transistor Analogy Switch Analogy

1 0
-

+5V

X T (1) F (0)

Y = X F (0) T (1)

Lamp (out) in On = 1 Off = 0 in 10K

10K out

Analogies taken from P. Scherz

Note: All digital computers are built using ONLY these three gate types: AND, OR, and Inverter. We will show some examples of how more complex gates can be constructed 4 using only these three gates.

Basics of Digital Design Review of Logic Gates [NAND & NOR]

NAND Gate = NOT (AND)
A B A B
A T (1) T (1) F (0) F (0) B T (1) F (0) T (1) F (0)
A & B A & B

Digital Design & Synthesis

NOR Gate = NOT(OR)

A B A B
A T (1) T (1) F (0) F (0) B T (1) F (0) T (1) F (0)
A + B A + B

C = A & B

C = A + B

C = A & B
C = A & B F (0) T (1) T (1) T (1)

C = A + B
C = A + B F (0) F (0) F (0) T (1)
5

Basics of Digital Design Review of Logic Gates [XOR]

A

Digital Design & Synthesis

XOR Gate = AB + AB

A
Y = A + B = AB + AB

B (1) (1) (0) (0) T F T F (1) (0) (1) (0)

C = A ++ B F T T F (0) (1) (1) (0)

T T F F

Basics of Digital Design Boolean Expressions and Math

Commutative a + b = b + a ab = ba Associative (a + b) + c = a + (b + c) (ab) c = a (bc) Distributive a + (bc) = (a + b)(a + c) a(b + c) = (ab) + (ac) Identity a+0=a a*1=a Complement
a b ab a b a a a+b a

Digital Design & Synthesis

a a b a b

ab a b

ab

a+b
7

Basics of Digital Design What if we only use NANDs or NORs

NAND equivalent circuit NOR equivalent circuit

Digital Design & Synthesis

NOT

AND

OR

Basics of Digital Design Review of Storage Elements [Latch]

R Q

Digital Design & Synthesis

Latch Logical Element

S Q

S F F T T

(0) (0) (1) (1)

R F T F T

(0) (1) (0) (1)

Q Q F (0) T (1) INVALID

Q Next State of the Latch Q Present State of the Latch

Basics of Digital Design Review of Storage Elements [Latch]

R Q

Digital Design & Synthesis

Latch Logical Element

S Q

S F F T T

(0) (0) (1) (1)

R F T F T

(0) (1) (0) (1)

Q Q F (0) T (1) INVALID

Q Next State of the Latch Q Present State of the Latch

10

Basics of Digital Design Review of Storage Elements [Latch...]

R
0 X 1 1

Digital Design & Synthesis

X 1

Q
0 0

Write (Store 1)
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Basics of Digital Design Clocks

Falling Edge of Clock
1 0 Hi Low

Digital Design & Synthesis

Rising Edge of Clock

Time

Low Level of Clock

Clock Period

High Level of Clock

Clocks electrical signals that follow a high/low pattern at some fixed period or frequency. Some examples of electronic components that can generate clocks are crystal oscillators and phase locked loops. Clocks are used to make a design synchronous. In digital design we primarily deal with Synchronous Latches as inputs and outputs to 12 combinational logic (more on this later).

Basics of Digital Design Synchronous Latches

S Q CLK Q R CLK S Q S CLK R

Digital Design & Synthesis

To make the latch work synchronously (SET or RESET is only evaluated during the rising edge of the clock), we add NAND gates to the inputs S and R.
Q
Synchronous RS Latch`

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Flip-Flops from Synchronous Latches

A Flip-Flop is a latch that synchronizes the input. The most common type of Flip-Flop used in ASIC design is the Data Flip -Flop .

Basics of Digital Design

Digital Design & Synthesis

D CLK D Q

S CLK R

Synchronous RS Latch`

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Basics of Digital Design Timing for Flip-Flops

Digital Design & Synthesis

There are three variations of flip-flop latch timing available: Level Triggered: Flip can only change state when the clock input is at a specific logic level. Positive-Edge Triggered: Flip flop changes state on the rising (leading) edge of the clock. Negative-Edge Triggered: Flip flop changes state on the falling (trailing) edge of the clock.

CLK

CLK

CLK

Level Triggered

Positive Edge-Triggered

Negative Edge-Triggered
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Basics of Digital Design Timing Diagrams for Flip-Flops

CLK D QLEVEL Q+EDGE Q-EDGE

Digital Design & Synthesis

Note: For the majority of this course (and in most digital designs in the real world) we will be using Positive-Edge Triggered DFFs.

Digital Design & Synthesis

Timing for Flip-Flops

Different triggering types are indicated by different symbols on the clock input.
D CLK Q Level Triggered Q D CLK Q Positive Edge-Triggered Q D CLK Q Negative Edge-Triggered
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Synchronous RS Latch`

Synchronous RS Latch`

Synchronous RS Latch`

Basics of Digital Design Setup and Hold Timing for Flip-Flops...

TSU
CLK D Q+EDGE

Digital Design & Synthesis

TH

TSU Setup Time This is the period of time BEFORE the clock

transition that the input signal must remain stable at in order to be flopped correctly. TH Hold Time This is the period of time AFTER the clock transition that the input signal must remain stable at in order to be flopped correctly.

Basics of Digital Design What does this really mean?

D

Digital Design & Synthesis

Setup Period
CLK D TSU

Hold Period

TH

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Basics of Digital Design Setup/Hold Timing Understanding Check

Which of the following signal are invalid?
IN3 IN2 IN1

Digital Design & Synthesis

Clk

T 20

Basics of Digital Design Basic Structure of a HDL Design

Sequential / Synchronous Logic Asynchronous / Combinational Logic

Digital Design & Synthesis

INPUT S

OUTPU TS

DFF
CLK Q

DFF
CLK Q
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Basics of Digital Design TTL Discrete Components (AND)

SN74LS08.v
module SN74LS08 (A0, B0, // I C0, // O A1, B1, // I C1, // O A2, B2, // I C2, // O A3, B3, // I C3); // O input A0, A1, A2, A3, B0, B1, B2, B3; output C0, C1, C2, C3;
GND

Digital Design & Synthesis

Quad 2-input AND

VCC VCC

Quad 2-input OR
GND

7408, 74LS08, 74LS08, 74F08, 74HC08, etc. Quad 2-input NAND

VCC

7432, 74LS32, 74LS32, 74F32, 74HC32, etc. Quad 2-input NOR

VCC

GND

GND

wire C0, C1, C2, C3; assign assign assign assign C0 C1 C2 C3 = = = = (A0 (A1 (A2 (A3 & & & & B0); B1); B2); B3);

7400, 74LS00, 74LS00, 74F00, 74HC00, etc.

7402, 74LS02, 74LS02, 74F02, 74HC02, etc.

HEX Inverter
VCC

7404, 74LS04, 74F04, 74HC04, etc.

GND

endmodule // SN74LS00

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TTL Chips! SN74LS08 (Quad NAND)

TTL Chips! SN74AC74 (Dual DFF)

TTL Based Edge Detect

VHDL Based Edge Detect (ENTITY DEFINITION...)

entity edge_detect is port( CLK : RESET_B : IN LONG_SIG : IN SHORT_SIG : OUT end entity edge_detect;

IN STD_LOGIC; STD_LOGIC; STD_LOGIC; STD_LOGIC);

architecture implementation of edge_detect is Begin end architecture implementation;

VHDL Based Edge Detect (COMPONENT DEFINITIONS...)

architecture implementation of edge_detect is component SN74AC74 is port ( 1CLR_B : in std_logic; 1D : in std_logic; 1CLK : in std_logic; 1PRE_B : in std_logic; 1Q : out std_logic; 1Q_B : out std_logic; 2CLR_B : in std_logic; 2D : in std_logic; 2CLK : in std_logic; 2PRE_B : in std_logic; 2Q : out std_logic; 2Q_B : out std_logic); end component SN74AC74; component SN74LS08 is port ( A0, A1, A2, A3 : in std_logic; B0, B1, B2, B3 : in std_logic; C0, C1, C2, C3 : out std_logic; end entity SN74LS08; begin end architecture implementation;

VHDL Based Edge Detect (INSTANTIATE THE COMPONENTS)

architecture implementation of edge_detect is begin I_DFF_2 : SN74AC74 port map ( CLR_B_1 => , D_1 => , CLK_1 => , 1PRE_B_1 => , Q => , Q_B_1 => , CLR_B_2 => , D_2 => , CLK_2 => , PRE_B_2 => , Q_2 => , Q_B_2 => ); I_AND_4 : SN74LS08 port map ( A1 => , A2 => , A3 C4 => ); end architecture implementation;

VHDL Based Edge Detect (CONNECT EVERYTHING UP)

architecture implementation of edge_detect is signal my_sig : std_logic; begin I_DFF_2 : SN74AC74 port map ( CLR_B_1 => RESET_B, D_1 => LED1 , CLK_1 => CLK , 1PRE_B_1 => 1 , Q => open , Q_B_1 => my_sig , CLR_B_2 => RESET_B, D_2 => 0 , CLK_2 => CLK , PRE_B_2 => 1 , Q_2 => open , Q_B_2 => open); I_AND_4 : SN74LS08 port map ( A1 => SW1 , B1 => my_sig , C1 => LED1 , C4 => ); end architecture implementation;