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Week 05 Digital Design - 03 Gate Level Minimization 31032020 112400am

The document discusses gate level minimization using NAND and NOR logic gates. It provides details on implementing logic functions using two-level and multi-level NAND/NOR circuits. Graphic symbols and implementation steps are outlined for converting equations to their NAND/NOR equivalents. Examples are also included to demonstrate the process of simplifying logic expressions and designing equivalent NAND/NOR circuits.

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Kamran Wahab
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45 views20 pages

Week 05 Digital Design - 03 Gate Level Minimization 31032020 112400am

The document discusses gate level minimization using NAND and NOR logic gates. It provides details on implementing logic functions using two-level and multi-level NAND/NOR circuits. Graphic symbols and implementation steps are outlined for converting equations to their NAND/NOR equivalents. Examples are also included to demonstrate the process of simplifying logic expressions and designing equivalent NAND/NOR circuits.

Uploaded by

Kamran Wahab
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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Gate Level Minimization

1
NAND implementation

2
NAND Implementation
Two Graphic Symbols

x x x’+y’+z’ = (xyz)’
y (xyz)’ y
z z
AND - Invert Invert - OR

4
NAND – Two Level Implementation
1. (Simplified) Equation must be in Sum-of-Products form. (Two Levels)

2. Draw AND-OR diagram


Assume all variables and their complements are available. i.e. do not
use inverters to take complement of a variable.

3. Replace AND gates with AND-Invert symbol.


Replace OR gates with Invert-OR symbols

4. If an input is directly going into the second level, invert it

5
NAND – Two Level Implementation
 Example
 F(x,y,z) = Σ(1,2,3,4,5,7)
1. Step-1: Simplify and express it in Sum of Products form
 Use K-Map to simplify and convert into sum-of-product form
 F = xy’ + x’y + z
2. Draw an AND-OR diagram

3. Replace AND gates with AND-Invert symbols


 Replace OR gates with Invert-OR symbols

4. Invert the symbol going into the second level

6
Multilevel NAND Circuit
 If three or more levels in the equation, follow these steps.

1. Draw a simple AND-OR diagram


Assume all variables and their complements are available. i.e. do not
use inverters to take complement of a variable.
2. Convert all AND gates to NAND gates with AND-Invert Graphic
symbols
Convert all OR gates to NAND gates with Invert-OR Graphic symbols
3. Check for all the bubbles in the diagram (i.e. must have two bubbles
per connecting line). Compensate all bubbles (with inverter)

7
Multilevel NAND Circuit
 Example:
 F = A(CD + B) + BC’
 Step-1: Draw AND-OR Diagram

 Step-2: AND to NAND, OR to Invert-OR

 Step-3: Compensate Bubbles

8
Multilevel NAND Circuit
 Examples
 F = (AB’ + A’B)(C + D’)

9
NOR Implementation

10
NOR Implementation
Two Graphic Symbols

x x x’.y’.z’ = (x+y+z)’
y (x+y+z)’ y
z z

OR - Invert Invert - AND

11
NOR – Two Level Implementation
1. Equation must be in Product-of-Sum form. (Two Levels)

2. Draw a AND-OR diagram

3. Replace OR gates with OR-Invert symbol.


Replace AND gates with Invert-AND symbols

4. If an input is directly going into the second level, invert it

12
NOR – Two Level Implementation
 Example
 F= (A + B)(C + D)E

13
Multilevel NOR Circuit
 If three or more levels in the equation, follow these steps.

1. Draw a simple AND-OR diagram


2. Convert all OR gates to NOR gates with
OR-Invert Graphic symbols
Convert all AND gates to NAND gates with Invert-AND Graphic
symbols
3. Check for all the bubbles in the diagram. Compensate all bubbles
(with inverter)

14
Multilevel NOR Circuit
 Example:
 F = (AB’ + A’B)(C + D’)

15
Selected Problems

16
Problem 3-16: Simplify the following expression and
implement with two-level NAND circuit
F = AB’ + ABD + ABD’ + A’C’D’ + A’BC’
Step-1: Simplified circuit be in SOP form
F = A + BC’ + C’D’
CD
AB 00 01 11 10

00 1

01 1 1

11 1 1 1 1

10 1 1 1 1

17
Problem 3-16: Simplify the following expression and
implement with two-level NAND circuit
 Step-1: Simplified circuit be in SOP form
 F = A + BC’ + C’D’
 Step-2: Draw AND-OR Diagram

 Step-3: Replace AND with AND-Invert


OR with Invert-OR

 Step-4: Input A is going directly to second level. Invert it.


18
Problem 3-19: Simplify the following expression and
implement with two-level NOR circuit
F(w, x, y, z) = ∑(5,6,9,10)
Step-1: Simplified circuit be in POS form
yz
wx 00 01 11 10

00 0 0 0 0

01 0 1 0 1

11 0 0 0 0

10 0 1 0 1

F’ = w’x’ + wx + y’z’ + yz


F = (w+x)(w’+x’)(y+z)(y’+z’)
19
Problem 3-20: Draw the multiple-level NAND circuit for
the following expression
(AB’ + CD’) + BC(A+B)
 Step-1: Draw AND-OR Diagram

 Step-2: AND to NAND, OR to Invert-OR

 Step-3: Compensate Bubbles

20
Problem 3-22: Convert the following logic diagram into
multiple-level NAND circuit
D'
1 2
Z

D 1
3
CD 1
C 2
2
3
Y
1
3 1 2
2
(C+D)'
C+D 1
3
B 2

2
3
X
1
3
1 2 2

1
3
2
1
3
W
A 2

21

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