Serial Peripheral Interface

(SPI)

By: Dr Mitesh Limachia

• The Serial Peripheral Interface (SPI) Bus is a
synchronous serial data protocol standard named
by Motorola, operates in full duplex mode.

• 4 wires bus protocol (Clock line (1), Data line (2),

Slave select line (1)).
 SPI Bus Characteristics
• One Central device (Master), initiates communication
with all slave devices.

• Master activates the clock signal when wishes to send

the data to slave or request information from the slave.

• Master sends 8 to 16 bits of data to the slave, while the

slave can always able to send a byte size data to the
master.
• Multiple slave devices are connected on the bus
with individual slave select (chip select) lines.

• No addressing mechanism required to select slave.

• Not have acknowledgement mechanism to confirm

receipt of data -- not have flow control.

• SPI Master, not have knowledge of whether slave

exist or Not
SPI Pin Description

Master send information on one line (MOSI)

while samples (read) from another line (MISO).
Contd.

• SCLK — Serial Clock (output from master)

• MOSI — Master Output, Slave Input (output from

master)

• MISO — Master Input, Slave Output (output from

slave)

• SS’ — Slave Select (active low; output from master)

 Pin Name :SCK (Serial Clock)
Type :Input / Output

• The SPI uses clock signal to synchronize the data

transfer across the SPI interface.

• Driven by the master and received by the slave,

The clock is programmable to be active high or
active low.

• The SCK is only active during a data transfer. Any

other time, it is either in its inactive state, or
tri-stated.
Pin Name : MOSI
(Master out Slave in)
Type : Input / Output

• The MOSI signal is a unidirectional signal used to

transfer serial data from the Master to the Slave.

•When a device is a Master, serial data is output on

this signal.

• When a device is a Slave, serial data is input on

this signal.
Pin Name : MISO (Master in Slave out)
Type : Input / Output
• The MISO signal is a unidirectional signal used to
transfer serial data from the slave to the master.

• When a device is a slave, serial data is output on

this signal.

• When a device is a master, serial data is input on

this signal.

• Slave device which is not selected, it has to drive

this signal into high impedance state.
 Pin Name : SSEL (Slave Select)
Type : Input

•Each slave has its own unique slave select signal

input.

• The SSEL’ is an active low signal indicates which

slave is currently selected to participate in a data
transfer.

• The SSEL must be low before data transmission

begin and normally stays low for the duration of the
transmission.

•If the SSEL signal goes high any time during a data
transfer, the transfer is considered to be aborted.
 Operation

• The SPI bus can operate with a single master

device and with one or more slave devices

• SPI bus: Single Master and Single Slave

•Single Master and Multiple Slaves

SS’
 Full Duplex Data Transmission
•Typical hardware setup uses two shift registers to form an
inter-chip circular buffer.

SS’

•Transmissions normally involve two shift registers of some

size, such as eight bits, one in the master and one in the slave;
they are connected in a ring.
• To begin a communication, the master first
configures the Clock, using a frequency less than
or equal to the maximum frequency the slave
device supports.

• The master then pulls the slave select SSEL (SS’)

low for the desired slave.

• The master sends a bit on the MOSI line; the

slave reads it from that same line.

•The slave sends a bit on the MISO line;

the master reads it from that same line
•During each SPI clock cycle, a full-duplex data
transmission occurs.

•After the total 8h clock pulses content of shift

register has been shifted out. Master and slave have
exchanged values.
 Multiple slave Configurations

• Two types of multiple slave configuration:

• Typical SPI bus: Master and independent Slaves

•Daisy-Chained SPI bus: Master and Co-operative

Slaves
 Typical SPI Bus
• With multiple slave devices, an independent SS’
signal is required from the master for each slave
device (3).
• In the independent slave configuration, there is an
independent slave select line (SS’) for each slave. This is
the way SPI is normally used.

• Since the MISO pins of the slaves are connected together,

they are required to be tri-state pins.

•When a slave device is not selected, the slave drives this

signal into high impedance state.
 Daisy-Chained SPI Bus

Daisy-chained SPI bus: Master and Cooperative

Slaves
• Some products with SPI bus are designed to be capable of
being connected in a daisy chain configuration, the first
slave output being connected to the second slave input, etc.

• The SPI port of each slave is designed to send out during

the second group of clock pulses an exact copy of what
it received during the first group of clock pulses.

•Such a feature only requires a single SS’ line from the

master, rather than a separate SS’ for each slave.
 Contd.
• All the slave devices in chain will be involved in a
write or read operation.

• Daisy Chained simplifies the connection by reducing

the length and connections of the data lines.

• Speed would be less.

• It restricts access to a single device in chain.

 Comparison
• Typical SPI Bus- Control each slave separately. Allowing connection
of SPI devices that require different clocking schemes.

• If SPI slaves that operate using different clocks (edges/idle states) , we

can re-programme the master SPI interface before enabling specific SS’
for particular slave. It provides Flexibility.

• Daisy chained SPI Bus- Make sure all the slave use the same clock
edge and idle clock state.
 Data Transmission
Clock polarity and phase

• In addition to setting the clock frequency, the

master can configure the clock polarity and
phase with respect to the data.
 Contd.
• CPOL: Clock Polarity
This governs the initial logic state of the clock
signal.

• CPHA: Clock Phase

This governs the relationship between the data
transitions and the clock transitions. 
 Data Transmission

A timing diagram showing clock polarity and phase

 Contd.
At CPOL=0, the base value of the clock is zero

• For CPHA=0, data are read on the clock's

rising edge and data are changed on a falling
edge.

• For CPHA=1, data are changed on a rising

edge and data are read on the clock's falling
edge.
 Contd.
At CPOL=1, the base value of the clock is one

•For CPHA=0, data are read on clock's falling

edge and data are changed on a rising edge.

•For CPHA=1, data are read on clock's rising

edge and data are changed on a falling edge.
 Data Transmission
• CPHA=0 means data sample (read) on the
leading (first) clock edge

• CPHA=1 means data sample on the trailing

(second) clock edge, regardless of whether that
clock edge is rising or falling.

•For correct data transfer, the CPOL and CPHA

bits must be configured in the same way in the
slave device and the master device.
Programming of SPI
 SPI Control Register 1 (SPI_CR1)

Bit 0 CPHA: Clock phase

0: The first clock transition is the first data capture edge
1: The second clock transition is the first data capture edge

Bit1 CPOL: Clock polarity

0: CK to 0 when idle
1: CK to 1 when idle

Bit 2 MSTR: Master selection

0: Slave configuration
1: Master configuration
 Contd.
Bits 5:3 BR[2:0]: Baud rate control
000: fPCLK/2 001: fPCLK/4 010: fPCLK/8
011: fPCLK/16 100: fPCLK/32 101: fPCLK/64
110: fPCLK/128 111: fPCLK/256

Bit 6 SPE: SPI enable

0: Peripheral disabled 1: Peripheral enabled

Bit 7 LSBFIRST: Frame format

0: MSB transmitted first 1: LSB transmitted first

Bit 11 DFF: Data frame format

0: 8-bit data frame format is selected
1: 16-bit data frame format is selected
 SPI Data Register (SPI_DR)

Bits 15:0 DR[15:0]: Data register

Data to be transmitted or received Data
The data register is split into 2 buffers - one for writing
(Transmit Buffer) and another one for reading
(Receive buffer).
A write to the data register will write into the Tx buffer and
a read from the data register will return the value held in the
Rx buffer.
- When data are written into the SPI_DR register (Tx buffer).
-Data are parallel loaded from the Tx buffer into the 8-bit shift register during
the first bit transmission and then shifted out serially to the MOSI pin.
 Contd.
For the Master receiver, when data transfer is received:
• The Data in shift register is transferred to Rx Buffer.
 SPI Status Register (SPI_SR)

Bit 7 BSY: Busy flag

0: SPI not busy
1: SPI is busy in communication or Tx buffer is not empty. This flag
is set and cleared by hardware.
Bit 1 TXE: Transmit buffer empty
0: Tx buffer not empty 1: Tx buffer empty
Bit 0 RXNE: Receive buffer not empty
0: Rx buffer empty 1: Rx buffer not empty
TXE and RXNE bits are set and cleared by hardware.
• The TXE flag is set on the transfer of data from the Tx Buffer
to the shift register. Note that TXE flag should be ‘1 before
any attempt to write the Tx buffer is made.
• After the last sampling clock edge the RXNE bit is set, a data byte
received in the shift register is moved to the Rx buffer. RxNE=‘1’
• When the SPI_DR register is read, the SPI peripheral returns this
buffered value.
• Clearing of the RXNE bit is performed by reading the SPI_DR
register.
 Configuring the SPI in Master
Transmitter Mode

In the master configuration, the serial clock is generated on the

SCK pin.
Procedure
1. Select the BR[2:0] bits to define the serial clock baud rate (see
SPI_CR1 register).
2. Select the CPOL and CPHA bits to define one of the four
relationships between the data transfer and the serial clock.
3. Set the DFF bit to define 8- or 16-bit data frame format
4. Configure the LSBFIRST bit in the SPI_CR1 register to
define the frame format.
 Contd.
5. The MSTR and SPE bits must be set.

• In this configuration the MOSI pin is a data output and the

MISO pin is a data input.
 Transmit Sequence

• The transmit sequence begins when a byte is written in the

Tx Buffer.
• The data byte is parallel-loaded into the shift register during
the first bit transmission and then shifted out serially to the
MOSI pin.
• The TXE flag is set on the transfer of data from the Tx Buffer
to the shift register .
• A continuous transmit stream can be maintained if the next
data to be transmitted is put in the Tx buffer once the
transmission is started. Note that TXE flag should be ‘1
before any attempt to write the Tx buffer is made.
Pros and Cons
Of
SPI
 Advantages
• Full duplex communication

• Higher throughput than I²C

• Complete protocol flexibility for the bits

transferred
* Not limited to 8-bit words
* Arbitrary choice of message size
 Disadvantages
• Requires more pins on IC packages than
I²C.

• No hardware slave acknowledgment

(the master could be "talking" to nothing and
not know it).

•No hardware flow control

 Disadvantages

• Supports only one master device

• Only handles short distances compared

to RS-232, RS-485, or CAN-bus
 Comparison between I2C & SPI
Parameter I 2C SPI
Speed 100/400 kbps 1MBPS
Number of Pins 2-wire 4-wire
Complexity More Less
Multi Master Yes No
Capability
Reliability (data Higher Lower
transmission)
Flow Control Yes No
More devices on board Preferred Not Preferred

Power Efficiency Lower Higher

(pull-up Resistors)