Debre Berhan University

College of engineering
Electrical & Computer Engineering
Department

CoEng3059: Digital Logic Design

Lecture-6
Counters and its Design
December- 2022
03/18/2023 BY Amanuel A. 1
 Contents
Introduction
Latches, Flip
Shift register flops and its
Types

Excitation
Counters Table

State
Diagram
2
Sate diagram

Design procedure for

synchronized counter

Type of FF

Flip flops

Types of
Counters

Introduction

Contents
• Counters are one of the most widely used logic
components in digital electronic circuits .
In addition to simply counting they can be used
*to increment memory addresses ; and

Counters
*to divide down clock signals amongst a host of other
applications.
 A counter driven by a clock can be used to count the
number of clock cycles.
 Since the clock pulses occur at known intervals, the counter
can be used as an instrument for measuring time and period of
frequency.
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• To divide the counters we will look at into two types:

I. Asynchronous and

Types of
II. Synchronous
When used with respect to counters: whether the flip-flops
holding the states of the circuit are all clocked together
(i.e. synchronously) by a master clock or rather
asynchronously, with each flip-flop clocked by the one
preceding it. 5
Are also known as ripple counters;
Are very simple;

Asynchronous
Use the minimum possible hardware (logic gates);
Employ flip-flops connected serially, with each one
triggering (clocking) the next;
Have an overall count which 'ripples' through, meaning
the overall operation is relatively slow;
Require virtually no design 6
 Use interconnected flip-flops, but all are clocked together by the system
clock;

Synchronous
 Use the outputs from the flip-flops, to determine the next states of
the following flip-flops (rather than simply clocking them);

 Require no settling time due to rippling (as all flip-flops are clocked
synchronously);

 Need designing, to determine how the present state of the circuit must be
used to determine the next state (i.e. count);

 Usually need more logic gates for their implementation.

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 The 'mod' of the counter is the number of states the
counter cycles through before resetting back to its initial state.

Cont’d…
So a binary mod-8 counter has eight count states, from 000 to
111 (e.g. The mod-8 counter actually counts from 0 to 7).
 All of the counters we will look at use flip-flops as the
storage elements that hold the count state. Therefore, a mod-N
counter will need to contain n flip-flops, where 2n>N.

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The simplest counter circuit can be built using T flip-flops b/c the

ASYNCHRONOUS (SERIAL
OR RIPPLE) COUNTERS
toggle feature is naturally suited for the implementation of the
counting operation.

J-K flip-flops can also be used with the toggle property in hand.

Other flip-flops like D or S-R can also be used, but they may lead to
more complex designs.
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Contents
 ASYNCHRONOUS (SERIAL OR RIPPLE) COUNTERS

• The simplest counter circuit can be built using T flip-flops b/c the
toggle feature is naturally suited for the implementation of the
counting operation.
• J-K flip-flops can also be used with the toggle property in hand.
Other flip-flops like D or S-R can also be used, but they may lead to
more complex designs

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Contents
 Cont’d…
 The asynchronous counter is simple and straight forward in operation and construction
and usually requires a minimum amount of hardware.
 In asynchronous counters, each flip-flop is triggered by the previous flip-flop out
put, and hence the speed of operation is limited.
 The first stage of the counter changes its state first with the application of the clock
pulse to the flip-flop and the successive flip-flops change their states in turn causing a
ripple-through effect of the clock pluses
 In fact, the settling time of the counter is the cumulative sum of the individual settling
times of the flip-flops. This type of counters is also called ripple or serial counter.
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 Cont’d…

 Figure shows a 3-bit counter capable

of counting from 0 to 7.
 The clock inputs of the three flip-
flops are connected in cascade.
 The T input of each flip-flop is
connected to a constant 1 Fig a. Logic circuit diagram
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Cont’d…

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Cont’d…

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 Cont’d…
 The above figure shows a timing diagram for the counter. The value of toggles once each

clock cycle.
 The change takes place shortly after the negative edge of the Clock signal. The delay is
caused by the propagation delay through the flip-flop.
 Since the second flip-flop is clocked by , the value of changes shortly after the negative edge
of the signal. Similarly, the value of changes shortly after the negative edge of the signal.
 If we look at the values as the count, then the timing diagram indicates that the counting
sequence is 0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, and so on.
 This circuit is a modulo-8 counter. Since it counts in the upward direction, we call the circuit
an up-counter.
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 Cont’d…

• Table shown the sequence of

binary states that the flip-flops Table1: Count sequence of a 3-bit binary ripple
up-counter
will follow as clock pulses are
applied continuously.
• An n-bit binary counter repeats
the counting sequence for every
(n = number of flip-flops) clock
pulses and has discrete states
from 0 to –1.

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Contents
 3-bit binary asynchronous counter with decoded outputs.

 The 3-bit binary ripple counter

with decoded outputs.
 It consists of the same circuit as
shown in timing diagram with
additional decoding circuitry.
 In decoding the states of a ripple
counter, pulses of one clock
duration will occur at the decoding
gate outputs as the flip-flops
change their state.
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Contents
 Modulus or MOD-Number of the Counter
The counter shown in Figure above has 8 different states. Thus it is a
MOD-8 asynchronous counter.
The Modulus (or MOD-number) of a counter is the total number of unique
states it passes through in each of the complete cycles.
 Modulus = Where n = Number of flip-flops.
The maximum binary number that can be counted by the counter is –1.
Hence, a 3-flip-flop counter can count a maximum of = – 1 =.
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Contents
 3-Bit Binary Ripple Down Counter
 The binary ripple down counter decreases
the count by one, each time a pulse occurs at
the input.
 If you compare this counter with the up-
counter the only difference you will notice is
that, in the down counter the complement
output Q, instead of the normal output, is
connected to the clock input of the next flip-
flop.
 The counter output which is relevant even in
the down counter is the normal output, Q, of
the flip-flops. 29
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Contents
Waveform or timing diagrams for 3-bit binary down-counter.

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Contents
 Up-Down Counters

• The normal and complement

outputs of flip-flops are connected
to AND gates D and E and the
output of the AND gates goes to the
clock input of the next flip-flop via
OR gates F.

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Contents
 SYNCHRONOUS (PARALLEL) COUNTERS

 The ripple or asynchronous counter is the simplest to build, but its highest
operating frequency is limited because of ripple action.
 Each flip-flop has a delay time.
 In ripple counters these delay times are additive and the total “settling” time
for the counter is approximately the product of the delay time of a single
flip-flop and the total number of flip-flops.
 These problems can be overcome, if all the flip-flops are clocked
synchronously, The resulting circuit is known as a synchronous counter.
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 Cont’d…
Synchronous counters can be designed for any count sequence (need not be
straight binary). These can be designed following a systematic approach.

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A 4-bit (MOD-16) synchronous counter
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Contents
 Cont’d…
 A 4-bit synchronous counter with parallel carry is shown in Figure above. In
this circuit the clock inputs of all the flip-flops are tied together so that the
input clock signal may be applied simultaneously to each flip-flop.
 Only the LSB flip-flop A has its T input connected permanently to logic 1
(i.e., VCC), while the T inputs of the other flip-flops are driven by some
combination of flip-flop outputs.
 The T input of flip-flop B is connected to the output of flip-flop A; the T
input of flip-flop C is connected with the AND-operated output of and .
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 Design procedure for synchronized counter

 The following steps are used to design mode N counter

Step-1- state diagram

Step-2- state table
Step-3- state assignment(giving values for state)
Step-4- excitation state from truth table of the flip-flop
Step-5-Excitation map (using k-map)
Step-6- schematic diagram of mode n
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 Cont’d…
 For example to design Mode 3 counter
Step 1-state diagram Step2-state table
PS( previous state) NS (next state)
a
a b
b b c
c c a

Step 3-state assignment PS NS

q1 q0 Q1 Q0
a= 00, b=01, c=10
0 O 0 1
0 1 1 0
1 0 0 0
1 1 d d
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Contents
Step 4-excitation table
PS NS Excitation state
q1 q0 Q1 Q0 J1 K1 J0 K0

0 0 0 1 0 d 1 d
0 1 1 0 d d d 1
1 0 0 0 d 1 0 d
1 1 d d d d d d
Step 5- excitation map
For J1 For K1 For Jo For K
q0 q0 q0 q0
q1 1 q1 d q 1d 1 q1 d d 1

d d 1 d d d 1

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Contents
 Cont’d…
There for from the k-map drown above we can design the
counter with k-map simplified equation
=
==1
=

+5V

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Contents
 REGISTERS
INTRODUCTION
 Registers are the group of flip-flops (single bit storage element).
 The simplest type of register is a data register, which is used for the temporary
storage of data.
 In its simplest form, it consists of a set of N, D flip-flops, all sharing a common
clock.
 All of the digits in the N bit data word are connected to the data register by an N
line “data bus”.
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Contents
 Cont’d…

 Fig bellow shows a four bit data register, implemented with four D flip flops

The data register is said to be a synchronous device, because all the flip flops change
state at the same time.

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 SHIFT REGISTERS

 A common form of register used in many types of logic circuits is a

shift register.
 The function of storage of binary data can be very well performed by a
simple register. Shift registers are required to do much more than that.
 They are required to store binary data momentarily until it is utilized
for instance, by a computer, microprocessor, etc.

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Cont’d…

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 Cont’d…

 Sometimes data is required to be presented to a device in a manner which

may be different from the way in which it is fed to a shift register.
 For instance, shift register can present data to a device in a serial or
parallel form, irrespective of the manner in which it is fed to a shift register
 Data can also be manipulated within the shift register, so that it is
presented to a device in the required form

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Contents
 Cont’d…

 These devices can also shift left or right and it is this capability which
gives them the name of shift register.
 There are two ways to shift data into a register (serial or parallel) and
similarly two ways to shift the data out of the register.
 This leads to the construction of four basic types of registers as shown in
Figures bellow, All of the four configurations are commercially available.

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Contents
 Cont’d…
They are
1) Serial in/Serial out (SISO) – 54/74L91, 8 bits
2) Serial in/Parallel out (SIPO) – 54/74164, 8 bits
3) Parallel in/Serial out (PISO) – 54/74265, 8 bits
4) Parallel in/Parallel out (PIPO) – 54/74198, 8 bits

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Contents
Cont’d…

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 SERIAL-IN–-SERIAL-OUT SHIFT REGISTER

 From the name itself it is obvious that this type of register accepts data
serially, i.e., one bit at a time at the single input line.
 The output is also obtained on a single output line in a serial fashion.
 The data within the register may be shifted from left to right using shift-
left register, or may be shifted from right to left using shift-right register.

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 SERIAL-IN–PARALLEL-OUT REGISTER

 In this type of register, the data is shifted in serially, but shifted out in
parallel.
 To obtain the output data in parallel, it is required that all the output bits are
available at the same time.
 This can be accomplished by connecting the output of each flip-flop to an output
pin.

 Once the data is stored in the flip-flop the bits are available simultaneously .

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 PARALLEL-IN–SERIAL-OUT REGISTER

 In the preceding two cases the data was shifted into the registers in a
serial manner.
 Now can develop an idea for the parallel entry of data into the
register.
 Here the data bits are entered into the flip-flops simultaneously,
rather than a bit-by-bit basis.

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 PARALLEL-IN–PARALLEL-OUT REGISTER

 There is a fourth type of register already mentioned which is designed

such that data can be shifted into or out of the register in parallel.
 In this type of register there is no interconnection between the flip-
flops since no serial shifting is required.
 Hence, the moment the parallel entry of the data is accomplished the
data will be available at the parallel outputs of the register.

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Contents
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