APPLICATION LOGIC DESIGN

OBJECTIVE
 To make trainees aware of Microlok II as a product
for railway signalling.
 To understand Microlok II as a product for railway
signalling.
 To know various hardware used in Microlok II
(MLKII).
 To know various aspects of design, installation,
testing and commissioning of MLKII.
 To configure, design, install, commission and
maintain MLKII.
 To update post commissioning changes in
yard.
 DESIGN

Microlok II Design consists of:

 Interface Design:
Wiring diagram of relays, panels, CT racks, Power supply,
Microlok II card file etc. (Mainly external to MLKII)

 Application Program Design:

Complete Interlocking program, further converted in
conventional circuit for which is easy to understand

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 INPUTS FOR STARTING THE DESIGN
To start design of MLK II based Interlocking
system, Inputs required are:

 Approved Signal Interlocking Plan

 Approved Front Plate Drawing
 Power supply scheme
 Relay room building layout
 CT rack termination
 details
Details of any additional
interlocking

equipment
to be interfaced with MLKII
 APPLICATION PROGRAM DESIGN

 Application Program is nothing but another form

of Interlocking Circuit

 The Design is based on Signal Interlocking Plan, Route

Control Chart & Front Plate Drawing

 Application Program is written in form of

equations called Boolean equations

 All the relays used in conventional circuits are called as

BIT when referred to Application Program
 CONVENTIONAL PI LOGIC

GN, UN GNR, UNR GNCR, UNCR NRR NNR WNR, WRR

Pressed Up Down Up Down Up

WKRs UCR ALSR WLR HR

Up Up Down Down Up

TPRs
Up

RECR RGKE
Down Down

HECR HGKE
Up Up
 CONCEPT OF MLKII APPLICATION LOGIC

GN + UN GN,
GN, UN
UN GNR, UNR GNCR, UNCR NRR NNR WNR, WRR WNR, WRR
Pressed NV I/P Up Down Up Down Up, Vital O/P Relay Up

WKRs WKRs
WKRs UCR ALSR WLR HR HR
Relay Up Up, Vital I/P Up Down Down Up, Vital O/P Relay Up

TPRs TPRs
TPRs
Relay Up Up, Vital I/P

RECR RECR
RECR RGKE INDICATIONS
Relay Down Down Vital I/P Down, NV O/P Control Panel

HECR HECR
HECR HGKE
HGKE
Relay Up Up, Vital I/P Up, NV O/P

THIS PORTION OF THE CIRCUIT IS WRITTEN INSIDE THE MLK II

IN FORM OF BOOLEAN EXPRESSIONS
 COMPARISON OF PI & SSI
CIRCUIT:

 Number of relays used per installation is very

 less MLK II requires relays only for Inputs and
 Outputs All other relays in case of PI are
represented by
Boolean Bits in MLK II Application Logic
GENERAL:

 Less wiring, time of installation

 Testing possible at Factory before actual installation
 If station layouts are standardized, design time can
also be reduced
 Easy maintenance
 SYMBOLS USED IN APPLICATION PROGRAM

* - SERIES
+ - PARALLEL
( - START OF PARALLEL PATH
) - END OF PARALLEL PATH
~ - BACK CONTACT
, - BIT SEPARATION
; - END OF STATEMENT /
SECTION
CONVERSION OF CIRCUIT TO EQUATION

A B C D XYZ

ASSIGN A * B * (~C * D + E) TO XYZ;

APPLICATION LOGIC DESIGN

 APPLICATION PROGRAM TEXT EDITOR

 FILE NAMING

NEXT
APPLICATION PROGRAM DESIGN
Program is divided in various parts
 Local I/O bit definition
 section Serial bit definition
 section Boolean bit definition
 section Timer section Log
 bit definition section
 Constant Definition
 System Configuration
 Numeric section
 Logic Section Logic
 Compilation

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TEXT EDITOR
END
 FILE NAMING

File Title

Application Logic for C1 MLKII

RNTL_C1_D01 Design Version

Factory and Site Testing Version
RNTL_C1_T01 Service Version

RNTL_C1_S01
Application Logic for C2 MLKII

RNTL_C2_D01 Design Version

Factory and Site Testing Version
RNTL_C2_T01 Service Version

RNTL_C2_S01
END
APPLICATION LOGIC

PROGRAM

RANITAL

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 PROGRAM TITLE
PROGRAM TITLE DISPLAYED ON SCROLLING DISPLAY OF MLKII

FOR C1 PROGRAM

MICROLOK_II PROGRAM RNTL_C1_S01;

FOR C2 PROGRAM

MICROLOK_II PROGRAM RNTL_C2_S01;

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 LOCAL BIT DEFINITIONS
BOARD: J1
ADJUSTABLE ENABLE: 1
TYPE: NV.IN32.OUT32
NV.OUTPUT:
1DGKE, 1RGKE, 1UGKE, 1.C1AJKE,
C1HGKE, SH3_OFFKE, SH3_ONKE, SH3AJKE,
SH5_OFFKE, SH5_ONKE, SH5AJKE, 8DGKE,
8RGKE, 8.SH8AJKE, SH8_OFFKE 10HGKE,
,
10RGKE, 10.SH10AJK 12HGKE,
12RGKE, E, SH10_OFFKE, 14DGKE,
12.SH12AJK
14RGKE, UD_DGKE,
E, SH12_OFFKE,
UD_HGKE,
16DGKE, 16RGKE, Note: These Bits are Defined in C1
UID_DGKE, UID_HGKE; Program.

The BITS which are LOCAL INPUT/OUTPUT are defined in this section.

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 LOCAL BIT DEFINITIONS
BOARD: J1
ADJUSTABLE ENABLE: 1
TYPE: NV.IN32.OUT32
NV.INPUT:
1GN, C1GN, SH3GN, SH5GN,
8GN, SH8GN, 10GN, SH10GN,
12GN, SH12GN, 14GN, 16GN,
14ATUN, DD1UN, DD2UN,
CLUN,
DLUN, DMUN, UMUN,
21WN, 22WN, SDUN,
23WN,
SPARE, SPARE,
25WN,
CH1N, CH2N, 28KTN,
CH3N; These 24LXN
Bits are Defined in C1 Program.
No ,
The BITS which are LOCAL INPUT/OUTPUT are defined
te in this section.
:

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 LOCAL BIT DEFINITIONS
BOARD: J1
ADJUSTABLE ENABLE: 1
TYPE: OUT16

OUTPUT:

1DR, 1HR, C1HR, 1BUR,

1CUR, SH3HR, 6DR, 6HR,

SH6HR, 8HR, SH8HR, 12DR,

SH15HR, UD_DR, UID_DR, UID_HHR;

Note: These Bits are Defined in C2 Program.

The BITS which are LOCAL INPUT/OUTPUT are defined in this section.

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 LOCAL BIT DEFINITIONS
BOARD: J7
ADJUSTABLE ENABLE: 1
TYPE: IN16

INPUT:

SH15_OFFECR, SH15_ONECR, UD_DECR, UD_HHECR,

UD_HECR, UID_DECR, UID_HHECR,
UID_HECR,
16NWK1R, 16RWK1R, 17NWK1R, 17RWK1R,
18NWK1R, 18RWK1R, 19NWK1R, 19RWK1R;

Note: These Bits are Defined in C2 Program.

The BITS which are LOCAL INPUT/OUTPUT are defined in this section.

BACK END
 SERIAL SECTION

 Communicate the STATUS of any bit to other compatible

system (VDU, MLKII etc)

 Output BIT from one system becomes Input BIT to other

system and vice a versa

 Output BIT and Input BIT definition sections are different

 The order of BIT definition shall be same in both

systems

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 SERIAL LINK PARAMETERS
LINK: IVSL // ANY USER SELECTED TEXT STRING
ADJUSTABLE ENABLE: 1
PROTOCOL: MICR // GENISYS.SLAVE, GENISYS.MASTER,
OLOK // MICROLOK.SLAVE, MICROLOK.MASTER
.MAS
TER
// PHYSICAL PORT DEFINITIONS

ADJUSTABLE POINT.POINT: 1; // 0-FOR SLAVE PORT, 1-FOR MASTER PORT

PORT: 2; // PORT 1 TO 4
ADJUSTABLE BAUD: 9600; // 150-19200 IN STEPS
STOPBITS: 1; // 1 OR 2 (DEFAULT 1)
ADJUSTABLE PARITY: // ODD, EVEN MARK, SPACE, NONE(DEFAULT
NONE; // 0-280 FOR GENISYS & 8-280 FOR MLK
ADJUSTABLE KEY.OFF.DELAY:
KEY.ON.DELAY: 12;
12;
ADJUSTABLE
// PROTOCOL DEFINITIONS

ADJUSTABLE STALE.DATA.TIMEOUT: 4:SEC; // KEEP DEFAULT VALUE - 4 FOR MICROLOK

// AND 30:SEC FOR GENISYS PROTOCOL)
ADJUSTABLE POLLING.INTERVAL: 50:MSEC; / DEFAULT: 50 MSEC
ADJUSTABLE MASTER.TIMEOUT: / DEFAULT: 500MSEC,
30-5000MSEC - MICROLOK
500:MSEC;// PROTOCOL
30-25000MSEC
// - GENISYS
// PROTOCOL

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 SERIAL LINK PARAMETERS
LINK: NVLMP //(ANY USER SELECTED TEXT STRING)
ADJUSTABLE ENABLE: 1
PROTOCOL: GENIS // GENISYS.SLAVE, GENISYS.MASTER,
YS.SL // MICROLOK.SLAVE, MICROLOK.MASTER
AVE
// PHYSICAL PORT DEFINITIONS

ADJUSTABLE POINT.POINT: 0; // 0-FOR SLAVE PORT, 1-FOR MASTER PORT

PORT: 3; // PORT 1 TO 4
ADJUSTABLE BAUD: 9600; // 150-19200 IN STEPS
STOPBITS: 1; // 1 OR 2 DEFAULT 1
ADJUSTABLE PARITY: // ODD, EVEN MARK, SPACE, NONE(DEFAULT
NONE; // 0-280 FOR GENISYS & 8-280 FOR MLK
ADJUSTABLE KEY.OFF.DELAY:
KEY.ON.DELAY: 64;
64;
ADJUSTABLE
// PROTOCOL DEFINITIONS

ADJUSTABLE STALE.DATA.TIMEOUT: 10:SEC; // DEFAULT VALUE - 4 FOR MICROLOK

// AND 30:SEC FOR GENISYS PROTOCOL
ADJUSTABLE CARRIER.MODE: CONSTANT;// CONSTANT OR KEYED
CRC.SIZE: 16; // 16 OR 24 BITS, DEFAULT:16BITS
ADJUSTABLE

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 SERIAL LINK PARAMETERS
LINK: NVLPC //(ANY USER SELECTED TEXT STRING)
ADJUSTABLE ENABLE: 1
PROTOCOL: GENIS // GENISYS.SLAVE, GENISYS.MASTER,
YS.SL // MICROLOK.SLAVE, MICROLOK.MASTER
AVE
// PHYSICAL PORT DEFINITIONS

ADJUSTABLE POINT.POINT: 0; // 0-FOR SLAVE PORT, 1-FOR MASTER PORT

PORT: 4; // PORT 1 TO 4
ADJUSTABLE BAUD: 9600; // 150-19200 IN STEPS
STOPBITS: 1; // 1 OR 2 DEFAULT 1
ADJUSTABLE PARITY: // ODD, EVEN MARK, SPACE, NONE(DEFAULT
NONE; // 0-280 FOR GENISYS & 8-280 FOR MLK
ADJUSTABLE KEY.OFF.DELAY:
KEY.ON.DELAY: 64;
64;
ADJUSTABLE
// PROTOCOL DEFINITIONS

ADJUSTABLE STALE.DATA.TIMEOUT: 10:SEC; // DEFAULT VALUE - 4 FOR MICROLOK

// AND 30:SEC FOR GENISYS PROTOCOL
ADJUSTABLE CARRIER.MODE: CONSTANT;// CONSTANT OR KEYED
CRC.SIZE: 16; // 16 OR 24 BITS, DEFAULT:16BITS
ADJUSTABLE

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 SERIAL BIT DEFINITIONS
ADDRESS: 20
ADJUSTABLE ENABLE:
1 OUTPUT:

// VITAL SERIAL OUTPUT TO I/O GATHERER MICROLOK

// MAXIMUM 128 OUTPUT BITS (16BYTES) CAN BE DEFINED IN THIS ADDRESS SECTION.

IVSL_COMOK.ISO,

1DR.ISO, 1HR.ISO, C1HR.ISO, 1BUR.ISO,

1CUR.ISO, SH3HR.ISO, 6DR.ISO, 6HR.ISO,

SH6HR.ISO, 8HR.ISO, SH8HR.ISO, 12DR.ISO,

SH15HR.ISO, UD_DR.ISO, UID_DR.ISO, UID_HHR.ISO,

16WNR.ISO, 16WRR.ISO, 17WNR.ISO, 17WRR.ISO,

18WNR.ISO, 18WRR.ISO, 19WNR.ISO, 19WRR.ISO;

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 SERIAL BIT DEFINITIONS
ADDRESS: 20
ADJUSTABLE ENABLE:
1 INPUT:

// VITAL SERIAL INPUT TO I/O GATHERER MICROLOK

// MAXIMUM 128 INPUT BITS (16BYTES) CAN BE DEFINED IN THIS ADDRESS SECTION.

1DECR.ISI, 1HECR.ISI, 1RECR.ISI, C1HECR.ISI,

1UECR.ISI, 6DECR.ISI, 6HECR.ISI, 6RECR.ISI,

8HECR.ISI, 8RECR.ISI, 12DECR.ISI, 12RECR.ISI,

UD_DECR.ISI, UD_HHECR.ISI, UD_HECR.ISI, UID_DECR.ISI;

The BITS which are to be TRANSFERRED between two MLKII systems OR between MLKII and
OPC/MPC are defined in this section.

BACK END
 VITAL SECTION
 Consists complete interlocking logic except button relay and
indication logics

 The names of Vital relays such as HR, DR, RECR, HECR, TPR
etc. are defined in Vital I/O board definition section

 And rest of the relays such as GNR, NRR, NNR, UCR, ALSR
etc. are defined in Vital Boolean bit definition section

 These logics are written as “ASSIGN” statement

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 NON-VITAL SECTION
 Consists button relay logics and indication logics

 The relays such as GNR, UNR and indications

such as RGKE, HGKE, WLKE etc. are defined in
Non-vital I/O board definition section

 Rest of the relays GNCR, UNCR are defined in NV

Boolean bit definition section

 These logics are written as “NV ASSIGN”

statement

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 BOOLEAN BIT DEFINITION
BOOLEAN BITS

1.C1EGNR, C1UCSR, 2.C2EGNR, C2UCSR,

1ANNR, 1BNNR, 1CNNR, C1ANNR,
1ANRR, 1BNRR, 1CNRR, C1ANRR,
OV5NNR, OV6NNR, OV7NNR, OV1_8NNR,
OV5JSLR, OV5JR, OV5SR, OV6JSLR,
16NLR, 16RLR, 17NLR, 17RLR,
1UCR, C1UCR, 2UCR, C2UCR,
1.C1TSR, 2.C2TSR, SH3TSR, SH4TSR,
1.C1ALSR 2.C2ALSR SH3ALSR, SH4ALSR,
, , 1.C1UYR3, 1.C1UYR4,
1.C1UYR1, 1.C1UYR2, CH1RR, CH2LR,
CH1LR,
CPS.STATUSJ2, CH1NR, SYSINITTMR, SYSINITTMR1,
CPSJR,
The BITS which are neither LOCAL INPUT/OUTPUT nor SERIAL INPUT/OUTPUT are defined in this section.

BACK END
 TIMER SECTION

 “Slow to Pick” or “Slow to Release” time delay for

any function are defined in this section

 The definition works as Condenser-Resistor

combination generally used in
conventional installation

 “Slow to Pick” is defined as “SET=1 SEC”

 “Slow to Release” is as “CLEAR=1 SEC”

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 TIMER BIT DEFINITION
TIMER BITS
EW_N.R_CR: SET=0:SEC CLEAR=1:SEC;
EUUYNPR:
SET=0:SEC CLEAR=1:SEC;
OV5JSLR:
OV5JBPR: SET=0:SEC CLEAR=1:SEC;
OV5JR: SET=0:SEC
SET=120:SEC CLEAR=1:SEC;
1.C1JSLR:
1.C1JBPR: SET=0:SEC
CLEAR=0:SEC;
1.C1JR: SET=0:SEC
SET=120:SEC CLEAR=1:SEC;
CPS.STATUSJ2:
SYSINITTMR: SET=0:SEC
CLEAR=1:SEC;
FLASH: SET=130:SEC
SET=700:MSEC
CLEAR=0:SEC;
The BITS that are defined in LOCAL BITS can be defined in this section if that BIT needs to
be CLEAR=2:SEC;
SLOW to PICKUP or SLOW to DROP. CLEAR=0:SEC;
CLEAR=700:MSEC;
BACK END
 LOG BIT DEFINITION
LOG BITS
1.C1EGNR, C1UCSR, 2.C2EGNR, C2UCSR,
1ANNR, 1BNNR, 1CNNR, C1ANNR,
1ANRR, 1BNRR, 1CNRR, C1ANRR,
OV5NNR, OV6NNR, OV7NNR, OV1_8NNR,
OV5JSLR, OV5JR, OV5SR, OV6JSLR,
16NLR, 16RLR, 17NLR, 17RLR,
1UCR, C1UCR, 2UCR, C2UCR,
1.C1TSR, 2.C2TSR, SH3TSR, SH4TSR,
1.C1ALSR, 2.C2ALSR, SH3ALSR, SH4ALSR,
1.C1UYR1, 1.C1UYR2, 1.C1UYR3, 1.C1UYR4,
CH1LR, CH1NR, CH1RR, CH2LR,
CPS.STATUSJ2, CPSJR, SYSINITTMR, SYSINITTMR1,

During the logic process if the STATUS of any BITS is required then that BITS are defined in this section.

END
 CONSTANT BIT DEFINITION

BOOLEAN:
ONE=1; ZERO=0;

NUMERIC:
INSTALLATION_ADDRESS = 51721;
APPLICATION_DATA_VERSION = 07;
EXECUTIVE_SOFTWARE_VERSION = 401;

END
 SYSTEM CONFIGURATION

CONFIGURATION

SYSTEM
ADJUSTABLE DEBUG_PORT_ADDRESS: 1;
DEBUG_PORT_BAUDRATE 19200;
ADJUSTABLE : LOGIC_TIMEOUT: 3000:MSEC; //100MSEC-5SEC
STEP
100MSEC
ADJUSTABLE DELAY_RESET: 100:MSEC;
ADJUSTABLE
//0-10SEC STEP
100MSEC

END
 NUMERIC BIT DEFINITION

USER NUMERIC

CONFIGURATIONELEMENT_ADDRESS: "INSTALLATION ADDRESS";

CONFIGURATIONELEMENT_APPLICATION_DATA_VERSION:
"APPLICATION DATA VERSION";
CONFIGURATIONELEMENT_EXECUTIVE_SOFTWARE_VERSION:
"
EXECUTIVE SOFTWARE
VERSION";

END
 LOGIC SECTION

 Panel PC Change over Logic

 Operator PC Serial Input Timer Logic

 Push Button Logic

 Emergency Operation Push Button Logic

 EGNR & UCSR Logic

 Signal NNR & NRR Logic

 Overlap Logic

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 LOGIC SECTION
 Point NLR & RLR Logic

 Point Chain Logic

 Point WNR & WRR Logic

 Point Detection Logic

 UCR Logic

 TSR Logic

 Signal ALSR, JSLR, UYR Logic

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 LOGIC SECTION

 Point WLR Logic

 Signal HR & DR Logic

 Crank Handle & Siding Control Logic

 Level Crossing Control Logic

 Block Logic

 Axle Counter Reset Logic

 Signal Indication Logic

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 LOGIC SECTION

 Point & Overlap Indication Logic

 Track Circuit Indication Logic

 Signal Failure Alarm Logic

 Point Failure & Button Stuck Alarm Logic

 System Initialization & Link Status Logic

 FCOR Logic

 Cardfile Identification Logic

BACK END
COMPILATION OF APPLICATION PROGRAM
 Program shall be stored as “PROGRAM.ML2” file
name
 Compilation is carried out with help of Microlok II
Compiler
 Result of compilation will be two files viz.
“PROGRAM.MLL”
& “PROGRAM.MLP”
 “MLL” file is a listing file, which gives any errors, warnings,
no. of BITs used, no. of time one bit used and so many other
important information. This also gives unique identification
numbers called as “CHECKSUM” & “CRC”

 “MLP” file is a data file, which is loaded in memory of

CPU
of MLK II using MLK II Maintenance tool

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 COMPILATION TECHNIQUES

4.1 INTRODUCTION

This chapter describes the command line operation of the

Microlok II logic compiler and the formats of its output files.
This chapter also covers the specific consistency checks that
the compiler performs on the user’s application. The compiler
is a 32-bit Windows compatible program. Details of the
program language are included in chapter 3.

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 COMPILATION TECHNIQUES

4.2 DEFAULT EXTENSIONS

If the user does not supply filename extensions,
the compiler will assign the following extensions
by default:

File Type Extension Extension

Application Source ML2
Listing MLL
Application MLP

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 COMPILATION TECHNIQUES
4.3 RUNNING THE COMPILER

The compiler is configured in Text Editor Program. User can run the
compiler by selecting proper compiler option in “Tool” menu of
Editplus Program.

The compiler will return a non-zero value to the command

processor if there were any errors during compilation or if there
was any problem with the form or content of the command line.
Otherwise, it will return zero.

The result of compilation will be displayed at the bottom of

Editplus Program window if Text Editor is configured to do so.

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 COMPILATION TECHNIQUES

4.5 LISTING INFORMATION

The listing file provides information about compiler-generated

information in the application, as well as reports about usage of
various resources defined in the application. The listing will show the
date of compilation, and the version number and date of the
compiler.

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 COMPILATION TECHNIQUES
4.5.1 Source Listing
First in the listing is the source listing. It shows warnings, severe
warnings, and errors as they relate to source lines. The listing also
shows relevant statement numbers assigned by the compiler.
Each line of the source listing has the form:
<line number> [<statement number>] <text of original source
line> If a line does not have an associated statement number, the
<statement number> portion of the line will appear blank. Lines
that
will have statement numbers will be those with ASSIGN,
NV.ASSIGN, EVALUATE, NV.EVALUATE, or IF statements.

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 COMPILATION TECHNIQUES

4.5.1 Source Listing: Cont’d

The compiler generates statement numbers to aid in debugging.
Errors and warnings reported by the executive refer to statements
by statement number.
Warning, severe warning, and error messages in addition to any
additional information that they may generate will be
interspersed between the source listing lines.

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 COMPILATION TECHNIQUES

4.5.2 Application Image Identification

After the source listing, the compiler presents enough

information to correctly match the listing to the application. This
information consists of:

 Target type -- Microlok II or MicroCab II

 CRC of application image as used by the Microlok
II
 Maintenance tool.
Checksum that would be seen on Flash
EPROM programmer.

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 COMPILATION TECHNIQUES

4.5.2.1 I/O Board Address Jumper Settings

The wiring and I/O board address jumper settings are dependent on the
organization of the Microlok II program’s I/O section. To emphasize
this, these settings are listed separately from the rest of the I/O board
information. For each defined board, the compiler lists:
 Board name as defined in the application
 Board type
 A text picture of switch positions drawn with | and -
characters

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 COMPILATION TECHNIQUES

3. Unusual Numeric Summary

To call attention to the numeric variables with non-default

minimum, maximum, error, or initial values, the compiler
generates a table listing the following:

1. Numeric variable name

2. Numeric variable id number
3. Minimum value
4. Maximum value
5. Error value
6. Initial value

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 COMPILATION TECHNIQUES

4.5.4 Unused Variable Summary

In order to call attention to variables that the system or the user
defined but never used in logic, the compiler will generate a list of
such bits. I/O points defined as SPARE will not appear in this list. It
looks like:

<id number> <id name> <bit type>

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 COMPILATION TECHNIQUES

4.5.5 Unassigned User-Defined Variable Summary

In order to call attention to variables that the user defined but were
never assigned a value, the complier will generate a list of
unassigned user-defined variables. This list will not include user
defined INPUTs, because inputs cannot be the object of an ASSIGN
or NV.ASSIGN statement.

The list looks like:

<id number> <id name> <bit type>

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 COMPILATION TECHNIQUES

4.5.6 Unused User-Defined Variable Summary

In order to call attention to variables that the user defined but did
not use, the complier will generate a list of unused user-defined
variables.
The list looks like:
<id number> <id name> <bit type>

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 COMPILATION TECHNIQUES

4.5.7 Bit Usage Summary

Information about each bit used in the system is also displayed in a

table. This table lists the id number and id name. Also listed is the
number of times it is used as a front contact, a back contact, a
block trigger, a table trigger or a coded output.
Variables in numeric blocks may be assigned to multiple times. If
the bit has multiple assignments to it, the next column shows the
number of assignments. If there is only one, this column is blank.
After this, the compiler will list which type of target the variable
is: assign, non-vital assign, input, user item, table or system.

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 COMPILATION TECHNIQUES

Following this is the vitality of the bit. The table will indicate if the bit is
vital or non-vital.
Next the nature of the definition is displayed. It indicates if the bit is an
internal, user
configuration, output or input.
For example, part of a table might look like:

ID# ID Name FRONT BACK BLOCK TABLE CODE ASGN TARG VITAL
14 34R 0 0 0 0 0 ASGN VITAL OUT
123 1ASR 1 3 0 0 0 ASGN VITAL INT
125 TRIG 0 0 1 1 0 ASGN VITAL INT

126 ERROR 0 0 0 0 0 23 NASGN NON INT

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 COMPILATION TECHNIQUES

4.5.9 I/O Board Summary

I/O boards are summarized as the name and type of the board
as well as the state any configuration parameters belonging
to it.
Entries for all boards will show the state of the enable as
defined in the application as well as its fixed or adjustable
status.

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 COMPILATION TECHNIQUES

4.5.10 Comm Link Summary

Comm Links are summarized as the name and protocol of the link as
well as the state any configuration parameters belonging to it.
Entries for all links will show the state of the enable as defined in the
application as well as its fixed or adjustable status.
Also, the enabled state of each of the stations on the link will be
displayed.

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 COMPILATION TECHNIQUES

4.6 COMPILER CHECKS

In the course of processing the source file, the compiler can
generate errors, warnings, and severe warnings. Errors are
generated in response to source code that cannot be interpreted by
the compiler as a meaningful program. Severe warnings are
generated when the user input can be interpreted as a usable
program, but the compiler makes corrections to the source code.
Sever warnings are intended to notify the programmer of what
corrections the compiler has made.
Warnings are generated for inputs that may cause safe, but
unusable behavior.

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 COMPILATION TECHNIQUES
The following are a few examples of source code problems that would
cause the various classes of messages to occur:
Warnings (an application image is generated and can be used): Any
board or link defined as FIXED and disabled.
Severe warnings (an application image is generated): The user must
check any of the following conditions to determine if a problem will
result:
 Non-vital assignment to vital bit.
 Non-vital evaluate to vital numeric.
 Errors (an application image is not
 generated): Syntax errors
 Use of undefined bits

BACK END
 ANY QUESTIONS

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Application Data Modification Training

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