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17CS563 Mod3

This document discusses interrupts, device drivers, and context switching in embedded systems. It defines an interrupt as an event that gets the processor's attention, causing the currently running routine to interrupt and an interrupt service routine (ISR) to execute. An ISR is also called a device driver. Context switching allows multiple tasks to run on a single processor by saving the context of the interrupted routine and loading the new context for the next routine. Direct memory access (DMA) is used to transfer blocks of data between devices and memory without processor involvement, using a DMA controller.

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53 views13 pages

17CS563 Mod3

This document discusses interrupts, device drivers, and context switching in embedded systems. It defines an interrupt as an event that gets the processor's attention, causing the currently running routine to interrupt and an interrupt service routine (ISR) to execute. An ISR is also called a device driver. Context switching allows multiple tasks to run on a single processor by saving the context of the interrupted routine and loading the new context for the next routine. Direct memory access (DMA) is used to transfer blocks of data between devices and memory without processor involvement, using a DMA controller.

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Module 3

Device drivers and interrupts and service mechanism


Interrupts
Interrupt is an event, which invites attention of the processor on occurrence of
some action at hardware or software interrupt instruction event.
In response to the interrupt, the routine or program, which is running presently
interrupts and an interrupt service routine (ISR) executes.
ISR is also called device driver in case of the devices and called exception or
signal or trap handler in case of software interrupts.
Processor executes the program, called interrupt service routine or signal
handler or trap handler or exception handler or device driver, related to input
or output from the port or device or related to a device function on an
interrupt and does not wait and look for the input ready or output completion
or device-status ready or set.
Hardware Interrupts
Examples ─ When a device or port is ready, a device or port generates an
interrupt, or when it completes the assigned action or when a timer overflows
or when a time at the timer equals a preset time in a compare register or on
setting a status flag (for example, on timer overflow or compare or capture of
time) or on click of mice in a computer.

Hardware interrupt generates call to an ISR


Software Interrupts
When software run-time exception condition (for examples, division by 0 or
overflow or illegal opcode detected) the processor-hardware generates an
interrupt, called trap, which calls an ISR.
When software run-time exception condition defined in a program occurs, then
a software instruction (SWI) is executed─ called software interrupt or exception
or signal, which calls an ISR .
Software Interrupts
When software run-time exception condition (for examples, division by 0 or
overflow or illegal opcode detected) the processor-hardware generates an
interrupt, called trap, which calls an ISR.
When software run-time exception condition defined in a program occurs, then
a software instruction (SWI) is executed─ called software interrupt or exception
or signal, which calls an ISR .
Context and Context Switching
An embedded system executes multiple tasks.
Even though there is only one processor multiple task execution can be
achieved by first saving the context and retrieving another context.
Before executing new instructions of the new function, the current program’s
program counter must be saved.
Also status word, registers, and other program-contexts are saved, if not done
automatically by the processor.
Because the program counter, status word register and other registers are
needed in the newly called function.
Context and Context Switching
Getting an address (pointer) from where the new function begins , and loading
that address into the program counter and then executing the called function's
instructions will change the running program at the CPU to a new program.
A context of a program must include program counter as well as the program
status word, stack pointer and may include the processor registers. The context
may be at a register set or at the separate memory block for the stack.
Context Switching
Context Switching
Context switching means saving the context of interrupted routine (or
function) or task and retrieving or loading the new context of the called routine
or task to be executed next.
Interrupt Latency
A period between occurrence of an interrupt and start of execution of the ISR.
The time taken in context switching also included in a period, called interrupt
latency period, Tlat.
Minimum Interrupt-latency period
Time taken for the response and initiating the ISR instructions which includes
context switching time.
Direct Memory Access
A DMA required when a multi-byte data set or a burst of data or a block of data
is to be transferred between the external device and system or two systems
without the processor involvement.
DMAC (DMA Controller)- A single purpose processing unit that facilitates DMA
transfer.
DMA based method useful, when a block of bytes are transferred, for example,
from disk to the RAM or RAM to the disk.
Direct Memory Access
Direct Memory Access
After an ISR initiates and programs the DMAC, the DMAC sends a hold request
to the CPU.
CPU acknowledges that if the system memory buses are free to use.
Three modes of data transfer
Single transfer at a time and then release of the hold on the system bus.
Burst transfer at a time and then release of the hold on the system bus. A burst
may be of a few kB.
Bulk transfer and then release of the hold on the system bus after the transfer
is completed.

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