BASIC VLSI DESIGN

Electronics today is characterized by

reliability,
low power dissipation,
extremely low weight
 low volume low cost
an ability to cope easily with
a high degree of sophistication and
complexity.
 Evoluation of Electronic
Devices
Vacume Tubes upto 1950
Transistors in 1947
Integrated Circuits at the biginning of 1960.
There are four generations depending on the number of transistors
integrated in circuits on a single chip
SSI(Small Scale Integration)
MSI(Medium Scale Integration)
LSI(Large Scale Integration)
VLSI(Very Large Scale Integration)
Moore’s First Law
 The figure sets out what has become known as
"Moore's first law" after predictions made by
Gordon Moore (of Intel) in the 1960s. It may
be seen that his predictions have largely come
true except for an increasing divergence
between "predicted" and "actual" over the last few
years due to problems associated with the
complexities involved in designing and testing
such very large circuits.
 Speed power product
• A common measure of effectiveness is the
speed power product of the basic logic gate
circuit
• of the technology (for nMOS, the Nor gate,
with Nand and Nor gates for CMOS).
• Speed power product is measured in
picojoules (pJ) and is the product of the
gate switching delay in nanoseconds and
the gate power dissipation in milliwatts
 MOSFET
(Metal Oxide Semiconductor Field Effect Transistor)

NMOS devices are formed in a p-type

substrate of moderate doping level.
The source and drain regions are formed by
diffusing N type impurities through suitable
masks into these areas to give the desired n-
impurity concentration and give rise to
depletion regions which extend mainly in the
more lightly doped p-region as shown. Thus,
source and drain are isolated from one
another by two diodes.
 Connections to the source and drain are made by
 a deposited metal layer.
 In order to mak'e a useful device, there must be the capability for establishing and
controlling a current between source and drain.
 this is commonly achieved in one of two ways, giving rise to the enhancement
mode and depletion mode transistors.
nMOS enhancement mode transistor
MOS Transistor Symbols
 nMOS enhancement mode transistor

• in order to establish the channel in the first place

a minimum voltage level of threshold voltage Vt
• Vt must be established between gate and
source
• No current through channel when Vds=0
• when current flows in the channel by applying a
voltage Vds between drain and source.
• There must, of course, be a corresponding IR
drop = Vds along the channel.
• the effective gate voltage is Vg = vgs - Vt
• there will be voltage available to invert the
channel at the drain end so long as
Vgs - Vt>=Vds.
When Vds>Vgs-Vt,an IR drop = Vgs - Vt takes
place over less than the whole length of the channel
so that over part of the channel, near the drain,
there is insufficient electric field available to give
rise to an inversion layer to create the channel.
 nMOS Enhancement mode
• The .channel is, therefore, 'pinched
• off . Diffusion current completes the path from
source to drain
• in this case, causing the channel to exhibit a high
resistance and behave as a constant current
source. This region, known as saturation,
is .characterized by almost constant current for
increase of vds above vds = vgs - Vt
• for enhancement mode devices, V1 = 1 volt for
VDD = 5 V or, in general terms, V1 = 0.2 V DD.
 nMOS
Depletion mode
Transistor
 nMOS Depletion mode
transistor
• For depletion mode devices the channel
is established, due to the implant.
• even when Vgs = 0, and to cause the
channel to cease to exist a negative
voltage Vtd must be applied between gate
and source.
• Vtd is typically<- 0.8 VDD
• the action is similar to that of the
enhancement mode transistor
 nMOS Fabrication
1.A thin wafer cut from a single crystal of silicon of high
purity 75 to 150 mm in diameter and 0.4 mm thick and are
doped with p-impurities
2.A layer of silicon dioxide (Si02), typically 1 micro meter
thick, is grown all over the surface of the wafer to protect the
surface.barrier to dopants

3,The surface is now covered with a photoresist which is

deposited onto the wafer and spun to achieve an even
distribution of the required thickness.

4.The photoresist layer is then exposed to ultraviolet light

nMOS Fabrication
 nMOS Fabrication
5.These areas are subsequently readilyetched
away together with the underlying silicon
dioxide so that the wafer surface is exposed in
the window defined by the mas.

6.The remaining photoresist is removed and a

thin layer of Si02 (0.1 micro m typical) is grown
over the entire chip surface and then polysilicon
is deposited on top of this to form the gate
structure.
Nmos fabrication
nMOS Fabrication
 nMOS Fabrication
 Further photoresist coating and masking
allows the polysilicon to be patterned(as
shown in Step 6) and then the thin oxide is
removed to expose areas into which n-
type impurities are to be diffused to form
the source and drain as shown.
 Thick oxide (Si02) is grown over all again
and is then masked with photoresist and
etched to expose selected are~s of the
polysilicon gate and the drain and source
areas where connections (i.e. contact cuts)
are to be made.
 nMOS Fabrication
The whole chip then has metal (aluminum)
deposited over its surface to a thickness
typically of 1 micro meter. This metal layer
is then masked and etched to form the
required
interconnection pattern.
 nMOS Fabrication
• Processing takes place on a p-doped
silicon crystal wafer on which is grown a
'thick' layer of Si02.
• Mask 1-Pattern Si02 to expose the silicon
surface in areas where paths in the
diffusion layer or gate areas of transistors
are required. Deposit thin oxide over alL
For this reason, this mask is often known as
the 'thinox' mask but some texts refer
to it as the diffusion mask.
 nMOS Fabrication
Mask 2-Pattern the ion implantation within
the thinox region where depletion mode
devices are to be produced-self-aligning.
• Mask 3-Deposit polysilicon over all (I _5
Jlm thick typically), then pattern using
Mask 3. Using the same mask, remove thin
oxide layer where it is not covered by
polysilicon.
• Diffuse n + regions into areas where thin
oxide has been removed. Transistor drains
and sources are thus self-aligning with
respect to the gate structure
 nMOS Fabrication
Mask 4--Grow thick oxide over all and then
etch for contact cuts.
• Mask 5-Deposit metal and pattern with
Mask 5!
• Mask 6-Would be required for the
overglassing process step
 CMOS Fabrication
The p-well Process
• There are a number of approaches to CMOS
fabrication, including the p-well, the n-well,twin-tub,
and the silicon-on-insulator processes.
• the structure consists of an n-type substrate in which
p-devices may be formed by suitable masking and
diffusion and, in order to accommodate n-type
devices a deep p-well is diffused into the n-type
substrate.
• This diffusion must be carried out with special care
since the p-well doping concentration and depth will
affect the threshold voltages as well as the breakdown
voltages of the n-transistors.
The p-wells.act as substrates for then-devices within the
parent n-substrate, and, provided that voltage polarity
restrictions are observed, the two areas are electrically
isolated
The p-well Process
CMOS n-well process
 Twin tub process
• A logical extension of the p-well and n-well
approaches is the twin-tub fabrication process
• Here we start with a substrate of high resistivity n-
type material and then create both .. n-well and p-well
regions.
• Through this process it is possib!e to preserve the
performance of n-transistors without compromising
the p-transistors.
• Doping control is more readily achieved and some
relaxation in manufacturing tolerances results.
• This is particularly important as far as latch-up is
concerned.