VHDL-AMS

Made by :
Amani Mtawaa
&
Islem Hedhli
1
 INTRODUCTION

General structure of a model

Structuring in libraries

Identifiers, Objects and Typing. Operators

conclusion

2
 INTRODUCTION
• VHDL-AMS is a language that was developed as an extension
of the VHDL language to allow modeling and simulation of
analog and mixed (logic-analog) circuits and systems.

• Why Needed?
• Many of today’s designs include at least some continuous
characteristics:
– System design
• Mixed-signal electrical designs (Cell phones, …)
• Mixed electrical/non-electrical designs (Music players,
Digital Cameras, Samand)
• Modeling design environment (Temperature, humidity,
…)
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 INTRODUCTION (2)
– Why Needed?
– Analog design
• Analog behavioral modeling and simulation

– Digital design: As frequency increases, and technology advances

(DSM effects), digital circuits become more analog

• Clock distribution (PLL’s, pulse shapers, oscillators)

• Pad design (buffers, protection circuits)
• Interconnect (become more like transmission lines)
• Logic cells (become more like RF and microwave circuits)
• Designers want a uniform description language

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Overview
• IEEE Std. 1076.1-1999:
– Extension to VHDL to support the description and
simulation of analog and mixed-signal circuits and
systems

• VHDL-AMS = IEEE Std. 1076.1-1999 + IEEE Std. 1076-

1993
– VHDL-AMS is a strict superset of IEEE Std. 1076-1993
– Any model valid in VHDL 1076 is valid in VHDL-AMS
and yields the same simulation results

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 INTRODUCTION

General structure of a model

Structuring in libraries

Identifiers, Objects and Typing. Operators

conclusion

6
General structure of a model
Entity Interfacing / netlist
Déf. connexions (port) signal: digital
terminal: analog, kirchoff
quantity: analog, signal flow
Architecture
Déclaration
Body
Inst.concurrentes
Inst.simultanées Vue interne du modèle
Instanciations
discret-event
continuous time
structurel/hiérarchie
Entity

Architecture

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General structure of a model: Example
ENTITY exemple IS
port (signal sig_ext:in real; terminal vp,vm : electrical);
END exemple;

LIBRARY ressource_lib;

Illustrative example not compilable

USE ressources_lib.ressources_package.ALL;
ARCHITECTURE archi1 OF exemple IS
TYPE list_ex IS (el1,el2,el2);
CONSTANT cst1 : list_ex, k:REAL;
SIGNAL sig1 : BIT, sig2 :INTEGER, sig3 : REAL;
QUANTITY vbias ACROSS ibias THROUGH vp TO vm;
QUANTITY free_quant : REAL;
BEGIN
u1:ENTITY model_externe(archi_du_modele)
GENERIC MAP(100.0e3,5.0) PORT MAP(vp,vm,sig1);
free_quant == 3.0*sinus( k * now );
ibias == free_quant’dot;
p1:PROCESS
variable x : real := 5.5;
BEGIN
wait on sig3 until sig2 > 3 for 25 ms;
x := 2*x ;
sig_ext <= sig3 after 1 ms;
END PROCESS;
END archi1;
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General structure of a model:

Supported by the simulator

Entity
Sim anal. Sim num.
Architecture
Tsim

E+A E+A CS1 SS1 {}Equa.Diff {}Equa.Log

CS2 SS2 NL (SS) (CS)
SS1
CS3 SS3
E+A E+A ... ... Produit des ASP Produit des
{valeurs i(t),v(t)} événements

CS1 SS
CS1 CS : concurrent statement
CS2 1
CS2 SS : simultaneous statement
SS
E+A : Entity + Architecture
2
SS
3
... 9
 INTRODUCTION

General structure of a model

Structuring in libraries

Identifiers, Objects and Typing. Operators

Identifiers, Objects and Typing. Operators

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Structuring in libraries
• No long description
• Small and hierarchical units
• Compilable part = Design
• unit Complex system = team Need for rigorous
methodology
• A compilation that results Updating a working library
(WORK)
• Resource library (project, supplier, test, ...)
LIBRARY ressource_lib;
USE ressource_lib.pack_lib.ALL;

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Library structuring: Design units
•
Model: ENTITY (UC) + ARCHITECTURE (UC)
several ARCHITECTURE possible by ENTITY

• Often used and shared code: PACKAGE package (UC)

+ PACKAGE BODY (UC
view ext. : export internal view: private

•
Effective association of an instance and a compiled
model: CONFIGURATION (UC)
• Libraries contain CUs Method: One file = One Design
Unit

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 INTRODUCTION

General structure of a model

Structuring in libraries

Identifiers, Objects and Typing. Operators

conclusion

13
Identifiers
Object names: identifiers

Sequence of letters and numbers

Starts with a letter, no case sensitive

Possible to apply low lines: Rdf_232

Double low lines, at the beginning, at the end:

Forbidden

Comment: - (until the end of the line)

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Typing

• All objects are typed (strong typing)

• Allows reliable initialization and increases the
verifying power of the compiler
• Families (defines the possible values ​and
operations):
• scalars (only one element carried at a time, orderedinteger, real,
physical
• Listed
• composites (several elements worn at the same
time)array, record
– access
– files
– Possible user types and subtypes
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 Typing: Predefined types (notes)
• Types prédéfinis
– integer TYPE integer IS RANGE integer’low to integer’high;
– real TYPE real IS RANGE real’low to real’high ;
– bit TYPE bit IS (‘0’, ’1’) ;
– std_logic TYPE std_logic IS (‘U’,’0 ’,’1’,’Z’,’X’,’H’,’L’,’W’,’-’) ; (IEEE 1164)
– bit_vector TYPE bit_vector IS ARRAY (natural RANGE<>) of bit ;
– boolean TYPE boolean IS (false, true)
– severity_level TYPE severity_level IS (NOTE,WARNING,ERROR,FAILURE) ;
– character TYPE character IS (NUL, SOH,…, ’a’, ’b’, …, ‘~’,DEL) ;
– string TYPE string IS ARRAY (positive range <>) of character ;
– time TYPE time IS RANGE integer’low TO integer’high UNITS fs;
ps = 1000 fs ; ns = 1000 ps ; us = 1000 ns ;
ms = 1000 us ; sec = 1000 ms ; mn = 60 sec ; hr = 60 mn;
END UNITS ;

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 Typing: Subtypes
subtype_declaration ::=
SUBTYPE subtype_name IS type_names [constraints];

 Allows you to define subsets of values ​while keeping compatibility with

the base type
 SUBTYPE signal_value IS real RANGE -15.0 to 15.0 ;
 Allows you to define resolution functions

SUBTYPE resolved_bit IS resolution_function bit ;

• Predefined subtypes
• natural SUBTYPE natural IS integer RANGE 0 to integer’high;
– positive SUBTYPE positive IS integer RANGE 1 to integer’high;

• Dynamique
SUBTYPE mot IS bit_vector (1 to max) ;(MAX variable)

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Typing: Initialization of objects
• In VHDL-AMS all objects are initialized implicitly or
explicitly
• An object takes the leftmost value of its type
signal A : bit ; -- A vaut ‘0’
signal A : bit := ‘1’; -- A vaut ‘1’
variable B : boolean ; -- B vaut false
quantity Q : real ; -- Q vaut 0.0
• A type can be incompletely defined
TYPE cell ; -- type incomplètement défini
TYPE link IS ACCESS cell ;
TYPE cell is record -- définitions récursive de type
value : index ;
succ : link ;
END RECORD ;

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Les 6 classes d’objets
• The object classes (information transport)
• CONSTANT: (fixed value known during processing)
VARIABLE (sequential / dynamic): modified by
assignment (: =)
• SIGNAL: (concurrent / static) modified by assignment
(<=)
• TERMINAL: allows branch / free analog connections
QUANTITY: participates in simult.stat. (==) is always
of a type from real
• FILE

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Object classes: Constants
• Allows you to store constant values

CONSTANT pi : real := 3.141592 ;

CONSTANT clock_period : time := 20 ns ;
CONSTANT BV0 : bit_vector(15 DOWNTO 0) := (‘1’, ’0 ’,others=> ’0 ’) ;
CONSTANT tt : truth_table := (other => (others => ‘ 0 ’)) ;
CONSTANT mem_bus : memory_bus := (adrr =>X «00AA»,data=>X«FF»,
read => ‘0’, write => ’1 ’, enable => ’1 ’ ) ;

• Can be initialized at the time of use

CONSTANT cst_val : integer := 40 * N ;
with N can only be known at elaboration (define generic) If the constant
declaration is in a function N can be a parameter of it

• Constant with deferred value

CONSTANT cst_val : integer ;
is valid (we do not know the value) declaration in the specification package
assignment in the body of the package (information hiding)

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Object classes: Variables

• Storage and manipulation of values

VARIABLE phase : real := 124.0 ;
VARIABLE clock_period : time := 20 ns ;
VARIABLE var1: integer := function_d_init(…) ;

Affectation et modification : A := B *C + 3.0;

• used in a PROCESS sequential context
• There are shared variables
!!! Non-deterministic programs !!!
!!! Handle with caution

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Object classes: Signal

signal_declaration ::=
SIGNAL signal_name : [fonc_resolution] type [contraintes]
[REGISTER|BUS] [:= init_value];

• Carries the values ​of the event-driven simulator

S <= 3 after 15 ns;
• Model the wires between the doors (symbolic)
Inport <= Outport ;
• Function name in the declaration: signal resolved
several sources possible / conflict resolution (see next
course)
• REGISTER or BUS: guarded signal
 can only be assigned if the GUARD signal is TRUE (seen
below)
• Has a past, a value, a proposed future
the signal driver
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Object classes: Terminal

terminal_declaration ::= terminal identifier_list :

subnature_indication ;

• Allows to name nodes (does not carry a value !!!)

• A nature is defined by two real types
•

NATURE name IS acr ACROSS thr THROUGH ref REFERENCE ;

Across = effort / through = flux
v-i, °C-W, m-N, rad.s-1-N.m, n.A-Wb, Pa-l/s, ...

SUBTYPE v IS real ; SUBTYPE i IS real ;

NATURE electrical IS v ACROSS i THROUGH gnd REFERENCE ;
TERMINAL vp,vm : electrical ;

• Nature vector
•
NATURE elec_vec IS ARRAY(natural RANGE <>) of electrical ;

• Nature record
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Object classes: Quantity

• "Continuous signals" of the analog simulator

• Free Quantity (not attached to a TERMINAL)
QUANTITY Q : real := expression;
Valeur initiale implicite 0.0 (dépend de l’outil)
• Branch Quantity
QUANTITY [across_aspect] [through_aspect] terminal_aspect ;
QUANTITY V12 across I1 through t1 to t2 ;
QUANTITY V1,V2 across t1; -- alias
QUANTITY I1,I2 through t1; -- branches parallèles

• Implicit Quantity

QUANTITY Q : real := expression;

Q’dot, Q’integ existent toujours et sont créées si besoin
QUANTITY QV : real_vector (3  downto 0) ;
QV’dot, QV’integ sont valides

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Quantities in Various Natures
• Electrical
– voltage: across
– current: through
• Translational
– position: across
– force: through
• Thermal
– temperature: across
– power (or heat-flow): through
• Fluidic
– pressure: across
– flow-rate: through

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Object classes: Terminal / Quantity: examples

• terminal t1,t2 : electrical ;

terminal t3, t4 : electrical_vector (1 to 5);

• quantity v12 across i1, i2 through t1 to t2 ;

définit une tension et deux courants

• quantity v31 across i3 through t3 to t2 ;

• quantity v24 across i4 through t2 to t4 ;

• quantity v34 across i5 through t3 to t4 ;

• Define a star system, a triangle system (scalar terminals) Define an N-

phase star, N-delta system (N unknown)

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CONCLUSION:
Highlights of VHDL-AMS

– Inclusion of continuous valued “quantities”

– Allows design entry at the behavioral or structural

levels

– Analog solution based on numerical integration

• Continuous models based on “differential algebraic
equations” (DAE)

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